ccmp25: add Cortex-M33 signed firmware support
Enable signed firmware to prevent unauthenticated code on the Cortex-M33 co-processor by verifying images against OTP-stored keys. https://onedigi.atlassian.net/browse/DEL-9813 Signed-off-by: Arturo Buzarra <arturo.buzarra@digi.com>
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From: Arturo Buzarra <arturo.buzarra@digi.com>
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Date: Fri, 31 Oct 2025 09:26:02 +0100
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Subject: [PATCH] ARM: dts: ccmp25: add signed firmware support for RPROC
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Enable device-tree bindings required to load/authenticate signed
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Cortex-M33 firmware via remoteproc.
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https://onedigi.atlassian.net/browse/DEL-9813
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Signed-off-by: Arturo Buzarra <arturo.buzarra@digi.com>
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---
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core/arch/arm/dts/ccmp25-dvk-rif.dtsi | 12 ++++++++++++
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core/arch/arm/dts/ccmp25-dvk.dts | 4 ++++
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2 files changed, 16 insertions(+)
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diff --git a/core/arch/arm/dts/ccmp25-dvk-rif.dtsi b/core/arch/arm/dts/ccmp25-dvk-rif.dtsi
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index f2f31dcdf..15121de46 100644
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--- a/core/arch/arm/dts/ccmp25-dvk-rif.dtsi
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+++ b/core/arch/arm/dts/ccmp25-dvk-rif.dtsi
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@@ -869,6 +869,8 @@
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&cm33_sram2 {
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st,protreg = <RISABPROT(RIF_DDCID_DIS, RIF_UNUSED, RIF_NSEC, RIF_NPRIV, RIF_CFDIS, RIF_UNUSED, RIF_UNUSED, RIF_UNUSED)>;
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+ access-controllers-conf-default = <&risab4 RISABPROT(RIF_DDCID_DIS, RIF_UNUSED, RIF_NSEC, RIF_UNUSED, RIF_CFEN, RIF_CID2_BF, RIF_CID2_BF, 0)>;
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+ access-controllers-conf-load = <&risab4 RISABPROT(RIF_DDCID_DIS, RIF_UNUSED, RIF_SEC, RIF_PRIV, RIF_CFEN, RIF_CID1_BF, RIF_CID1_BF, RIF_CID1_BF)>;
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};
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&cm33_retram {
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@@ -948,22 +950,32 @@
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&tfm_code {
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st,protreg = <RISAFPROT(RISAF_REG_ID(1), RIF_CID2_BF, RIF_CID2_BF, RIF_UNUSED, RIF_SEC, RIF_ENC_EN, RIF_BREN_EN)>;
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+ access-controllers-conf-default = <&risaf4 RISAFPROT(RISAF_REG_ID(1), RIF_CID2_BF, RIF_CID2_BF, RIF_UNUSED, RIF_NSEC, RIF_ENC_DIS, RIF_BREN_EN)>;
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+ access-controllers-conf-load = <&risaf4 RISAFPROT(RISAF_REG_ID(1), RIF_CID1_BF, RIF_CID1_BF, RIF_PRIV, RIF_SEC, RIF_ENC_DIS, RIF_BREN_EN)>;
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};
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&cm33_cube_fw {
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st,protreg = <RISAFPROT(RISAF_REG_ID(2), RIF_CID0_BF|RIF_CID1_BF|RIF_CID2_BF, RIF_CID0_BF|RIF_CID1_BF|RIF_CID2_BF, RIF_UNUSED, RIF_NSEC, RIF_ENC_DIS, RIF_BREN_EN)>;
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+ access-controllers-conf-default = <&risaf4 RISAFPROT(RISAF_REG_ID(2), RIF_CID2_BF, RIF_CID2_BF, RIF_UNUSED, RIF_NSEC, RIF_ENC_DIS, RIF_BREN_EN)>;
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+ access-controllers-conf-load = <&risaf4 RISAFPROT(RISAF_REG_ID(2), RIF_CID1_BF, RIF_CID1_BF, RIF_PRIV, RIF_SEC, RIF_ENC_DIS, RIF_BREN_EN)>;
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};
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&tfm_data {
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st,protreg = <RISAFPROT(RISAF_REG_ID(3), RIF_CID2_BF, RIF_CID2_BF, RIF_UNUSED, RIF_SEC, RIF_ENC_EN, RIF_BREN_EN)>;
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+ access-controllers-conf-default = <&risaf4 RISAFPROT(RISAF_REG_ID(3), RIF_CID2_BF, RIF_CID2_BF, RIF_UNUSED, RIF_NSEC, RIF_ENC_DIS, RIF_BREN_EN)>;
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+ access-controllers-conf-load = <&risaf4 RISAFPROT(RISAF_REG_ID(3), RIF_CID1_BF, RIF_CID1_BF, RIF_PRIV, RIF_SEC, RIF_ENC_DIS, RIF_BREN_EN)>;
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};
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&cm33_cube_data {
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st,protreg = <RISAFPROT(RISAF_REG_ID(4), RIF_CID0_BF|RIF_CID1_BF|RIF_CID2_BF, RIF_CID0_BF|RIF_CID1_BF|RIF_CID2_BF, RIF_UNUSED, RIF_NSEC, RIF_ENC_DIS, RIF_BREN_EN)>;
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+ access-controllers-conf-default = <&risaf4 RISAFPROT(RISAF_REG_ID(4), RIF_CID2_BF, RIF_CID2_BF, RIF_UNUSED, RIF_NSEC, RIF_ENC_DIS, RIF_BREN_EN)>;
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+ access-controllers-conf-load = <&risaf4 RISAFPROT(RISAF_REG_ID(4), RIF_CID1_BF, RIF_CID1_BF, RIF_PRIV, RIF_SEC, RIF_ENC_DIS, RIF_BREN_EN)>;
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};
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&ipc_shmem {
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st,protreg = <RISAFPROT(RISAF_REG_ID(5), RIF_CID0_BF|RIF_CID1_BF|RIF_CID2_BF, RIF_CID0_BF|RIF_CID1_BF|RIF_CID2_BF, RIF_UNUSED, RIF_NSEC, RIF_ENC_DIS, RIF_BREN_EN)>;
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+ access-controllers-conf-default = <&risaf4 RISAFPROT(RISAF_REG_ID(5), RIF_CID1_BF|RIF_CID2_BF, RIF_CID1_BF|RIF_CID2_BF, RIF_UNUSED, RIF_NSEC, RIF_ENC_DIS, RIF_BREN_EN)>;
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+ access-controllers-conf-load = <&risaf4 RISAFPROT(RISAF_REG_ID(5), RIF_CID1_BF, RIF_CID1_BF, RIF_PRIV, RIF_SEC, RIF_ENC_DIS, RIF_BREN_EN)>;
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};
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&spare1 {
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diff --git a/core/arch/arm/dts/ccmp25-dvk.dts b/core/arch/arm/dts/ccmp25-dvk.dts
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index 7292b9be8..3ce64ccff 100644
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--- a/core/arch/arm/dts/ccmp25-dvk.dts
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+++ b/core/arch/arm/dts/ccmp25-dvk.dts
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@@ -437,6 +437,10 @@
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&m33_rproc {
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status = "okay";
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+ compatible = "st,stm32mp2-m33-tee";
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+ memory-region = <&cm33_cube_fw>, <&cm33_cube_data>,
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+ <&ipc_shmem>, <&tfm_code>, <&tfm_data>,
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+ <&cm33_sram2>;
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};
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&ommanager {
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@ -2,6 +2,8 @@
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# Copyright (C) 2022-2025, Digi International Inc.
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#
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FILESEXTRAPATHS:prepend := "${THISDIR}/${BPN}:"
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# Inherit custom DIGI sign class to skip signing tool and key parsing restrictions
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inherit sign-stm32mp-digi
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@ -17,3 +19,10 @@ SRC_URI = " \
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${OPTEE_GIT_URI};branch=${SRCBRANCH};name=os \
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file://fonts.tar.gz;subdir=git;name=fonts \
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"
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SRC_URI:append:ccmp25 = " \
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${@oe.utils.conditional('TRUSTFENCE_ENABLED', '1' , 'file://0001-ARM-dts-ccmp25-add-signed-firmware-support-for-RPROC.patch', '', d)} \
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"
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# Enable remoteproc OTP public key verification for signed firmware support
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EXTRA_OEMAKE:append:ccmp25 = " ${@oe.utils.conditional('TRUSTFENCE_ENABLED', '1', 'CFG_REMOTEPROC_PUB_KEY_VERIFY=y', '', d)}"
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@ -0,0 +1,32 @@
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From: Arturo Buzarra <arturo.buzarra@digi.com>
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Date: Thu, 30 Oct 2025 14:35:29 +0100
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Subject: [PATCH] ARM: dts: ccmp25: add signed firmware support for RPROC
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Declare only the shared memory used for inter-processor communication
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(including the resource table) to allow remoteproc to load/authenticate signed
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Cortex-M33 firmware.
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https://onedigi.atlassian.net/browse/DEL-9813
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Signed-off-by: Arturo Buzarra <arturo.buzarra@digi.com>
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---
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arch/arm/dts/ccmp25.dtsi | 7 ++-----
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1 file changed, 2 insertions(+), 5 deletions(-)
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diff --git a/arch/arm/dts/ccmp25.dtsi b/arch/arm/dts/ccmp25.dtsi
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index 913eac366b9..51b65f2408a 100644
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--- a/arch/arm/dts/ccmp25.dtsi
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+++ b/arch/arm/dts/ccmp25.dtsi
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@@ -246,11 +246,8 @@
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&m33_rproc {
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mboxes = <&ipcc1 0x100>, <&ipcc1 0x101>, <&ipcc1 2>;
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mbox-names = "vq0", "vq1", "shutdown";
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- memory-region = <&cm33_cube_fw>, <&cm33_cube_data>,
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- <&ipc_shmem_1>, <&vdev0vring0>,
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- <&vdev0vring1>, <&vdev0buffer>,
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- <&cm33_sram2>;
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- st,syscfg-nsvtor = <&a35ss_syscfg 0xa8 0xffffff80>;
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+ compatible = "st,stm32mp2-m33-tee";
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+ memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&ipc_shmem_1>;
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status = "okay";
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};
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@ -13,6 +13,10 @@ SRC_URI += " \
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${@oe.utils.conditional('TRUSTFENCE_SIGN_FIT_STM', '1', 'file://fit_signature.cfg', '', d)} \
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"
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SRC_URI:append:ccmp25 = " \
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${@oe.utils.conditional('TRUSTFENCE_ENABLED', '1' , 'file://0001-ARM-dts-ccmp25-add-signed-firmware-support-for-RPROC.patch', '', d)} \
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"
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install_helper_files() {
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# Install dtbs from UBOOT_DEVICETREE to datadir, so that kernel
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# can use it for signing, and kernel will deploy after signs it.
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@ -0,0 +1,32 @@
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From: Arturo Buzarra <arturo.buzarra@digi.com>
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Date: Thu, 30 Oct 2025 14:15:14 +0100
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Subject: [PATCH] ARM64: dts: ccmp25: add signed firmware support for RPROC
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Declare only the shared memory used for inter-processor communication
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(including the resource table) to allow remoteproc to load/authenticate signed
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Cortex-M33 firmware.
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https://onedigi.atlassian.net/browse/DEL-9813
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Signed-off-by: Arturo Buzarra <arturo.buzarra@digi.com>
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---
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arch/arm64/boot/dts/digi/ccmp25.dtsi | 7 ++-----
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1 file changed, 2 insertions(+), 5 deletions(-)
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diff --git a/arch/arm64/boot/dts/digi/ccmp25.dtsi b/arch/arm64/boot/dts/digi/ccmp25.dtsi
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index 153726203533..89f5bf75fd9f 100644
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--- a/arch/arm64/boot/dts/digi/ccmp25.dtsi
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+++ b/arch/arm64/boot/dts/digi/ccmp25.dtsi
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@@ -346,11 +346,8 @@ &m0_rproc {
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&m33_rproc {
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mboxes = <&ipcc1 0x100>, <&ipcc1 0x101>, <&ipcc1 2>;
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mbox-names = "vq0", "vq1", "shutdown";
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- memory-region = <&cm33_cube_fw>, <&cm33_cube_data>,
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- <&ipc_shmem_1>, <&vdev0vring0>,
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- <&vdev0vring1>, <&vdev0buffer>,
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- <&cm33_sram2>;
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- st,syscfg-nsvtor = <&a35ss_syscfg 0xa8 0xffffff80>;
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+ compatible = "st,stm32mp2-m33-tee";
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+ memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&ipc_shmem_1>;
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status = "okay";
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};
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@ -21,6 +21,10 @@ SRC_URI:append = " \
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${@bb.utils.contains('DISTRO_FEATURES', 'rt', '${RT_FILES}', '', d)} \
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"
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SRC_URI:append:ccmp25 = " \
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${@oe.utils.conditional('TRUSTFENCE_ENABLED', '1' , 'file://0001-ARM64-dts-ccmp25-add-signed-firmware-support-for-RPR.patch', '', d)} \
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"
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# Define RT config fragments per machine
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RT_CONFIG_FRAGS:use-nxp-bsp = " ${WORKDIR}/fragment-nxp-rt.config"
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RT_CONFIG_FRAGS:stm32mpcommon = " \
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