Merge branch 'dey-2.4/master' into 'dey-2.4/maint'
Conflicts: meta-digi-arm/recipes-bsp/u-boot/u-boot-dey_2015.04.bb meta-digi-arm/recipes-digi/trustfence/trustfence-sign-tools_git.bb meta-digi-arm/recipes-kernel/kernel-module-qualcomm/kernel-module-qualcomm.bb meta-digi-arm/recipes-kernel/linux/linux-dey.inc meta-digi-arm/recipes-kernel/linux/linux-dey_4.9.bb meta-digi-dey/recipes-digi/dey-examples/awsiotsdk-demo_git.bb meta-digi-dey/recipes-digi/dey-examples/dey-examples-cryptochip.bb meta-digi-dey/recipes-digi/dey-examples/dey-examples-digiapix.bb meta-digi-dey/recipes-multimedia/gstreamer/gstreamer1.0-plugins-bad_1.12.%.bbappend meta-digi-dey/recipes-multimedia/gstreamer/gstreamer1.0-plugins-base_1.12.%.bbappend meta-digi-dey/recipes-multimedia/gstreamer/gstreamer1.0-plugins-good_1.12.%.bbappend meta-digi-dey/recipes-multimedia/gstreamer/gstreamer1.0_1.12.%.bbappend meta-digi-dey/recipes-multimedia/gstreamer/imx-gst1.0-plugin_4.4.0.bb Signed-off-by: Hector Palacios <hector.palacios@digi.com>
This commit is contained in:
Hector Palacios
commit
8e246b98be
|
|
@ -0,0 +1,33 @@
|
||||||
|
# fsl-eula-unpack2.bbclass provides a mechanism for a) unpacking certain
|
||||||
|
# EULA-licensed archives downloaded by HTTP and b) handling the EULA
|
||||||
|
# acceptance.
|
||||||
|
|
||||||
|
inherit fsl-eula-unpack fsl-eula
|
||||||
|
|
||||||
|
IMX_PACKAGE_VERSION = "${PV}"
|
||||||
|
|
||||||
|
SRC_URI = "${FSL_MIRROR}${IMX_PACKAGE_NAME}.bin;name=${SRC_URI_NAME};fsl-eula=true"
|
||||||
|
|
||||||
|
S = "${WORKDIR}/${IMX_PACKAGE_NAME}"
|
||||||
|
|
||||||
|
# For native apps, insert the user-local sysroot path
|
||||||
|
# For nativesdk apps, insert the correct distro folder
|
||||||
|
D_SUBDIR = ""
|
||||||
|
D_SUBDIR_class-native = "${STAGING_DIR_NATIVE}"
|
||||||
|
D_SUBDIR_class-nativesdk = "/opt/${DISTRO}"
|
||||||
|
|
||||||
|
# SCR is the location and name of the Software Content Register file
|
||||||
|
# relative to ${D}${D_SUBDIR}.
|
||||||
|
SCR = "SCR.txt"
|
||||||
|
|
||||||
|
do_install () {
|
||||||
|
install -d ${D}${D_SUBDIR}
|
||||||
|
cp -r ${S}/* ${D}${D_SUBDIR}
|
||||||
|
rm ${D}${D_SUBDIR}/COPYING
|
||||||
|
if [ ! -f ${D}${D_SUBDIR}/${SCR} ]; then
|
||||||
|
bbfatal "Missing Software Content Register \"${D}${D_SUBDIR}/${SCR}\""
|
||||||
|
fi
|
||||||
|
rm ${D}${D_SUBDIR}/${SCR}
|
||||||
|
}
|
||||||
|
|
||||||
|
FILES_${PN} = "/"
|
||||||
|
|
@ -0,0 +1,29 @@
|
||||||
|
# fsl-eula.bbclass defines a common naming scheme used by the
|
||||||
|
# packing and unpacking mechanisms defined in fsl-eula-pack.bbclass
|
||||||
|
# and fsl-eula-unpack2.bbclass.
|
||||||
|
#
|
||||||
|
# Note that it is not necessary to inherit this class directly. It is
|
||||||
|
# already inherited from fsl-eula-pack.bbclass and fsl-eula-unpack2.bbclass.
|
||||||
|
#
|
||||||
|
# The naming scheme takes into account the fact that a single software
|
||||||
|
# package can create many archives based on the combinations of a) target
|
||||||
|
# versus native/nativesdk components, and b) the target or native architecture.
|
||||||
|
# The naming scheme can be extended through regular bitbake means to allow
|
||||||
|
# configuration-specific archives, as can be seen in fsl-eula-graphics.bbclass.
|
||||||
|
|
||||||
|
# The variable IMX_PACKAGE_NAME gives a unique name for every possible
|
||||||
|
# archive. The variable is built from a combination of the package name ${PN},
|
||||||
|
# the version ${IMX_PACKAGE_VERSION} and the target or native architecture,
|
||||||
|
# ${TARGET_ARCH} or ${BUILD_ARCH}.
|
||||||
|
IMX_PACKAGE_NAME = "${PN}-${IMX_PACKAGE_VERSION}-${TARGET_ARCH}"
|
||||||
|
IMX_PACKAGE_NAME_class-native = "${PN}-${IMX_PACKAGE_VERSION}-${BUILD_ARCH}"
|
||||||
|
IMX_PACKAGE_NAME_class-nativesdk = "${PN}-${IMX_PACKAGE_VERSION}-${BUILD_ARCH}"
|
||||||
|
|
||||||
|
# The variable SRC_URI_NAME gives a unique SRC_URI name option for use in
|
||||||
|
# unpacking recipes derived from fsl-eula-unpack2.bbclass. With this name,
|
||||||
|
# a single unpacking recipe can handle all possible archives. The name is
|
||||||
|
# built from with a combination of target or native architecture,
|
||||||
|
# ${TARGET_ARCH} or ${BUILD_ARCH}, and a native or nativesdk designation.
|
||||||
|
SRC_URI_NAME = "${TARGET_ARCH}"
|
||||||
|
SRC_URI_NAME_class-native = "${BUILD_ARCH}-native"
|
||||||
|
SRC_URI_NAME_class-nativesdk = "${BUILD_ARCH}-nativesdk"
|
||||||
|
|
@ -21,6 +21,8 @@ IMAGE_CMD_boot.vfat() {
|
||||||
BOOTIMG_FILES_SYMLINK="${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${MACHINE}.bin"
|
BOOTIMG_FILES_SYMLINK="${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${MACHINE}.bin"
|
||||||
if [ -n "${KERNEL_DEVICETREE}" ]; then
|
if [ -n "${KERNEL_DEVICETREE}" ]; then
|
||||||
for DTB in ${KERNEL_DEVICETREE}; do
|
for DTB in ${KERNEL_DEVICETREE}; do
|
||||||
|
# Remove potential sub-folders
|
||||||
|
DTB="$(basename ${DTB})"
|
||||||
if [ -e "${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${DTB}" ]; then
|
if [ -e "${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${DTB}" ]; then
|
||||||
BOOTIMG_FILES="${BOOTIMG_FILES} $(readlink -e ${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${DTB})"
|
BOOTIMG_FILES="${BOOTIMG_FILES} $(readlink -e ${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${DTB})"
|
||||||
BOOTIMG_FILES_SYMLINK="${BOOTIMG_FILES_SYMLINK} ${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${DTB}"
|
BOOTIMG_FILES_SYMLINK="${BOOTIMG_FILES_SYMLINK} ${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${DTB}"
|
||||||
|
|
@ -81,6 +83,8 @@ IMAGE_CMD_boot.ubifs() {
|
||||||
BOOTIMG_FILES_SYMLINK="${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${MACHINE}.bin"
|
BOOTIMG_FILES_SYMLINK="${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${MACHINE}.bin"
|
||||||
if [ -n "${KERNEL_DEVICETREE}" ]; then
|
if [ -n "${KERNEL_DEVICETREE}" ]; then
|
||||||
for DTB in ${KERNEL_DEVICETREE}; do
|
for DTB in ${KERNEL_DEVICETREE}; do
|
||||||
|
# Remove potential sub-folders
|
||||||
|
DTB="$(basename ${DTB})"
|
||||||
if [ -e "${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${DTB}" ]; then
|
if [ -e "${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${DTB}" ]; then
|
||||||
BOOTIMG_FILES_SYMLINK="${BOOTIMG_FILES_SYMLINK} ${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${DTB}"
|
BOOTIMG_FILES_SYMLINK="${BOOTIMG_FILES_SYMLINK} ${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${DTB}"
|
||||||
fi
|
fi
|
||||||
|
|
@ -149,6 +153,8 @@ IMAGE_CMD_recovery.ubifs() {
|
||||||
RECOVERYIMG_FILES_SYMLINK="${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${MACHINE}.bin"
|
RECOVERYIMG_FILES_SYMLINK="${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${MACHINE}.bin"
|
||||||
if [ -n "${KERNEL_DEVICETREE}" ]; then
|
if [ -n "${KERNEL_DEVICETREE}" ]; then
|
||||||
for DTB in ${KERNEL_DEVICETREE}; do
|
for DTB in ${KERNEL_DEVICETREE}; do
|
||||||
|
# Remove potential sub-folders
|
||||||
|
DTB="$(basename ${DTB})"
|
||||||
if [ -e "${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${DTB}" ]; then
|
if [ -e "${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${DTB}" ]; then
|
||||||
RECOVERYIMG_FILES_SYMLINK="${RECOVERYIMG_FILES_SYMLINK} ${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${DTB}"
|
RECOVERYIMG_FILES_SYMLINK="${RECOVERYIMG_FILES_SYMLINK} ${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${DTB}"
|
||||||
fi
|
fi
|
||||||
|
|
|
||||||
|
|
@ -11,7 +11,12 @@ WIRELESS_MODULE_append = " ${@base_conditional('HAVE_WIFI', '1', 'kernel-module-
|
||||||
# Wireless p2p interface
|
# Wireless p2p interface
|
||||||
WLAN_P2P_INTERFACE ?= "p2p0"
|
WLAN_P2P_INTERFACE ?= "p2p0"
|
||||||
|
|
||||||
MACHINE_EXTRA_RRECOMMENDS += "cryptoauthlib"
|
MACHINE_EXTRA_RRECOMMENDS += " \
|
||||||
|
cryptoauthlib \
|
||||||
|
cryptoauth-openssl-engine \
|
||||||
|
"
|
||||||
|
|
||||||
|
MACHINE_FEATURES += "cryptochip"
|
||||||
|
|
||||||
# Firmware
|
# Firmware
|
||||||
MACHINE_FIRMWARE_append = " ${@base_conditional('HAVE_BT', '1', 'firmware-qualcomm-qca6564-bt', '', d)}"
|
MACHINE_FIRMWARE_append = " ${@base_conditional('HAVE_BT', '1', 'firmware-qualcomm-qca6564-bt', '', d)}"
|
||||||
|
|
@ -22,7 +27,7 @@ PREFERRED_PROVIDER_virtual/libg2d_mx6 = "imx-gpu-g2d"
|
||||||
# U-Boot configurations
|
# U-Boot configurations
|
||||||
# Last one is the default (the one the symlinks point at)
|
# Last one is the default (the one the symlinks point at)
|
||||||
UBOOT_CONFIG ??= "ccimx6qpsbc2GB"
|
UBOOT_CONFIG ??= "ccimx6qpsbc2GB"
|
||||||
UBOOT_CONFIG[ccimx6qpsbc2GB] = "ccimx6qpsbc2GB_defconfig"
|
UBOOT_CONFIG[ccimx6qpsbc2GB] = "ccimx6qpsbc2GB_defconfig,,u-boot-dtb.${UBOOT_SUFFIX}"
|
||||||
|
|
||||||
KERNEL_DEVICETREE ?= " \
|
KERNEL_DEVICETREE ?= " \
|
||||||
imx6qp-ccimx6qpsbc.dtb \
|
imx6qp-ccimx6qpsbc.dtb \
|
||||||
|
|
|
||||||
|
|
@ -14,11 +14,11 @@ PREFERRED_PROVIDER_virtual/libg2d_mx6 = "imx-gpu-g2d"
|
||||||
# U-Boot configurations
|
# U-Boot configurations
|
||||||
# Last one is the default (the one the symlinks point at)
|
# Last one is the default (the one the symlinks point at)
|
||||||
UBOOT_CONFIG ??= "ccimx6dlsbc512MB ccimx6dlsbc ccimx6qsbc2GB ccimx6qsbc512MB ccimx6qsbc"
|
UBOOT_CONFIG ??= "ccimx6dlsbc512MB ccimx6dlsbc ccimx6qsbc2GB ccimx6qsbc512MB ccimx6qsbc"
|
||||||
UBOOT_CONFIG[ccimx6dlsbc512MB] = "ccimx6dlsbc512MB_defconfig"
|
UBOOT_CONFIG[ccimx6dlsbc512MB] = "ccimx6dlsbc512MB_defconfig,,u-boot-dtb.${UBOOT_SUFFIX}"
|
||||||
UBOOT_CONFIG[ccimx6dlsbc] = "ccimx6dlsbc_defconfig"
|
UBOOT_CONFIG[ccimx6dlsbc] = "ccimx6dlsbc_defconfig,,u-boot-dtb.${UBOOT_SUFFIX}"
|
||||||
UBOOT_CONFIG[ccimx6qsbc2GB] = "ccimx6qsbc2GB_defconfig"
|
UBOOT_CONFIG[ccimx6qsbc2GB] = "ccimx6qsbc2GB_defconfig,,u-boot-dtb.${UBOOT_SUFFIX}"
|
||||||
UBOOT_CONFIG[ccimx6qsbc512MB] = "ccimx6qsbc512MB_defconfig"
|
UBOOT_CONFIG[ccimx6qsbc512MB] = "ccimx6qsbc512MB_defconfig,,u-boot-dtb.${UBOOT_SUFFIX}"
|
||||||
UBOOT_CONFIG[ccimx6qsbc] = "ccimx6qsbc_defconfig"
|
UBOOT_CONFIG[ccimx6qsbc] = "ccimx6qsbc_defconfig,,u-boot-dtb.${UBOOT_SUFFIX}"
|
||||||
|
|
||||||
KERNEL_DEVICETREE ?= " \
|
KERNEL_DEVICETREE ?= " \
|
||||||
imx6dl-ccimx6sbc.dtb \
|
imx6dl-ccimx6sbc.dtb \
|
||||||
|
|
|
||||||
|
|
@ -8,8 +8,8 @@ include conf/machine/include/ccimx6ul.inc
|
||||||
# U-Boot configurations
|
# U-Boot configurations
|
||||||
# Last one is the default (the one the symlinks point at)
|
# Last one is the default (the one the symlinks point at)
|
||||||
UBOOT_CONFIG ??= "ccimx6ulsbc1GB ccimx6ulsbc"
|
UBOOT_CONFIG ??= "ccimx6ulsbc1GB ccimx6ulsbc"
|
||||||
UBOOT_CONFIG[ccimx6ulsbc1GB] = "ccimx6ulsbc1GB_defconfig"
|
UBOOT_CONFIG[ccimx6ulsbc1GB] = "ccimx6ulsbc1GB_defconfig,,u-boot-dtb.${UBOOT_SUFFIX}"
|
||||||
UBOOT_CONFIG[ccimx6ulsbc] = "ccimx6ulsbc_defconfig"
|
UBOOT_CONFIG[ccimx6ulsbc] = "ccimx6ulsbc_defconfig,,u-boot-dtb.${UBOOT_SUFFIX}"
|
||||||
|
|
||||||
# U-Boot environment offset (within partition)
|
# U-Boot environment offset (within partition)
|
||||||
UBOOT_ENV_OFFSET ?= "0x0"
|
UBOOT_ENV_OFFSET ?= "0x0"
|
||||||
|
|
|
||||||
|
|
@ -8,8 +8,8 @@ include conf/machine/include/ccimx6ul.inc
|
||||||
# U-Boot configurations
|
# U-Boot configurations
|
||||||
# Last one is the default (the one the symlinks point at)
|
# Last one is the default (the one the symlinks point at)
|
||||||
UBOOT_CONFIG ??= "ccimx6ulstarter1GB ccimx6ulstarter"
|
UBOOT_CONFIG ??= "ccimx6ulstarter1GB ccimx6ulstarter"
|
||||||
UBOOT_CONFIG[ccimx6ulstarter1GB] = "ccimx6ulstarter1GB_defconfig"
|
UBOOT_CONFIG[ccimx6ulstarter1GB] = "ccimx6ulstarter1GB_defconfig,,u-boot-dtb.${UBOOT_SUFFIX}"
|
||||||
UBOOT_CONFIG[ccimx6ulstarter] = "ccimx6ulstarter_defconfig"
|
UBOOT_CONFIG[ccimx6ulstarter] = "ccimx6ulstarter_defconfig,,u-boot-dtb.${UBOOT_SUFFIX}"
|
||||||
|
|
||||||
# U-Boot environment offset (within partition)
|
# U-Boot environment offset (within partition)
|
||||||
UBOOT_ENV_OFFSET ?= "0x0"
|
UBOOT_ENV_OFFSET ?= "0x0"
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,43 @@
|
||||||
|
#@TYPE: Machine
|
||||||
|
#@NAME: ConnectCore 8X Single Board Computer Express.
|
||||||
|
#@DESCRIPTION: Machine configuration for Digi's ConnectCore 8X SBC Express.
|
||||||
|
|
||||||
|
# Include the machine configuration for Digi's ConnectCore 8X module.
|
||||||
|
include conf/machine/include/ccimx8x.inc
|
||||||
|
|
||||||
|
# Wireless external module
|
||||||
|
WIRELESS_MODULE_append = " ${@base_conditional('HAVE_WIFI', '1', 'kernel-module-qualcomm', '', d)}"
|
||||||
|
|
||||||
|
# Wireless p2p interface
|
||||||
|
WLAN_P2P_INTERFACE ?= "p2p0"
|
||||||
|
|
||||||
|
MACHINE_EXTRA_RRECOMMENDS += " \
|
||||||
|
cryptoauthlib \
|
||||||
|
cryptoauth-openssl-engine \
|
||||||
|
"
|
||||||
|
|
||||||
|
# Firmware
|
||||||
|
MACHINE_FIRMWARE_append = " ${@base_conditional('HAVE_BT', '1', 'firmware-qualcomm-qca6574-bt', '', d)}"
|
||||||
|
MACHINE_FIRMWARE_append = " ${@base_conditional('HAVE_WIFI', '1', 'firmware-qualcomm-qca6574-wifi', '', d)}"
|
||||||
|
|
||||||
|
# U-Boot configurations
|
||||||
|
# Last one is the default (the one the symlinks point at)
|
||||||
|
UBOOT_CONFIG ??= "ccimx8x_sbc_express2GB ccimx8x_sbc_express1GB"
|
||||||
|
UBOOT_CONFIG[ccimx8x_sbc_express2GB] = "ccimx8x_sbc_express2GB_defconfig,,u-boot-dtb.${UBOOT_SUFFIX}"
|
||||||
|
UBOOT_CONFIG[ccimx8x_sbc_express1GB] = "ccimx8x_sbc_express1GB_defconfig,,u-boot-dtb.${UBOOT_SUFFIX}"
|
||||||
|
|
||||||
|
KERNEL_DEVICETREE ?= " \
|
||||||
|
digi/ccimx8x-sbc-express-wb.dtb \
|
||||||
|
digi/ccimx8x-sbc-express.dtb \
|
||||||
|
"
|
||||||
|
|
||||||
|
SERIAL_CONSOLES ?= "115200;ttyLP2"
|
||||||
|
|
||||||
|
# Bluetooth tty
|
||||||
|
BT_TTY ?= "ttyLP1"
|
||||||
|
|
||||||
|
# U-Boot script to be copied to the boot image
|
||||||
|
BOOT_SCRIPTS = "boot.scr:boot.scr"
|
||||||
|
|
||||||
|
# Flash image types
|
||||||
|
IMAGE_FSTYPES ?= "boot.vfat ext4 sdcard tar.bz2 recovery.vfat"
|
||||||
|
|
@ -12,6 +12,9 @@ include conf/machine/include/tune-cortexa9.inc
|
||||||
UBOOT_SUFFIX = "imx"
|
UBOOT_SUFFIX = "imx"
|
||||||
UBOOT_SYMLINK = "u-boot-${MACHINE}.${UBOOT_SUFFIX}"
|
UBOOT_SYMLINK = "u-boot-${MACHINE}.${UBOOT_SUFFIX}"
|
||||||
|
|
||||||
|
# Linux kernel configuration
|
||||||
|
KERNEL_DEFCONFIG ?= "arch/arm/configs/ccimx6sbc_defconfig"
|
||||||
|
|
||||||
# Wireless external module
|
# Wireless external module
|
||||||
WIRELESS_MODULE ?= ""
|
WIRELESS_MODULE ?= ""
|
||||||
|
|
||||||
|
|
@ -30,7 +33,7 @@ MACHINE_EXTRA_RDEPENDS += " \
|
||||||
MACHINE_EXTRA_RRECOMMENDS += " \
|
MACHINE_EXTRA_RRECOMMENDS += " \
|
||||||
${MACHINE_FIRMWARE} \
|
${MACHINE_FIRMWARE} \
|
||||||
${WIRELESS_MODULE} \
|
${WIRELESS_MODULE} \
|
||||||
${@bb.utils.contains('DISTRO_FEATURES', 'alsa', 'imx-alsa-plugins', '', d)} \
|
${@bb.utils.contains('COMBINED_FEATURES', 'alsa', 'imx-alsa-plugins', '', d)} \
|
||||||
cryptodev-module \
|
cryptodev-module \
|
||||||
"
|
"
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -12,6 +12,9 @@ include conf/machine/include/tune-cortexa7.inc
|
||||||
UBOOT_SUFFIX = "imx"
|
UBOOT_SUFFIX = "imx"
|
||||||
UBOOT_SYMLINK = "u-boot-${MACHINE}.${UBOOT_SUFFIX}"
|
UBOOT_SYMLINK = "u-boot-${MACHINE}.${UBOOT_SUFFIX}"
|
||||||
|
|
||||||
|
# Linux kernel configuration
|
||||||
|
KERNEL_DEFCONFIG ?= "arch/arm/configs/ccimx6ul_defconfig"
|
||||||
|
|
||||||
# Wireless external module
|
# Wireless external module
|
||||||
WIRELESS_MODULE ?= ""
|
WIRELESS_MODULE ?= ""
|
||||||
WIRELESS_MODULE_append = " ${@base_conditional('HAVE_WIFI', '1', 'kernel-module-qualcomm', '', d)}"
|
WIRELESS_MODULE_append = " ${@base_conditional('HAVE_WIFI', '1', 'kernel-module-qualcomm', '', d)}"
|
||||||
|
|
@ -32,12 +35,13 @@ MACHINE_EXTRA_RDEPENDS += " \
|
||||||
MACHINE_EXTRA_RRECOMMENDS += " \
|
MACHINE_EXTRA_RRECOMMENDS += " \
|
||||||
${MACHINE_FIRMWARE} \
|
${MACHINE_FIRMWARE} \
|
||||||
${WIRELESS_MODULE} \
|
${WIRELESS_MODULE} \
|
||||||
${@bb.utils.contains('DISTRO_FEATURES', 'alsa', 'imx-alsa-plugins', '', d)} \
|
${@bb.utils.contains('COMBINED_FEATURES', 'alsa', 'imx-alsa-plugins', '', d)} \
|
||||||
cryptoauthlib \
|
cryptoauthlib \
|
||||||
cryptodev-module \
|
cryptodev-module \
|
||||||
|
cryptoauth-openssl-engine \
|
||||||
"
|
"
|
||||||
|
|
||||||
MACHINE_FEATURES += "wifi bluetooth"
|
MACHINE_FEATURES += "wifi bluetooth cryptochip"
|
||||||
|
|
||||||
MACHINE_FIRMWARE_append = " ${@base_conditional('HAVE_BT', '1', 'firmware-qualcomm-qca6564-bt', '', d)}"
|
MACHINE_FIRMWARE_append = " ${@base_conditional('HAVE_BT', '1', 'firmware-qualcomm-qca6564-bt', '', d)}"
|
||||||
MACHINE_FIRMWARE_append = " ${@base_conditional('HAVE_WIFI', '1', 'firmware-qualcomm-qca6564-wifi', '', d)}"
|
MACHINE_FIRMWARE_append = " ${@base_conditional('HAVE_WIFI', '1', 'firmware-qualcomm-qca6564-wifi', '', d)}"
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,48 @@
|
||||||
|
#@TYPE: Machine
|
||||||
|
#@NAME: ConnectCore 8X module.
|
||||||
|
#@DESCRIPTION: Machine configuration for Digi's ConnectCore 8X module.
|
||||||
|
|
||||||
|
DIGI_FAMILY = "ccimx8x"
|
||||||
|
MACHINEOVERRIDES =. "mx8:mx8x:mx8qxp:mx8dxp:mx8dx:${DIGI_FAMILY}:"
|
||||||
|
|
||||||
|
include conf/machine/include/imx-digi-base.inc
|
||||||
|
include conf/machine/include/arm/arch-arm64.inc
|
||||||
|
|
||||||
|
# Platform u-boot settings
|
||||||
|
UBOOT_SUFFIX = "bin"
|
||||||
|
UBOOT_SYMLINK = "u-boot-${MACHINE}.${UBOOT_SUFFIX}"
|
||||||
|
|
||||||
|
# The bootloader image that gets flashed consists of U-Boot and several fw binaries
|
||||||
|
EXTRA_IMAGEDEPENDS = "imx-boot"
|
||||||
|
|
||||||
|
# Linux kernel configuration
|
||||||
|
KERNEL_DEFCONFIG ?= "arch/arm64/configs/ccimx8x_defconfig"
|
||||||
|
|
||||||
|
# Wireless external module
|
||||||
|
WIRELESS_MODULE ?= ""
|
||||||
|
|
||||||
|
# Firmware
|
||||||
|
MACHINE_FIRMWARE ?= ""
|
||||||
|
|
||||||
|
MACHINE_EXTRA_RDEPENDS += " \
|
||||||
|
e2fsprogs-mke2fs \
|
||||||
|
e2fsprogs-resize2fs \
|
||||||
|
mca-tool \
|
||||||
|
parted \
|
||||||
|
u-boot-fw-utils \
|
||||||
|
"
|
||||||
|
|
||||||
|
MACHINE_EXTRA_RRECOMMENDS += " \
|
||||||
|
${MACHINE_FIRMWARE} \
|
||||||
|
${WIRELESS_MODULE} \
|
||||||
|
cryptodev-module \
|
||||||
|
"
|
||||||
|
|
||||||
|
MACHINE_FEATURES += "accel-graphics accel-video wifi bluetooth cryptochip"
|
||||||
|
|
||||||
|
# AARCH64 doesn't support self-extracting zImage
|
||||||
|
KERNEL_IMAGETYPE = "Image.gz"
|
||||||
|
|
||||||
|
# Adding 'wayland' along with 'x11' enables the xwayland backend
|
||||||
|
# Vulkan is necessary for wayland to build
|
||||||
|
DISTRO_FEATURES_append = " wayland vulkan"
|
||||||
|
|
@ -10,9 +10,10 @@ PREFERRED_PROVIDER_virtual/xserver = "xserver-xorg"
|
||||||
#
|
#
|
||||||
# Platform Linux U-Boot
|
# Platform Linux U-Boot
|
||||||
# -------------------------------------------------
|
# -------------------------------------------------
|
||||||
# ccimx6 4.1, 3.14 2015.04
|
# ccimx6 4.9 2017.03, 2015.04
|
||||||
# ccimx6qp 4.9 2015.04
|
# ccimx6qp 4.9 2017.03, 2015.04
|
||||||
# ccimx6ul 4.9, 4.1 2015.04
|
# ccimx6ul 4.9 2017.03, 2015.04
|
||||||
|
# ccimx8x 4.9 2017.03 (packaged in imx-boot)
|
||||||
#
|
#
|
||||||
|
|
||||||
# Help variables used in recipes
|
# Help variables used in recipes
|
||||||
|
|
|
||||||
|
|
@ -2,7 +2,8 @@
|
||||||
include conf/machine/include/digi-defaults.inc
|
include conf/machine/include/digi-defaults.inc
|
||||||
|
|
||||||
XSERVER_DRIVER = "xf86-video-fbdev"
|
XSERVER_DRIVER = "xf86-video-fbdev"
|
||||||
XSERVER_DRIVER_imxgpu2d = "xf86-video-imxfb-vivante"
|
XSERVER_DRIVER_imxgpu2d = "xf86-video-imx-vivante"
|
||||||
|
XSERVER_DRIVER_append_mx8 = " xf86-video-modesetting"
|
||||||
XSERVER = "xserver-xorg \
|
XSERVER = "xserver-xorg \
|
||||||
xf86-input-evdev \
|
xf86-input-evdev \
|
||||||
${XSERVER_DRIVER}"
|
${XSERVER_DRIVER}"
|
||||||
|
|
@ -19,23 +20,33 @@ MACHINE_EXTRA_RRECOMMENDS = "kernel-modules"
|
||||||
# handled by hardware
|
# handled by hardware
|
||||||
DEFAULTTUNE_mx6 ?= "cortexa9thf-neon"
|
DEFAULTTUNE_mx6 ?= "cortexa9thf-neon"
|
||||||
DEFAULTTUNE_mx6ul ?= "cortexa7thf-neon"
|
DEFAULTTUNE_mx6ul ?= "cortexa7thf-neon"
|
||||||
|
DEFAULTTUNE_mx8 ?= "aarch64"
|
||||||
|
|
||||||
INHERIT += "machine-overrides-extender"
|
INHERIT += "machine-overrides-extender"
|
||||||
|
|
||||||
MACHINEOVERRIDES_EXTENDER_mx6q = "imxipu:imxvpu:imxgpu2d:imxgpu3d"
|
MACHINEOVERRIDES_EXTENDER_mx6q = "imxfbdev:imxipu:imxvpu:imxvpucnm:imxgpu:imxgpu2d:imxdpublit:imxgpu3d"
|
||||||
MACHINEOVERRIDES_EXTENDER_mx6dl = "imxpxp:imxipu:imxvpu:imxgpu2d:imxgpu3d:imxepdc"
|
MACHINEOVERRIDES_EXTENDER_mx6dl = "imxfbdev:imxipu:imxpxp:imxvpu:imxvpucnm:imxgpu:imxgpu2d:imxdpublit:imxgpu3d:imxepdc"
|
||||||
MACHINEOVERRIDES_EXTENDER_mx6ul = "imxpxp"
|
MACHINEOVERRIDES_EXTENDER_mx6ul = "imxfbdev:imxpxp"
|
||||||
|
MACHINEOVERRIDES_EXTENDER_mx8qxp = "imxdrm:imxdpu:imxgpu:imxgpu2d:imxgpu3d"
|
||||||
|
|
||||||
# Sub-architecture support
|
# Sub-architecture support
|
||||||
MACHINE_SOCARCH_SUFFIX ?= ""
|
MACHINE_SOCARCH_SUFFIX ?= ""
|
||||||
MACHINE_SOCARCH_SUFFIX_mx6q = "-mx6qdl"
|
MACHINE_SOCARCH_SUFFIX_mx6q = "-mx6qdl"
|
||||||
MACHINE_SOCARCH_SUFFIX_mx6dl = "-mx6qdl"
|
MACHINE_SOCARCH_SUFFIX_mx6dl = "-mx6qdl"
|
||||||
MACHINE_SOCARCH_SUFFIX_mx6ul = "-mx6ul"
|
MACHINE_SOCARCH_SUFFIX_mx6ul = "-mx6ul"
|
||||||
|
MACHINE_SOCARCH_SUFFIX_mx8qxp = "-mx8qxp"
|
||||||
|
MACHINE_SOCARCH_SUFFIX_mx8dxp = "-mx8dxp"
|
||||||
|
MACHINE_SOCARCH_SUFFIX_mx8dx = "-mx8dx"
|
||||||
|
|
||||||
MACHINE_ARCH_FILTER = "virtual/kernel"
|
MACHINE_ARCH_FILTER = "virtual/kernel"
|
||||||
MACHINE_SOCARCH_FILTER_append_imxvpu = " imx-vpu libimxvpuapi imx-codec imx-vpuwrap imx-parser"
|
MACHINE_SOCARCH_FILTER_append_imxvpu = " imx-vpu libimxvpuapi imx-codec imx-vpuwrap imx-parser"
|
||||||
MACHINE_SOCARCH_FILTER_append_imxgpu2d = " virtual/libopenvg virtual/libgles1 virtual/libgles2 virtual/egl virtual/mesa virtual/libgl virtual/libg2d cairo pango"
|
MACHINE_SOCARCH_FILTER_append_imxgpu2d = " virtual/libopenvg virtual/libgles1 virtual/libgles2 virtual/egl virtual/mesa virtual/libgl virtual/libg2d cairo pango"
|
||||||
MACHINE_SOCARCH_FILTER_append_imxpxp = " imx-codec imx-parser"
|
MACHINE_SOCARCH_FILTER_append_imxpxp = " imx-codec imx-parser"
|
||||||
|
MACHINE_SOCARCH_FILTER_append_mx8 = " \
|
||||||
|
virtual/libopenvx \
|
||||||
|
virtual/opencl-icd \
|
||||||
|
opencl-headers \
|
||||||
|
"
|
||||||
|
|
||||||
INHERIT += "fsl-dynamic-packagearch"
|
INHERIT += "fsl-dynamic-packagearch"
|
||||||
|
|
||||||
|
|
@ -55,11 +66,13 @@ MACHINE_GSTREAMER_1_0_PLUGIN ?= ""
|
||||||
MACHINE_GSTREAMER_1_0_PLUGIN_mx6q ?= "imx-gst1.0-plugin imx-gst1.0-plugin-gplay imx-gst1.0-plugin-grecorder"
|
MACHINE_GSTREAMER_1_0_PLUGIN_mx6q ?= "imx-gst1.0-plugin imx-gst1.0-plugin-gplay imx-gst1.0-plugin-grecorder"
|
||||||
MACHINE_GSTREAMER_1_0_PLUGIN_mx6dl ?= "imx-gst1.0-plugin imx-gst1.0-plugin-gplay imx-gst1.0-plugin-grecorder"
|
MACHINE_GSTREAMER_1_0_PLUGIN_mx6dl ?= "imx-gst1.0-plugin imx-gst1.0-plugin-gplay imx-gst1.0-plugin-grecorder"
|
||||||
MACHINE_GSTREAMER_1_0_PLUGIN_mx6ul ?= "imx-gst1.0-plugin imx-gst1.0-plugin-gplay imx-gst1.0-plugin-grecorder"
|
MACHINE_GSTREAMER_1_0_PLUGIN_mx6ul ?= "imx-gst1.0-plugin imx-gst1.0-plugin-gplay imx-gst1.0-plugin-grecorder"
|
||||||
|
MACHINE_GSTREAMER_1_0_PLUGIN_mx8 ?= "imx-gst1.0-plugin imx-gst1.0-plugin-gplay imx-gst1.0-plugin-grecorder"
|
||||||
|
|
||||||
# Determines if the SoC has support for Vivante kernel driver
|
# Determines if the SoC has support for Vivante kernel driver
|
||||||
SOC_HAS_VIVANTE_KERNEL_DRIVER_SUPPORT = "0"
|
SOC_HAS_VIVANTE_KERNEL_DRIVER_SUPPORT = "0"
|
||||||
SOC_HAS_VIVANTE_KERNEL_DRIVER_SUPPORT_mx6q = "1"
|
SOC_HAS_VIVANTE_KERNEL_DRIVER_SUPPORT_mx6q = "1"
|
||||||
SOC_HAS_VIVANTE_KERNEL_DRIVER_SUPPORT_mx6dl = "1"
|
SOC_HAS_VIVANTE_KERNEL_DRIVER_SUPPORT_mx6dl = "1"
|
||||||
|
SOC_HAS_VIVANTE_KERNEL_DRIVER_SUPPORT_mx8 = "1"
|
||||||
|
|
||||||
# Handle Vivante kernel driver setting:
|
# Handle Vivante kernel driver setting:
|
||||||
# 0 - machine does not have Vivante GPU driver support
|
# 0 - machine does not have Vivante GPU driver support
|
||||||
|
|
@ -70,25 +83,30 @@ MACHINE_HAS_VIVANTE_KERNEL_DRIVER_SUPPORT ?= "${SOC_HAS_VIVANTE_KERNEL_DRIVER_SU
|
||||||
PREFERRED_PROVIDER_virtual/egl_mx6q ?= "imx-gpu-viv"
|
PREFERRED_PROVIDER_virtual/egl_mx6q ?= "imx-gpu-viv"
|
||||||
PREFERRED_PROVIDER_virtual/egl_mx6dl ?= "imx-gpu-viv"
|
PREFERRED_PROVIDER_virtual/egl_mx6dl ?= "imx-gpu-viv"
|
||||||
PREFERRED_PROVIDER_virtual/egl_mx6ul ?= "mesa"
|
PREFERRED_PROVIDER_virtual/egl_mx6ul ?= "mesa"
|
||||||
|
PREFERRED_PROVIDER_virtual/egl_mx8 ?= "imx-gpu-viv"
|
||||||
|
|
||||||
PREFERRED_PROVIDER_virtual/libgles1_mx6q ?= "imx-gpu-viv"
|
PREFERRED_PROVIDER_virtual/libgles1_mx6q ?= "imx-gpu-viv"
|
||||||
PREFERRED_PROVIDER_virtual/libgles1_mx6dl ?= "imx-gpu-viv"
|
PREFERRED_PROVIDER_virtual/libgles1_mx6dl ?= "imx-gpu-viv"
|
||||||
PREFERRED_PROVIDER_virtual/libgles1_mx6ul ?= "mesa"
|
PREFERRED_PROVIDER_virtual/libgles1_mx6ul ?= "mesa"
|
||||||
|
PREFERRED_PROVIDER_virtual/libgles1_mx8 ?= "imx-gpu-viv"
|
||||||
|
|
||||||
PREFERRED_PROVIDER_virtual/libgles2_mx6q ?= "imx-gpu-viv"
|
PREFERRED_PROVIDER_virtual/libgles2_mx6q ?= "imx-gpu-viv"
|
||||||
PREFERRED_PROVIDER_virtual/libgles2_mx6dl ?= "imx-gpu-viv"
|
PREFERRED_PROVIDER_virtual/libgles2_mx6dl ?= "imx-gpu-viv"
|
||||||
PREFERRED_PROVIDER_virtual/libgles2_mx6ul ?= "mesa"
|
PREFERRED_PROVIDER_virtual/libgles2_mx6ul ?= "mesa"
|
||||||
|
PREFERRED_PROVIDER_virtual/libgles2_mx8 ?= "imx-gpu-viv"
|
||||||
|
|
||||||
PREFERRED_PROVIDER_virtual/libgl_mx6q ?= "imx-gpu-viv"
|
PREFERRED_PROVIDER_virtual/libgl_mx6q ?= "imx-gpu-viv"
|
||||||
PREFERRED_PROVIDER_virtual/libgl_mx6dl ?= "imx-gpu-viv"
|
PREFERRED_PROVIDER_virtual/libgl_mx6dl ?= "imx-gpu-viv"
|
||||||
PREFERRED_PROVIDER_virtual/libgl_mx6ul ?= "mesa"
|
PREFERRED_PROVIDER_virtual/libgl_mx6ul ?= "mesa"
|
||||||
|
PREFERRED_PROVIDER_virtual/libgl_mx8 ?= "imx-gpu-viv"
|
||||||
|
|
||||||
PREFERRED_PROVIDER_virtual/libg2d_mx6 ?= "imx-gpu-viv"
|
PREFERRED_PROVIDER_virtual/libg2d_mx6 ?= "imx-gpu-viv"
|
||||||
PREFERRED_PROVIDER_virtual/libg2d_mx6ul = ""
|
PREFERRED_PROVIDER_virtual/libg2d_mx6ul = ""
|
||||||
|
PREFERRED_PROVIDER_virtual/libg2d_mx8 = "imx-dpu-g2d"
|
||||||
|
|
||||||
EXTRA_IMAGEDEPENDS = "u-boot"
|
EXTRA_IMAGEDEPENDS = "u-boot"
|
||||||
|
|
||||||
KERNEL_IMAGETYPE = "zImage"
|
KERNEL_IMAGETYPE ?= "zImage"
|
||||||
|
|
||||||
MACHINE_FEATURES = "usbgadget usbhost vfat alsa touchscreen"
|
MACHINE_FEATURES = "usbgadget usbhost vfat alsa touchscreen"
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,30 @@
|
||||||
|
Copyright (c) 2017 Microchip Technology Inc. and its subsidiaries (Microchip). All rights reserved.
|
||||||
|
|
||||||
|
You are permitted to use this software and its derivatives with Microchip
|
||||||
|
products. Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, is permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer.
|
||||||
|
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
|
||||||
|
3. The name of Microchip may not be used to endorse or promote products derived
|
||||||
|
from this software without specific prior written permission.
|
||||||
|
|
||||||
|
4. This software may only be redistributed and used in connection with a
|
||||||
|
Microchip integrated circuit.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||||
|
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||||
|
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||||
|
EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL MICROCHIP BE LIABLE FOR
|
||||||
|
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||||
|
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
# Copyright (C) 2013 Digi International.
|
# Copyright (C) 2013-2018 Digi International.
|
||||||
|
|
||||||
FILESEXTRAPATHS_prepend := "${THISDIR}/${BPN}:"
|
FILESEXTRAPATHS_prepend := "${THISDIR}/${BPN}:"
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,271 @@
|
||||||
|
defaults.pcm.rate_converter "linear"
|
||||||
|
|
||||||
|
pcm.dmix_48000{
|
||||||
|
type dmix
|
||||||
|
ipc_key 5678293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 48000
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.dmix_44100{
|
||||||
|
type dmix
|
||||||
|
ipc_key 5678293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 44100
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.dmix_32000{
|
||||||
|
type dmix
|
||||||
|
ipc_key 5678293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 32000
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.dmix_24000{
|
||||||
|
type dmix
|
||||||
|
ipc_key 5678293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 24000
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.dmix_22050{
|
||||||
|
type dmix
|
||||||
|
ipc_key 5678293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 22050
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.dmix_16000{
|
||||||
|
type dmix
|
||||||
|
ipc_key 5678293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 16000
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.dmix_12000{
|
||||||
|
type dmix
|
||||||
|
ipc_key 5678293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 12000
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.dmix_11025{
|
||||||
|
type dmix
|
||||||
|
ipc_key 5678293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 11025
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.dmix_8000{
|
||||||
|
type dmix
|
||||||
|
ipc_key 5678293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 8000
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.!dsnoop_48000{
|
||||||
|
type dsnoop
|
||||||
|
ipc_key 5778293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 48000
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.!dsnoop_44100{
|
||||||
|
type dsnoop
|
||||||
|
ipc_key 5778293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 44100
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.!dsnoop_32000{
|
||||||
|
type dsnoop
|
||||||
|
ipc_key 5778293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 32000
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.!dsnoop_24000{
|
||||||
|
type dsnoop
|
||||||
|
ipc_key 5778293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 24000
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.!dsnoop_22050{
|
||||||
|
type dsnoop
|
||||||
|
ipc_key 5778293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 22050
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.!dsnoop_16000{
|
||||||
|
type dsnoop
|
||||||
|
ipc_key 5778293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 16000
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.!dsnoop_12000{
|
||||||
|
type dsnoop
|
||||||
|
ipc_key 5778293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 12000
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.!dsnoop_11025{
|
||||||
|
type dsnoop
|
||||||
|
ipc_key 5778293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 11025
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.!dsnoop_8000{
|
||||||
|
type dsnoop
|
||||||
|
ipc_key 5778293
|
||||||
|
ipc_key_add_uid yes
|
||||||
|
slave{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
period_time 40000
|
||||||
|
format S16_LE
|
||||||
|
rate 8000
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.asymed{
|
||||||
|
type asym
|
||||||
|
playback.pcm "dmix_44100"
|
||||||
|
capture.pcm "dsnoop_44100"
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.dsp0{
|
||||||
|
type plug
|
||||||
|
slave.pcm "asymed"
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.!default{
|
||||||
|
type plug
|
||||||
|
route_policy "average"
|
||||||
|
slave.pcm "asymed"
|
||||||
|
}
|
||||||
|
|
||||||
|
ctl.!default{
|
||||||
|
type hw
|
||||||
|
card 0
|
||||||
|
}
|
||||||
|
|
||||||
|
ctl.mixer0{
|
||||||
|
type hw
|
||||||
|
card 0
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm_slave.esai{
|
||||||
|
pcm "hw:0,0"
|
||||||
|
channels 8
|
||||||
|
rate 48000
|
||||||
|
period_time 40000
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.esaich1to6{
|
||||||
|
type dshare
|
||||||
|
ipc_key 5778293
|
||||||
|
slave esai
|
||||||
|
bindings.0 0
|
||||||
|
bindings.1 4
|
||||||
|
bindings.2 1
|
||||||
|
bindings.3 5
|
||||||
|
bindings.4 2
|
||||||
|
bindings.5 6
|
||||||
|
}
|
||||||
|
|
||||||
|
pcm.esaich78{
|
||||||
|
type dshare
|
||||||
|
ipc_key 5778293
|
||||||
|
slave esai
|
||||||
|
bindings.0 3
|
||||||
|
bindings.1 7
|
||||||
|
}
|
||||||
|
|
@ -1,13 +0,0 @@
|
||||||
# Copyright (C) 2012-2016 Freescale Semiconductor
|
|
||||||
# Copyright 2017 NXP
|
|
||||||
|
|
||||||
require recipes-bsp/firmware-imx/firmware-imx.inc
|
|
||||||
LIC_FILES_CHKSUM = "file://COPYING;md5=6b552f505eedab4a11ab538cf3db743a"
|
|
||||||
|
|
||||||
SRC_URI[md5sum] = "088fb08b565748b537f6481b1ad6c9d7"
|
|
||||||
SRC_URI[sha256sum] = "9fa7c204a6ff8a30f2b5e8f9002d8c5736791e455dc137b952fa725dc0c3aeb8"
|
|
||||||
|
|
||||||
#BRCM firmware git
|
|
||||||
SRCREV = "951c1363abe95dd75ab3e9447f640d7807240236"
|
|
||||||
|
|
||||||
COMPATIBLE_MACHINE = "(ccimx6)"
|
|
||||||
|
|
@ -0,0 +1,70 @@
|
||||||
|
# Copyright 2017-2018 NXP
|
||||||
|
|
||||||
|
require recipes-bsp/firmware-imx/firmware-imx.inc
|
||||||
|
LIC_FILES_CHKSUM = "file://COPYING;md5=ab61cab9599935bfe9f700405ef00f28"
|
||||||
|
|
||||||
|
#BRCM firmware v1.141.100.6
|
||||||
|
IMX_FIRMWARE_SRC ?= "git://github.com/NXP/imx-firmware.git;protocol=https"
|
||||||
|
SRC_URI = "${FSL_MIRROR}/firmware-imx-${PV}.bin;fsl-eula=true \
|
||||||
|
${IMX_FIRMWARE_SRC};branch=${SRCBRANCH};destsuffix=${S}/git "
|
||||||
|
|
||||||
|
SRC_URI[md5sum] = "3f6a00c3dfc0693c050bf39824865d28"
|
||||||
|
SRC_URI[sha256sum] = "6c1e4d4f33b216f69eb46a6dff7a3e10d722afb694acd412c5398ccc270f8a9c"
|
||||||
|
|
||||||
|
#BRCM firmware git
|
||||||
|
SRCREV = "8ce9046f5058fdd2c5271f86ccfc61bc5a248ae3"
|
||||||
|
|
||||||
|
do_install_append() {
|
||||||
|
# No need to do install for ddr & hdmi binaries
|
||||||
|
if [ -d ${D}${base_libdir}/firmware/ddr ]; then
|
||||||
|
rm -rf ${D}${base_libdir}/firmware/ddr
|
||||||
|
fi
|
||||||
|
if [ -d ${D}${base_libdir}/firmware/hdmi ]; then
|
||||||
|
rm -rf ${D}${base_libdir}/firmware/hdmi
|
||||||
|
fi
|
||||||
|
|
||||||
|
# Don't install hifi4 related binary
|
||||||
|
if [ -d ${D}${base_libdir}/firmware/hifi4 ]; then
|
||||||
|
rm -rf ${D}${base_libdir}/firmware/hifi4
|
||||||
|
fi
|
||||||
|
# Don't install seco related binary
|
||||||
|
if [ -d ${D}${base_libdir}/firmware/seco ]; then
|
||||||
|
rm -rf ${D}${base_libdir}/firmware/seco
|
||||||
|
fi
|
||||||
|
|
||||||
|
#1FD_BCM89359
|
||||||
|
install -d ${D}${base_libdir}/firmware/bcm/1FD_BCM89359
|
||||||
|
cp -rfv git/brcm/1FD_BCM89359/*.bin ${D}${base_libdir}/firmware/bcm/1FD_BCM89359
|
||||||
|
cp -rfv git/brcm/1FD_BCM89359/*.hcd ${D}${sysconfdir}/firmware/
|
||||||
|
|
||||||
|
#1CX_BCM4356
|
||||||
|
install -d ${D}${base_libdir}/firmware/bcm/1CX_BCM4356
|
||||||
|
cp -rfv git/brcm/1CX_BCM4356/fw_bcmdhd.bin ${D}${base_libdir}/firmware/bcm/1CX_BCM4356
|
||||||
|
}
|
||||||
|
|
||||||
|
IS_MX8 = "0"
|
||||||
|
IS_MX8_mx8mq = "8mq"
|
||||||
|
IS_MX8_mx8qm = "8qm"
|
||||||
|
IS_MX8_mx8qxp = "8qx"
|
||||||
|
inherit deploy
|
||||||
|
addtask deploy before do_build after do_install
|
||||||
|
do_deploy () {
|
||||||
|
# Deploy i.MX8 related firmware files
|
||||||
|
if [ "${IS_MX8}" = "8mq" ]; then
|
||||||
|
# Deploy ddr/synopsys
|
||||||
|
for ddr_firmware in ${DDR_FIRMWARE_NAME}; do
|
||||||
|
install -m 0644 ${S}/firmware/ddr/synopsys/${ddr_firmware} ${DEPLOYDIR}
|
||||||
|
done
|
||||||
|
|
||||||
|
# Deploy hdmi/cadence
|
||||||
|
install -m 0644 ${S}/firmware/hdmi/cadence/signed_hdmi_imx8m.bin ${DEPLOYDIR}
|
||||||
|
elif [ "${IS_MX8}" = "8qm" ]; then
|
||||||
|
# Deploy hdmi/cadence
|
||||||
|
install -m 0644 ${S}/firmware/hdmi/cadence/hdmitxfw.bin ${DEPLOYDIR}
|
||||||
|
install -m 0644 ${S}/firmware/hdmi/cadence/hdmirxfw.bin ${DEPLOYDIR}
|
||||||
|
install -m 0644 ${S}/firmware/hdmi/cadence/dpfw.bin ${DEPLOYDIR}
|
||||||
|
elif [ "${IS_MX8}" = "8qx" ]; then
|
||||||
|
# Deploy seco
|
||||||
|
install -m 0644 ${S}/firmware/seco/ahab-container.img ${DEPLOYDIR}
|
||||||
|
fi
|
||||||
|
}
|
||||||
|
|
@ -1,18 +1,22 @@
|
||||||
# Copyright (C) 2016,2017 Digi International.
|
# Copyright (C) 2016-2018 Digi International.
|
||||||
|
|
||||||
SUMMARY = "Qualcomm firmware files for Digi's platforms."
|
SUMMARY = "Qualcomm firmware files for Digi's platforms."
|
||||||
SECTION = "base"
|
SECTION = "base"
|
||||||
LICENSE = "Proprietary"
|
LICENSE = "Proprietary"
|
||||||
LIC_FILES_CHKSUM = "file://${DIGI_EULA_FILE};md5=8c0ad592dd48ace3d25eed5bbb26ba78"
|
LIC_FILES_CHKSUM = "file://${DIGI_EULA_FILE};md5=8c0ad592dd48ace3d25eed5bbb26ba78"
|
||||||
|
|
||||||
FW_QCA6564-BT = " \
|
# Selects whether to use proprietary or community driver
|
||||||
|
QUALCOMM_WIFI_DRIVER ?= "proprietary"
|
||||||
|
|
||||||
|
FW_QUALCOMM_BT = " \
|
||||||
file://qca/nvm_tlv_3.0.bin \
|
file://qca/nvm_tlv_3.0.bin \
|
||||||
file://qca/nvm_tlv_3.2.bin \
|
file://qca/nvm_tlv_3.2.bin \
|
||||||
file://qca/rampatch_tlv_3.0.tlv \
|
file://qca/rampatch_tlv_3.0.tlv \
|
||||||
file://qca/rampatch_tlv_3.2.tlv \
|
file://qca/rampatch_tlv_3.2.tlv \
|
||||||
"
|
"
|
||||||
|
|
||||||
FW_QCA6564-WIFI = " \
|
# Firmware files for QCA6564 (Qualcomm proprietary driver)
|
||||||
|
FW_QCA6564_WIFI_PROPRIETARY = " \
|
||||||
file://bdwlan30_US.bin \
|
file://bdwlan30_US.bin \
|
||||||
file://LICENCE.atheros_firmware \
|
file://LICENCE.atheros_firmware \
|
||||||
file://otp30.bin \
|
file://otp30.bin \
|
||||||
|
|
@ -20,39 +24,74 @@ FW_QCA6564-WIFI = " \
|
||||||
file://utf30.bin \
|
file://utf30.bin \
|
||||||
"
|
"
|
||||||
|
|
||||||
|
# Firmware files for QCA6574 (Qualcomm proprietary driver)
|
||||||
|
FW_QCA6574_WIFI_PROPRIETARY = " \
|
||||||
|
file://LICENCE.atheros_firmware \
|
||||||
|
file://qca6574_proprietary/qwlan30.bin \
|
||||||
|
file://qca6574_proprietary/fakeboar.bin \
|
||||||
|
file://qca6574_proprietary/otp.bin \
|
||||||
|
file://qca6574_proprietary/utf.bin \
|
||||||
|
"
|
||||||
|
|
||||||
|
# Firmware files for QCA6574 (Qualcomm community driver)
|
||||||
|
# NOTE: the community file 'board.bin' must be substituted by proprietary
|
||||||
|
# 'fakeboar.bin'
|
||||||
|
FW_QCA6574_WIFI_COMMUNITY = " \
|
||||||
|
file://qca6574_community/board-2.bin \
|
||||||
|
file://qca6574_community/firmware-4.bin \
|
||||||
|
file://qca6574_community/firmware-6.bin \
|
||||||
|
file://qca6574_community/notice_ath10k_firmware-4.txt \
|
||||||
|
file://qca6574_community/notice_ath10k_firmware-6.txt \
|
||||||
|
file://qca6574_proprietary/fakeboar.bin \
|
||||||
|
"
|
||||||
|
|
||||||
|
FW_QUALCOMM_WIFI ?= "${FW_QCA6564_WIFI_PROPRIETARY}"
|
||||||
|
FW_QUALCOMM_WIFI_ccimx8x = "${@base_conditional('QUALCOMM_WIFI_DRIVER', 'community', '${FW_QCA6574_WIFI_COMMUNITY}', '${FW_QCA6574_WIFI_PROPRIETARY}', d)}"
|
||||||
|
|
||||||
SRC_URI = " \
|
SRC_URI = " \
|
||||||
${FW_QCA6564-BT} \
|
${FW_QUALCOMM_BT} \
|
||||||
${FW_QCA6564-WIFI} \
|
${FW_QUALCOMM_WIFI} \
|
||||||
"
|
"
|
||||||
|
|
||||||
S = "${WORKDIR}"
|
S = "${WORKDIR}"
|
||||||
|
|
||||||
do_install() {
|
do_install() {
|
||||||
# BT firmware
|
# BT firmware (remove 'file://' from variable with files list)
|
||||||
|
BT_FW_FILES=$(echo ${FW_QUALCOMM_BT} | sed -e 's,file\:\/\/,,g')
|
||||||
install -d ${D}${base_libdir}/firmware/qca
|
install -d ${D}${base_libdir}/firmware/qca
|
||||||
install -m 0644 \
|
install -m 0644 ${BT_FW_FILES} ${D}${base_libdir}/firmware/qca
|
||||||
qca/nvm_tlv_3.0.bin \
|
|
||||||
qca/nvm_tlv_3.2.bin \
|
|
||||||
qca/rampatch_tlv_3.0.tlv \
|
|
||||||
qca/rampatch_tlv_3.2.tlv \
|
|
||||||
${D}${base_libdir}/firmware/qca
|
|
||||||
|
|
||||||
# Wifi firmware
|
# Wifi firmware
|
||||||
install -d ${D}${base_libdir}/firmware
|
if [ "${QUALCOMM_WIFI_DRIVER}" = "community" ]; then
|
||||||
install -m 0644 \
|
WIFI_FW_PATH="${D}${base_libdir}/firmware/ath10k/QCA6174/hw3.0"
|
||||||
bdwlan30_US.bin \
|
else
|
||||||
LICENCE.atheros_firmware \
|
WIFI_FW_PATH="${D}${base_libdir}/firmware"
|
||||||
otp30.bin \
|
fi
|
||||||
qwlan30.bin \
|
install -d ${WIFI_FW_PATH}
|
||||||
utf30.bin \
|
# Remove preceeding 'file://' from variable with files list
|
||||||
${D}${base_libdir}/firmware
|
FW_WIFI_FILES="$(echo ${FW_QUALCOMM_WIFI} | sed -e 's,file\:\/\/,,g')"
|
||||||
|
install -m 0644 ${FW_WIFI_FILES} ${WIFI_FW_PATH}
|
||||||
|
cd ${WIFI_FW_PATH}
|
||||||
|
if [ "${QUALCOMM_WIFI_DRIVER}" = "community" ]; then
|
||||||
|
# If using community driver, create symlink 'board.bin' to
|
||||||
|
# proprietary 'fakeboar.bin'
|
||||||
|
ln -s fakeboar.bin board.bin
|
||||||
|
else
|
||||||
|
if [ "${FW_QUALCOMM_WIFI}" = "${FW_QCA6574_WIFI_PROPRIETARY}" ]; then
|
||||||
|
ln -s qwlan30.bin athwlan.bin
|
||||||
|
ln -s otp.bin athsetup.bin
|
||||||
|
fi
|
||||||
|
fi
|
||||||
}
|
}
|
||||||
|
|
||||||
# Do not create empty debug and development packages (PN-dbg PN-dev PN-staticdev)
|
QCA_MODEL ?= "qca6564"
|
||||||
PACKAGES = "${PN}-qca6564-bt ${PN}-qca6564-wifi"
|
QCA_MODEL_ccimx8x = "qca6574"
|
||||||
|
|
||||||
FILES_${PN}-qca6564-bt = "/lib/firmware/qca"
|
# Do not create empty debug and development packages (PN-dbg PN-dev PN-staticdev)
|
||||||
FILES_${PN}-qca6564-wifi = "/lib/firmware"
|
PACKAGES = "${PN}-${QCA_MODEL}-bt ${PN}-${QCA_MODEL}-wifi"
|
||||||
|
|
||||||
|
FILES_${PN}-${QCA_MODEL}-bt = "/lib/firmware/qca"
|
||||||
|
FILES_${PN}-${QCA_MODEL}-wifi = "/lib/firmware"
|
||||||
|
|
||||||
PACKAGE_ARCH = "${MACHINE_ARCH}"
|
PACKAGE_ARCH = "${MACHINE_ARCH}"
|
||||||
COMPATIBLE_MACHINE = "(ccimx6qpsbc|ccimx6ul)"
|
COMPATIBLE_MACHINE = "(ccimx6qpsbc|ccimx6ul|ccimx8x)"
|
||||||
|
|
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,4 @@
|
||||||
|
# Display options
|
||||||
|
HAVE_TOUCHSCREEN=1
|
||||||
|
HAVE_KEYBOARD=0
|
||||||
|
SHOWCURSOR="yes"
|
||||||
|
|
@ -0,0 +1,68 @@
|
||||||
|
# Copyright 2017-2018 NXP
|
||||||
|
|
||||||
|
DESCRIPTION = "i.MX ARM Trusted Firmware"
|
||||||
|
SECTION = "BSP"
|
||||||
|
LICENSE = "BSD-3-Clause"
|
||||||
|
LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/BSD-3-Clause;md5=550794465ba0ec5312d6919e203a55f9"
|
||||||
|
|
||||||
|
inherit pkgconfig deploy
|
||||||
|
|
||||||
|
PV = "1.4.1+git${SRCPV}"
|
||||||
|
|
||||||
|
ATF_SRC ?= "git://source.codeaurora.org/external/imx/imx-atf.git;protocol=https"
|
||||||
|
SRCBRANCH = "imx_4.9.88_imx8qxp_beta2"
|
||||||
|
|
||||||
|
SRC_URI = "${ATF_SRC};branch=${SRCBRANCH}"
|
||||||
|
SRCREV = "00b653ec4b51a211ae735ffe0d3c9de7a8979947"
|
||||||
|
|
||||||
|
S = "${WORKDIR}/git"
|
||||||
|
|
||||||
|
BOOT_TOOLS = "imx-boot-tools"
|
||||||
|
|
||||||
|
SOC_ATF ?= "imx8qm"
|
||||||
|
SOC_ATF_mx8qm = "imx8qm"
|
||||||
|
SOC_ATF_mx8qxp = "imx8qxp"
|
||||||
|
SOC_ATF_mx8mq = "imx8mq"
|
||||||
|
|
||||||
|
SYSROOT_DIRS += "/boot"
|
||||||
|
|
||||||
|
EXTRA_OEMAKE_append = " ${@bb.utils.contains('COMBINED_FEATURES', 'optee', 'SPD=opteed', '', d)}"
|
||||||
|
|
||||||
|
do_compile () {
|
||||||
|
export CROSS_COMPILE="${TARGET_PREFIX}"
|
||||||
|
cd ${S}
|
||||||
|
# Clear LDFLAGS to avoid the option -Wl recognize issue
|
||||||
|
unset LDFLAGS
|
||||||
|
|
||||||
|
echo "-> Build ${SOC_ATF} bl31.bin"
|
||||||
|
# Set BUIL_STRING with the revision info
|
||||||
|
BUILD_STRING=""
|
||||||
|
if [ -e ${S}/.revision ]; then
|
||||||
|
cur_rev=`cat ${S}/.revision`
|
||||||
|
echo " Current revision is ${cur_rev} ."
|
||||||
|
BUILD_STRING="BUILD_STRING=${cur_rev}"
|
||||||
|
else
|
||||||
|
echo " No .revision found! "
|
||||||
|
fi
|
||||||
|
oe_runmake clean PLAT=${SOC_ATF}
|
||||||
|
oe_runmake ${BUILD_STRING} PLAT=${SOC_ATF} bl31
|
||||||
|
|
||||||
|
unset CROSS_COMPILE
|
||||||
|
}
|
||||||
|
|
||||||
|
do_install () {
|
||||||
|
install -d ${D}/boot
|
||||||
|
install -m 0644 ${S}/build/${SOC_ATF}/release/bl31.bin ${D}/boot/bl31-${SOC_ATF}.bin
|
||||||
|
}
|
||||||
|
|
||||||
|
do_deploy () {
|
||||||
|
install -d ${DEPLOYDIR}/${BOOT_TOOLS}
|
||||||
|
install -m 0644 ${S}/build/${SOC_ATF}/release/bl31.bin ${DEPLOYDIR}/${BOOT_TOOLS}/bl31-${SOC_ATF}.bin
|
||||||
|
}
|
||||||
|
|
||||||
|
addtask deploy before do_install after do_compile
|
||||||
|
|
||||||
|
FILES_${PN} = "/boot"
|
||||||
|
|
||||||
|
PACKAGE_ARCH = "${MACHINE_ARCH}"
|
||||||
|
COMPATIBLE_MACHINE = "(mx8)"
|
||||||
|
|
@ -0,0 +1,604 @@
|
||||||
|
From: Hector Palacios <hector.palacios@digi.com>
|
||||||
|
Date: Fri, 22 Jun 2018 10:46:31 +0200
|
||||||
|
Subject: [PATCH] cc8x: configure DDRC for Micron MT53B256M32D1
|
||||||
|
|
||||||
|
The main differences to NXP part are:
|
||||||
|
- 1 rank, instead of 2.
|
||||||
|
- 4Gb density per channel, instead of 12.
|
||||||
|
- tRFC = 180 ns, instead of 280 ns. This also affects tXSR, tXS
|
||||||
|
- Reordering of the data bus lines.
|
||||||
|
|
||||||
|
These were calculated using Excel aid sheet:
|
||||||
|
MX8QXP_LPDDR4_register_programming_aid_ValidationBoard_1.2GHz_v7_DBI_enabled.xlsx
|
||||||
|
|
||||||
|
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
|
||||||
|
---
|
||||||
|
iMX8QX/imx8qx_dcd_1.2GHz.cfg | 558 ++++++++++++++++-------------------
|
||||||
|
1 file changed, 255 insertions(+), 303 deletions(-)
|
||||||
|
mode change 100755 => 100644 iMX8QX/imx8qx_dcd_1.2GHz.cfg
|
||||||
|
|
||||||
|
diff --git a/iMX8QX/imx8qx_dcd_1.2GHz.cfg b/iMX8QX/imx8qx_dcd_1.2GHz.cfg
|
||||||
|
old mode 100755
|
||||||
|
new mode 100644
|
||||||
|
index e16e2ec27b5d..abf0ad89fcca
|
||||||
|
--- a/iMX8QX/imx8qx_dcd_1.2GHz.cfg
|
||||||
|
+++ b/iMX8QX/imx8qx_dcd_1.2GHz.cfg
|
||||||
|
@@ -10,323 +10,275 @@
|
||||||
|
* Addr-type Address Value
|
||||||
|
*
|
||||||
|
* where:
|
||||||
|
- * Addr-type register length (1,2 or 4 bytes)
|
||||||
|
- * Address absolute address of the register
|
||||||
|
- * value value to be stored in the register
|
||||||
|
+ * Addr-type register length (1,2 or 4 bytes)
|
||||||
|
+ * Address absolute address of the register
|
||||||
|
+ * value value to be stored in the register
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef SCFW_DCD
|
||||||
|
/* For 1200MHz DDR, DRC 600MHz operation */
|
||||||
|
-DATA 4 0xff190000 0x00000CC8 /* DRC0 bringup */
|
||||||
|
+DATA 4 0xff190000 0x00000CC8 /* DRC0 bringup */
|
||||||
|
#else
|
||||||
|
-/* Set the DRC rate to 1.2GHz. */
|
||||||
|
+/* Set the DRC rate to 600MHz, the PHY PLL will double this for the DRAM rate. */
|
||||||
|
uint32_t rate2 = SC_600MHZ;
|
||||||
|
pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
-DATA 4 0x41C80208 0x1
|
||||||
|
-
|
||||||
|
-DATA 4 0x41C80040 0xb
|
||||||
|
-
|
||||||
|
-DATA 4 0x41C80204 0x1
|
||||||
|
+DATA 4 0x41C80208 0x1
|
||||||
|
+DATA 4 0x41C80040 0xb
|
||||||
|
+DATA 4 0x41C80204 0x1
|
||||||
|
|
||||||
|
/* DRAM 0 controller configuration begin */
|
||||||
|
-DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks
|
||||||
|
-DATA 4 DDRC_RFSHTMG_0 0x004800A9 // tREFI, tRFC
|
||||||
|
-DATA 4 DDRC_INIT0_0 0x4003049A // pre_cke = 2ms is too long - LPDDR4 model hacked for 20us
|
||||||
|
-DATA 4 DDRC_INIT1_0 0x007A0000 // dram_rstn - LPDDR4 model hacked for 20us;
|
||||||
|
-DATA 4 DDRC_INIT3_0 0x00440024 // MR1=0x54: nWR=30 BL=16; MR2=0x2d: RL=28 WL=14
|
||||||
|
-//DATA 4 DDRC_INIT4_0 0x00310000 // MR3, MR13
|
||||||
|
-DATA 4 DDRC_INIT4_0 0x00F10000 // MR3=0xF1: DBI-WR=DBI-RD=1, PU-CAL=VDDQ/3 PDDS=RZQ/6, MR13
|
||||||
|
-//DATA 4 DDRC_RANKCTL_0 0x0000075f // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
|
||||||
|
-DATA 4 DDRC_RANKCTL_0 0x0000066f // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd, waiting for SNPS feedback
|
||||||
|
-DATA 4 DDRC_DRAMTMG0_0 0x1619141a // wr2pr, tFAW, tRASmax, tRASmin
|
||||||
|
-DATA 4 DDRC_DRAMTMG1_0 0x00050527 // tXP, rd2pre, tRC
|
||||||
|
-//DATA 4 DDRC_DRAMTMG2_0 0x060c1011 // WL, RL, rd2wr, wr2rd
|
||||||
|
-DATA 4 DDRC_DRAMTMG2_0 0x060E1111 // WL, RL (DBI enabled, 28), rd2wr, wr2rd
|
||||||
|
-DATA 4 DDRC_DRAMTMG3_0 0x0090900a // tmrw, tmrd, tmod
|
||||||
|
-DATA 4 DDRC_DRAMTMG4_0 0x0c04070c // trcd, tccd, trrd, trp
|
||||||
|
-DATA 4 DDRC_DRAMTMG5_0 0x02040a05 // tCKCKEH, tCKCKEL, tckesr, tcke
|
||||||
|
-DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx
|
||||||
|
-DATA 4 DDRC_DRAMTMG7_0 0x00000401 // tckpde, tckpdx
|
||||||
|
-DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD (=tXP?)
|
||||||
|
-DATA 4 DDRC_DRAMTMG13_0 0x0b100002 // tODTLoff, tCCDMW, tPPD
|
||||||
|
-DATA 4 DDRC_DRAMTMG14_0 0x000000ae // txsr
|
||||||
|
-DATA 4 DDRC_ZQCTL0_0 0x425b0013 // tZQCAL, tZQLAT
|
||||||
|
-
|
||||||
|
-DATA 4 DDRC_ZQCTL1_0 0x01f00100 // tZQReset, tzq_short_interval
|
||||||
|
-
|
||||||
|
-//DATA 4 DDRC_DFITMG0_0 0x0495820a // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat
|
||||||
|
-DATA 4 DDRC_DFITMG0_0 0x0499820a // dfi_t_ctrl_delay, dfi_t_rddata_en RL=28 with DBI enabled, dfi_tphy_wrdata, dfi_tphy_wrlat
|
||||||
|
-DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
|
||||||
|
-//DATA 4 DDRC_DFITMG2_0 0x00001308 // dfi_tphy_rdcslat, dfi_tphy_wrcslat
|
||||||
|
-DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat RL=28 with DBI enabled, dfi_tphy_wrcslat
|
||||||
|
-DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity
|
||||||
|
-DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation
|
||||||
|
-DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max)
|
||||||
|
-DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en
|
||||||
|
-
|
||||||
|
-DATA 4 DDRC_ADDRMAP0_0 0x00000015 // addrmap_cs_bit0
|
||||||
|
-DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated
|
||||||
|
-
|
||||||
|
-DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
|
||||||
|
-DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
|
||||||
|
-DATA 4 DDRC_ADDRMAP6_0 0x48080707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12
|
||||||
|
-
|
||||||
|
-DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1
|
||||||
|
-
|
||||||
|
-DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt
|
||||||
|
-DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0
|
||||||
|
-DATA 4 DDRC_HWLPCTL_0 0x0FFF0003 //Enable Hardware idle period - 96 * 32 DFI clk cycles
|
||||||
|
-
|
||||||
|
- //Enables DFI Low Power interface
|
||||||
|
-DATA 4 DDRC_DFILPCFG0_0 0x07009100 // dfi_lp_en_sr=1, dfi_lp_wakeup_sr=0x9
|
||||||
|
-
|
||||||
|
-DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000
|
||||||
|
-
|
||||||
|
-DATA 4 DDRC_PWRCTL_0 0x10A
|
||||||
|
-DATA 4 DDRC_PWRTMG_0 0xFF201F
|
||||||
|
-
|
||||||
|
-DATA 4 0x41C80208 0x1
|
||||||
|
-
|
||||||
|
-DATA 4 0x41C80040 0xf
|
||||||
|
-
|
||||||
|
-DATA 4 0x41C80204 0x1
|
||||||
|
-
|
||||||
|
- //-------------------------------------------
|
||||||
|
- // Configure registers for PHY initialization
|
||||||
|
- // Timings are computed for a PHY at 800MHz (DRAM at 1600MHz)
|
||||||
|
- //-------------------------------=------------
|
||||||
|
-
|
||||||
|
- // Set-up DRAM Configuration Register
|
||||||
|
-DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank
|
||||||
|
-
|
||||||
|
- // Set-up byte and bit swapping registers
|
||||||
|
-DATA 4 DDR_PHY_PGCR8_0 0x000F000A // Set BSWAPMSB='b1001 (byte 0 and 1 are swapped)
|
||||||
|
-DATA 4 DDR_PHY_DX0DQMAP0_0 0x00061032 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
-DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004578 // DQ bit 5/6/7 and DM remapping
|
||||||
|
-DATA 4 DDR_PHY_DX1DQMAP0_0 0x00071032 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
-DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004685 // DQ bit 5/6/7 and DM remapping
|
||||||
|
-DATA 4 DDR_PHY_DX2DQMAP0_0 0x00016578 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
-DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004203 // DQ bit 5/6/7 and DM remapping
|
||||||
|
-DATA 4 DDR_PHY_DX3DQMAP0_0 0x00015867 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
-DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004320 // DQ bit 5/6/7 and DM remapping
|
||||||
|
-DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
|
||||||
|
-DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
|
||||||
|
-
|
||||||
|
- // Set-up PHY General Configuration Register
|
||||||
|
- // PGCR1,4,5,6,7 are untouched
|
||||||
|
-SET_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=1 (no uMCTL2 commands can go to memory)
|
||||||
|
-DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy)
|
||||||
|
-DATA 4 DDR_PHY_PGCR2_0 0x00F0A190 // Set tREFPRD (9*3.904us - 600)
|
||||||
|
-DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity
|
||||||
|
-
|
||||||
|
- // Set-up PHY Timing Register
|
||||||
|
- // PTR2 is untouched
|
||||||
|
-DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST
|
||||||
|
-DATA 4 DDR_PHY_PTR1_0 0x3AA01520 // tPLLLOCK reduced to 4.3us, tPLLRST=9us
|
||||||
|
-
|
||||||
|
- // Set-up PLL Control Register
|
||||||
|
-DATA 4 DDR_PHY_PLLCR0_0 0x000E0000 // FREQSEL=0
|
||||||
|
-DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x000E0000
|
||||||
|
-
|
||||||
|
- // Set-up Impedance Control Register
|
||||||
|
-DATA 4 DDR_PHY_ZQCR_0 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup)
|
||||||
|
-
|
||||||
|
- // ZPROG_DRAM_ODT and ZPROG_HOST_ODT = 60ohm
|
||||||
|
-//DATA 4 DDR_PHY_ZQ0PR0_0 0x0B7BB // comment is wrong => PU_DRV_ADJUST 3b001 = Adjust calibrated drive strength by 2/8 to obtain 1.25x of original strength
|
||||||
|
-//DATA 4 DDR_PHY_ZQ1PR0_0 0x0B7BB
|
||||||
|
-//DATA 4 DDR_PHY_ZQ2PR0_0 0x0B7BB
|
||||||
|
-//DATA 4 DDR_PHY_ZQ3PR0_0 0x0B7BB
|
||||||
|
-DATA 4 DDR_PHY_ZQ0PR0_0 0x1B7BB // PU_DRV_ADJUST 3b001 = Adjust calibrated drive strength by 2/8 to obtain 1.25x of original strength
|
||||||
|
-DATA 4 DDR_PHY_ZQ1PR0_0 0x1B7BB
|
||||||
|
-DATA 4 DDR_PHY_ZQ2PR0_0 0x1B7BB
|
||||||
|
-DATA 4 DDR_PHY_ZQ3PR0_0 0x1B7BB
|
||||||
|
-
|
||||||
|
-
|
||||||
|
- // Set-up PHY Initialization Register
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x32
|
||||||
|
-
|
||||||
|
- // Launch initialization (set bit 0)
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x33
|
||||||
|
-
|
||||||
|
- //-------------------------------------------
|
||||||
|
- // Configure registers for DRAM initialization
|
||||||
|
- //-------------------------------------------
|
||||||
|
-
|
||||||
|
- // Set-up Mode Register
|
||||||
|
- // MR0, MR3, MR4, MR5 MR6 are untouched
|
||||||
|
-DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR=24, RPST
|
||||||
|
-DATA 4 DDR_PHY_MR2_0 0x24 // Set RL=14/WL=8
|
||||||
|
-//DATA 4 DDR_PHY_MR3_0 0x31 // Set drive strength (40 Ohms by default)
|
||||||
|
-DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength (40 Ohms by default), DBI_RD=DBI_WR=1
|
||||||
|
-DATA 4 DDR_PHY_MR11_0 0x05 // Set CA ODT=Disable DQ_ODT=RZQ/5
|
||||||
|
-DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks), SoC ODT = RZQ/5
|
||||||
|
-
|
||||||
|
-/* LPDDR4 mode register writes for CA and DQ VREF settings; range=1, 27.2% */
|
||||||
|
-DATA 4 DDR_PHY_MR12_0 0x48
|
||||||
|
-DATA 4 DDR_PHY_MR14_0 0x48
|
||||||
|
-
|
||||||
|
- // Set-up DRAM Timing Parameters Register
|
||||||
|
- // DTPR6 is untouched
|
||||||
|
-DATA 4 DDR_PHY_DTPR0_0 0x0d331a09 // tRRD, tRAS, tRP, tRTP
|
||||||
|
-DATA 4 DDR_PHY_DTPR1_0 0x28310411 // tWLMRD, tFAW, tODTUP, tMRD
|
||||||
|
-DATA 4 DDR_PHY_DTPR2_0 0x006a615a // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
|
||||||
|
-DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
|
||||||
|
-DATA 4 DDR_PHY_DTPR4_0 0x01512b0D // tRFC, tWLO, tXP
|
||||||
|
-DATA 4 DDR_PHY_DTPR5_0 0x194c160d // tRC, tRCD, tWTR
|
||||||
|
-
|
||||||
|
- // Set-up PHY Timing Register
|
||||||
|
-DATA 4 DDR_PHY_PTR3_0 0x00249F80 // tDINIT0 - 2ms
|
||||||
|
-DATA 4 DDR_PHY_PTR4_0 0x00000970 // tDINIT1 (2000ns)
|
||||||
|
-DATA 4 DDR_PHY_PTR5_0 0x0003A9A0 // tDINIT2 - normally 200us but memory model hacked to 20us
|
||||||
|
-DATA 4 DDR_PHY_PTR6_0 0x027004B5 // tDINIT4 (30ns), tDINIT3 (1us)
|
||||||
|
-
|
||||||
|
- // RDIMMGCR0-2 RDIMMGCR0-4??
|
||||||
|
-
|
||||||
|
- // Set-up DATX8 Common Configuration Register
|
||||||
|
- // DXCCR is untouched
|
||||||
|
-
|
||||||
|
- // Set-up DDR System General Configuration Register
|
||||||
|
- // DSGCR is untouched
|
||||||
|
-
|
||||||
|
- // Set-up ODT Configuration Register
|
||||||
|
- // DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
|
||||||
|
-DATA 4 DDR_PHY_RANKIDR_0 1 // Select rank 1 to write
|
||||||
|
-DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled
|
||||||
|
-DATA 4 DDR_PHY_RANKIDR_0 0 // Select rank 0 to write
|
||||||
|
-DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled
|
||||||
|
-
|
||||||
|
- // Set-up Anti-Aging Control Register
|
||||||
|
- // AACR is untouched
|
||||||
|
-
|
||||||
|
- // Set-up Data Training Address Register
|
||||||
|
- // DTAR0-3 are untouched
|
||||||
|
- // !! DTAR3 is not described in spec !!
|
||||||
|
-
|
||||||
|
- // Set-up AC I/O Configuration Register
|
||||||
|
- // ACIOCR1-4 are untouched
|
||||||
|
-DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2
|
||||||
|
-DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4
|
||||||
|
- // Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON.
|
||||||
|
-DATA 4 DDR_PHY_ACIOCR1_0 0x44000000
|
||||||
|
-
|
||||||
|
- // IOVCR0-1, DXnGCR0-4??, CALBYP
|
||||||
|
-
|
||||||
|
- // Set-up VREF Training Control Registers
|
||||||
|
-DATA 4 DDR_PHY_VTCR0_0 0xF0032019 // CK1, CK0
|
||||||
|
-DATA 4 DDR_PHY_VTCR1_0 0x07F00193 // HVIO=1, SHREN=1, SHRNK=0
|
||||||
|
-
|
||||||
|
- // Set-up DATX8 General Configuration Registers
|
||||||
|
- // DXnGCR0-3 are untouched
|
||||||
|
-DATA 4 DDR_PHY_PGCR5_0 0x01010004
|
||||||
|
-DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit
|
||||||
|
-
|
||||||
|
+DATA 4 DDRC_MSTR_0 0xC1080020 // Set LPDDR4, BL = 16 and active ranks
|
||||||
|
+DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data
|
||||||
|
+DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read
|
||||||
|
+DATA 4 DDRC_RFSHTMG_0 0x0049006C // tREFI, tRFC
|
||||||
|
+DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us
|
||||||
|
+DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us
|
||||||
|
+DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2
|
||||||
|
+DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13
|
||||||
|
+DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
|
||||||
|
+DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin
|
||||||
|
+DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC
|
||||||
|
+DATA 4 DDRC_DRAMTMG2_0 0x060E1714 // WL, RL, rd2wr, wr2rd
|
||||||
|
+DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod
|
||||||
|
+DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp
|
||||||
|
+DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke
|
||||||
|
+DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx
|
||||||
|
+DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx
|
||||||
|
+DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD
|
||||||
|
+DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD
|
||||||
|
+DATA 4 DDRC_DRAMTMG14_0 0x00000071 // txsr
|
||||||
|
+DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT
|
||||||
|
+DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval
|
||||||
|
+DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat
|
||||||
|
+DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
|
||||||
|
+DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat
|
||||||
|
+DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity
|
||||||
|
+DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation
|
||||||
|
+DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max)
|
||||||
|
+DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en
|
||||||
|
+DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0
|
||||||
|
+DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6
|
||||||
|
+DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated
|
||||||
|
+DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
|
||||||
|
+DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
|
||||||
|
+DATA 4 DDRC_ADDRMAP6_0 0x0F070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12
|
||||||
|
+DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1
|
||||||
|
+DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt
|
||||||
|
+DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0
|
||||||
|
+
|
||||||
|
+DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000
|
||||||
|
+
|
||||||
|
+DATA 4 DDRC_PWRCTL_0 0x0000010D
|
||||||
|
+
|
||||||
|
+DATA 4 0x41c80208 0x1
|
||||||
|
+DATA 4 0x41c80040 0xf
|
||||||
|
+DATA 4 0x41c80204 0x1
|
||||||
|
+
|
||||||
|
+//-------------------------------------------
|
||||||
|
+// Configure registers for PHY initialization
|
||||||
|
+// Timings are computed for 1200MHz DRAM operation
|
||||||
|
+//--------------------------------------------
|
||||||
|
+// Set-up DRAM Configuration Register
|
||||||
|
+DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank
|
||||||
|
+// Set-up byte and bit swapping registers
|
||||||
|
+DATA 4 DDR_PHY_PGCR8_0 0x0001000A
|
||||||
|
+DATA 4 DDR_PHY_DX0DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
+DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
+DATA 4 DDR_PHY_DX1DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
+DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
+DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
+DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
+DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
+DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
+DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
|
||||||
|
+DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
|
||||||
|
+// Set-up PHY General Configuration Register
|
||||||
|
+// PGCR1,4,5,6,7 are untouched
|
||||||
|
+SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1
|
||||||
|
+DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy)
|
||||||
|
+DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD
|
||||||
|
+DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity
|
||||||
|
+// Set-up PHY Timing Register
|
||||||
|
+// PTR2 is untouched
|
||||||
|
+DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST
|
||||||
|
+DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST
|
||||||
|
+// Set-up PLL Control Register
|
||||||
|
+DATA 4 DDR_PHY_PLLCR0_0 0x001C0000
|
||||||
|
+DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000
|
||||||
|
+// Set-up Impedance Control Register
|
||||||
|
+DATA 4 DDR_PHY_ZQCR_0 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup)
|
||||||
|
+// ZPROG_DRAM_ODT and ZPROG_HOST_ODT
|
||||||
|
+DATA 4 DDR_PHY_ZQ0PR0_0 0x1BBBB // Optimal setting based on factory testing
|
||||||
|
+DATA 4 DDR_PHY_ZQ1PR0_0 0x1B9BB // Optimal setting based on factory testing
|
||||||
|
+// Set-up PHY Initialization Register
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x32
|
||||||
|
+// Launch initialization (set bit 0)
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x33
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+//-------------------------------------------
|
||||||
|
+// Configure registers for DRAM initialization
|
||||||
|
+//-------------------------------------------
|
||||||
|
+// Set-up Mode Register
|
||||||
|
+// MR0, MR3, MR4, MR5 MR6 are untouched
|
||||||
|
+DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST
|
||||||
|
+DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL
|
||||||
|
+DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength
|
||||||
|
+
|
||||||
|
+DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT
|
||||||
|
+DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks)
|
||||||
|
+/* LPDDR4 mode register writes for CA and DQ VREF settings */
|
||||||
|
+DATA 4 DDR_PHY_MR12_0 0x48
|
||||||
|
+DATA 4 DDR_PHY_MR14_0 0x48
|
||||||
|
+// Set-up DRAM Timing Parameters Register
|
||||||
|
+// DTPR6 is untouched
|
||||||
|
+DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP
|
||||||
|
+DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD
|
||||||
|
+DATA 4 DDR_PHY_DTPR2_0 0x006960E2 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
|
||||||
|
+DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
|
||||||
|
+DATA 4 DDR_PHY_DTPR4_0 0x00D82B0C // tRFC, tWLO, tXP
|
||||||
|
+DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR
|
||||||
|
+// Set-up PHY Timing Register
|
||||||
|
+DATA 4 DDR_PHY_PTR3_0 0x00249F00 // tDINIT0
|
||||||
|
+DATA 4 DDR_PHY_PTR4_0 0x00000960 // tDINIT1
|
||||||
|
+DATA 4 DDR_PHY_PTR5_0 0x0003A980 // tDINIT2
|
||||||
|
+DATA 4 DDR_PHY_PTR6_0 0x027004B0 // tDINIT4, tDINIT3
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+// Set-up ODT Configuration Register
|
||||||
|
+// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
|
||||||
|
+DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write
|
||||||
|
+DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled
|
||||||
|
+DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write
|
||||||
|
+DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+// Set-up AC I/O Configuration Register
|
||||||
|
+// ACIOCR1-4 are untouched
|
||||||
|
+DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2
|
||||||
|
+DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4
|
||||||
|
+// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON.
|
||||||
|
+DATA 4 DDR_PHY_ACIOCR1_0 0x44000000
|
||||||
|
+// Set-up VREF Training Control Registers
|
||||||
|
+DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12
|
||||||
|
+DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0
|
||||||
|
// Set-up DATX8 General Configuration Registers
|
||||||
|
-DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
-DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
-DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
-DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
-DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
-DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
-DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
-DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
-
|
||||||
|
- // Set-up DATX8 DX Control Register 2
|
||||||
|
- // PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA
|
||||||
|
-DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400
|
||||||
|
-
|
||||||
|
- //Enable PHY PLL to go into power down on DFI low power request
|
||||||
|
-DATA 4 DDR_PHY_PGCR4_0 0x001900A1
|
||||||
|
-
|
||||||
|
- // Set-up DATX8 IO Control Register
|
||||||
|
-DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4
|
||||||
|
+// DXnGCR0-4 are untouched
|
||||||
|
+SET_BIT 4 DDR_PHY_PGCR5_0 0x4
|
||||||
|
+DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit
|
||||||
|
+// Set-up DATX8 General Configuration Registers
|
||||||
|
+DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
+// Set-up DATX8 DX Control Register 2
|
||||||
|
+// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA
|
||||||
|
+DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400
|
||||||
|
+// Set-up DATX8 IO Control Register
|
||||||
|
+DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4
|
||||||
|
|
||||||
|
#if DDR_TRAIN_IN_DCD
|
||||||
|
-
|
||||||
|
- // Wait for bit 0 of PGSR0 to be '1'
|
||||||
|
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
-
|
||||||
|
- // Launch DRAM initialization
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x180
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x181
|
||||||
|
-
|
||||||
|
- // Wait for bit 0 of PGSR0 to be '1'
|
||||||
|
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
-
|
||||||
|
- // Launch a second time DRAM initialization due to following Synopsys PHY bug:
|
||||||
|
- // Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration"
|
||||||
|
- // Workaround: "Run DRAM Initialization twice"
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x100
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x101
|
||||||
|
-
|
||||||
|
- // Wait for bit 0 of PGSR0 to be '1'
|
||||||
|
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
-
|
||||||
|
- // Set-up Data Training Configuration Register
|
||||||
|
- // Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys
|
||||||
|
- // case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training).
|
||||||
|
- // (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED).
|
||||||
|
-DATA 4 DDR_PHY_DTCR0_0 0x000071CF // Set DTRPTN to 0xF. RFSHDT=0
|
||||||
|
-DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN=3
|
||||||
|
-
|
||||||
|
-CLR_BIT 4 DDR_PHY_DX4GCR1_0 0xFF
|
||||||
|
-
|
||||||
|
-/* -- Write leveling */
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x00000200
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x00000201
|
||||||
|
-
|
||||||
|
- // Wait for bit 0 of PGSR0 to be '1'
|
||||||
|
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
- // Check that no error occured
|
||||||
|
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000
|
||||||
|
-
|
||||||
|
-// -- Read DQS training
|
||||||
|
-// Set DQS/DQSn glitch suppression resistor for training
|
||||||
|
-DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7
|
||||||
|
-
|
||||||
|
-/* Launch training for DRC_0 */
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x00000400
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x00000401
|
||||||
|
-
|
||||||
|
- // Wait for bit 0 of PGSR0 to be '1'
|
||||||
|
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
- // Check that no error occured
|
||||||
|
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000
|
||||||
|
-
|
||||||
|
-/* Remove DQS/DQSn glitch suppression resistor */
|
||||||
|
-DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000
|
||||||
|
-
|
||||||
|
-/* DQS2DQ training, Write leveling, Deskew and eye trainings */
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x0010F800
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x0010F801
|
||||||
|
-
|
||||||
|
- // Wait for bit 0 of PGSR0 to be '1'
|
||||||
|
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
-
|
||||||
|
-/* VREF training for DRC_0 */
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x00020000
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x00020001
|
||||||
|
-
|
||||||
|
- // Wait for bit 0 of PGSR0 to be '1'
|
||||||
|
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
- // Check that no error occured
|
||||||
|
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00080000
|
||||||
|
-
|
||||||
|
- //Re-allow uMCTL2 to send commands to DDR
|
||||||
|
-CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020000
|
||||||
|
-
|
||||||
|
-//DQS Drift Registers
|
||||||
|
-CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000
|
||||||
|
-CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000
|
||||||
|
-CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000
|
||||||
|
-CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000
|
||||||
|
-DATA 4 DDR_PHY_DQSDR0_0 0x20188004
|
||||||
|
-//DATA 4 DDR_PHY_DQSDR1_0 0xA8770100
|
||||||
|
-//DATA 4 DDR_PHY_DQSDR2_0 0x00062000
|
||||||
|
-DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 // SNPS recommendation
|
||||||
|
-DATA 4 DDR_PHY_DQSDR2_0 0x00070200 // SNPS recommendation
|
||||||
|
+// Wait PHY initialization end then launch DRAM initialization
|
||||||
|
+// Wait for bit 0 of PGSR0 to be '1'
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured
|
||||||
|
+
|
||||||
|
+// Launch DRAM 0 initialization (set bit 0)
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x180
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x181
|
||||||
|
+
|
||||||
|
+// DRAM 0 initialization end
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
|
||||||
|
+
|
||||||
|
+// Launch a second time DRAM initialization due to following Synopsys PHY bug:
|
||||||
|
+// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration"
|
||||||
|
+// Workaround: "Run DRAM Initialization twice"
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x100
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x101
|
||||||
|
+
|
||||||
|
+// Wait (second time) DRAM 0 initialization end
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
|
||||||
|
+
|
||||||
|
+//---------------------------------------------------------------//
|
||||||
|
+// DATA training
|
||||||
|
+//---------------------------------------------------------------//
|
||||||
|
+// configure PHY for data training
|
||||||
|
+// The following register writes are recommended by SNPS prior to running training
|
||||||
|
+CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift
|
||||||
|
+SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation
|
||||||
|
+SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1
|
||||||
|
+// Per SNPS initialize BIST registers for VREF training
|
||||||
|
+DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16)
|
||||||
|
+DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC)
|
||||||
|
+DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC)
|
||||||
|
+
|
||||||
|
+// Set-up Data Training Configuration Register
|
||||||
|
+// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys
|
||||||
|
+// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training).
|
||||||
|
+// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED).
|
||||||
|
+DATA 4 DDR_PHY_DTCR0_0 0x000071C7 // Set DTRPTN to 0x7. RFSHDT=0
|
||||||
|
+DATA 4 DDR_PHY_DTCR1_0 0x00010236 // Set RANKEN
|
||||||
|
+
|
||||||
|
+CLR_BIT 4 DDR_PHY_DX4GCR1_0 0xFF // disable byte 4
|
||||||
|
+
|
||||||
|
+// Launch Write leveling
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x200
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x201
|
||||||
|
+// Wait Write leveling to complete
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000
|
||||||
|
+
|
||||||
|
+// Set DQS/DQSn glitch suppression resistor for training PHY0
|
||||||
|
+DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7
|
||||||
|
+// Launch Read DQS training
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x400
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x401
|
||||||
|
+// Wait Read DQS training to complete PHY0
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000
|
||||||
|
+// Remove DQS/DQSn glitch suppression resistor PHY0
|
||||||
|
+DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000
|
||||||
|
+
|
||||||
|
+// DQS2DQ training, Write leveling, Deskew and eye trainings
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x0010F800
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x0010F801
|
||||||
|
+// Wait for training to complete
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
|
||||||
|
+
|
||||||
|
+// Launch VREF training
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x00020000
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x00020001
|
||||||
|
+// Wait for training to complete
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00080000
|
||||||
|
+
|
||||||
|
+//Re-allow uMCTL2 to send commands to DDR
|
||||||
|
+CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0
|
||||||
|
+
|
||||||
|
+//DQS Drift Registers PHY0
|
||||||
|
+CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000
|
||||||
|
+CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000
|
||||||
|
+CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000
|
||||||
|
+CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000
|
||||||
|
+// Enable DQS drift detection PHY0
|
||||||
|
+DATA 4 DDR_PHY_DQSDR0_0 0x20188005
|
||||||
|
+DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000
|
||||||
|
+DATA 4 DDR_PHY_DQSDR2_0 0x00070200
|
||||||
|
+
|
||||||
|
+// Enable VT compensation
|
||||||
|
+CLR_BIT 4 DDR_PHY_PGCR6_0 0x1
|
||||||
|
|
||||||
|
//Check that controller is ready to operate
|
||||||
|
-CHECK_BITS_SET 4 DDRC_STAT_0 0x1
|
||||||
|
+CHECK_BITS_SET 4 DDRC_STAT_0 0x1
|
||||||
|
+
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,892 @@
|
||||||
|
From: Gabriel Valcazar <gabriel.valcazar@digi.com>
|
||||||
|
Date: Fri, 27 Jul 2018 12:50:37 +0200
|
||||||
|
Subject: [PATCH 2/2] cc8x: add second DCD for the 2GB variant of the cc8x
|
||||||
|
|
||||||
|
This DCD is the same as the one used for the 1GB variant, but with minor timing
|
||||||
|
and indexing changes.
|
||||||
|
|
||||||
|
Also, suffix each DCD with their corresponding UBOOT_CONFIG values so the
|
||||||
|
imx-boot recipe is able to handle them.
|
||||||
|
|
||||||
|
https://jira.digi.com/browse/DEL-6085
|
||||||
|
|
||||||
|
Signed-off-by: Gabriel Valcazar <gabriel.valcazar@digi.com>
|
||||||
|
---
|
||||||
|
iMX8QX/imx8qx_dcd_1.2GHz.cfg | 284 ---------------------
|
||||||
|
.../imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express1GB | 284 +++++++++++++++++++++
|
||||||
|
.../imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express2GB | 284 +++++++++++++++++++++
|
||||||
|
3 files changed, 568 insertions(+), 284 deletions(-)
|
||||||
|
delete mode 100644 iMX8QX/imx8qx_dcd_1.2GHz.cfg
|
||||||
|
create mode 100644 iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express1GB
|
||||||
|
create mode 100644 iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express2GB
|
||||||
|
|
||||||
|
diff --git a/iMX8QX/imx8qx_dcd_1.2GHz.cfg b/iMX8QX/imx8qx_dcd_1.2GHz.cfg
|
||||||
|
deleted file mode 100644
|
||||||
|
index abf0ad8..0000000
|
||||||
|
--- a/iMX8QX/imx8qx_dcd_1.2GHz.cfg
|
||||||
|
+++ /dev/null
|
||||||
|
@@ -1,284 +0,0 @@
|
||||||
|
-#define __ASSEMBLY__
|
||||||
|
-
|
||||||
|
-#include <ddrc_mem_map.h>
|
||||||
|
-#include <ddr_phy_mem_map.h>
|
||||||
|
-
|
||||||
|
-/*
|
||||||
|
- * Device Configuration Data (DCD)
|
||||||
|
- *
|
||||||
|
- * Each entry must have the format:
|
||||||
|
- * Addr-type Address Value
|
||||||
|
- *
|
||||||
|
- * where:
|
||||||
|
- * Addr-type register length (1,2 or 4 bytes)
|
||||||
|
- * Address absolute address of the register
|
||||||
|
- * value value to be stored in the register
|
||||||
|
- */
|
||||||
|
-
|
||||||
|
-#ifndef SCFW_DCD
|
||||||
|
-/* For 1200MHz DDR, DRC 600MHz operation */
|
||||||
|
-DATA 4 0xff190000 0x00000CC8 /* DRC0 bringup */
|
||||||
|
-#else
|
||||||
|
-/* Set the DRC rate to 600MHz, the PHY PLL will double this for the DRAM rate. */
|
||||||
|
-uint32_t rate2 = SC_600MHZ;
|
||||||
|
-pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2);
|
||||||
|
-#endif
|
||||||
|
-
|
||||||
|
-DATA 4 0x41C80208 0x1
|
||||||
|
-DATA 4 0x41C80040 0xb
|
||||||
|
-DATA 4 0x41C80204 0x1
|
||||||
|
-
|
||||||
|
-/* DRAM 0 controller configuration begin */
|
||||||
|
-DATA 4 DDRC_MSTR_0 0xC1080020 // Set LPDDR4, BL = 16 and active ranks
|
||||||
|
-DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data
|
||||||
|
-DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read
|
||||||
|
-DATA 4 DDRC_RFSHTMG_0 0x0049006C // tREFI, tRFC
|
||||||
|
-DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us
|
||||||
|
-DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us
|
||||||
|
-DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2
|
||||||
|
-DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13
|
||||||
|
-DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
|
||||||
|
-DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin
|
||||||
|
-DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC
|
||||||
|
-DATA 4 DDRC_DRAMTMG2_0 0x060E1714 // WL, RL, rd2wr, wr2rd
|
||||||
|
-DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod
|
||||||
|
-DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp
|
||||||
|
-DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke
|
||||||
|
-DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx
|
||||||
|
-DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx
|
||||||
|
-DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD
|
||||||
|
-DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD
|
||||||
|
-DATA 4 DDRC_DRAMTMG14_0 0x00000071 // txsr
|
||||||
|
-DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT
|
||||||
|
-DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval
|
||||||
|
-DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat
|
||||||
|
-DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
|
||||||
|
-DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat
|
||||||
|
-DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity
|
||||||
|
-DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation
|
||||||
|
-DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max)
|
||||||
|
-DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en
|
||||||
|
-DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0
|
||||||
|
-DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6
|
||||||
|
-DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated
|
||||||
|
-DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
|
||||||
|
-DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
|
||||||
|
-DATA 4 DDRC_ADDRMAP6_0 0x0F070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12
|
||||||
|
-DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1
|
||||||
|
-DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt
|
||||||
|
-DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0
|
||||||
|
-
|
||||||
|
-DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000
|
||||||
|
-
|
||||||
|
-DATA 4 DDRC_PWRCTL_0 0x0000010D
|
||||||
|
-
|
||||||
|
-DATA 4 0x41c80208 0x1
|
||||||
|
-DATA 4 0x41c80040 0xf
|
||||||
|
-DATA 4 0x41c80204 0x1
|
||||||
|
-
|
||||||
|
-//-------------------------------------------
|
||||||
|
-// Configure registers for PHY initialization
|
||||||
|
-// Timings are computed for 1200MHz DRAM operation
|
||||||
|
-//--------------------------------------------
|
||||||
|
-// Set-up DRAM Configuration Register
|
||||||
|
-DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank
|
||||||
|
-// Set-up byte and bit swapping registers
|
||||||
|
-DATA 4 DDR_PHY_PGCR8_0 0x0001000A
|
||||||
|
-DATA 4 DDR_PHY_DX0DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
-DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
-DATA 4 DDR_PHY_DX1DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
-DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
-DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
-DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
-DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
-DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
-DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
|
||||||
|
-DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
|
||||||
|
-// Set-up PHY General Configuration Register
|
||||||
|
-// PGCR1,4,5,6,7 are untouched
|
||||||
|
-SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1
|
||||||
|
-DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy)
|
||||||
|
-DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD
|
||||||
|
-DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity
|
||||||
|
-// Set-up PHY Timing Register
|
||||||
|
-// PTR2 is untouched
|
||||||
|
-DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST
|
||||||
|
-DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST
|
||||||
|
-// Set-up PLL Control Register
|
||||||
|
-DATA 4 DDR_PHY_PLLCR0_0 0x001C0000
|
||||||
|
-DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000
|
||||||
|
-// Set-up Impedance Control Register
|
||||||
|
-DATA 4 DDR_PHY_ZQCR_0 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup)
|
||||||
|
-// ZPROG_DRAM_ODT and ZPROG_HOST_ODT
|
||||||
|
-DATA 4 DDR_PHY_ZQ0PR0_0 0x1BBBB // Optimal setting based on factory testing
|
||||||
|
-DATA 4 DDR_PHY_ZQ1PR0_0 0x1B9BB // Optimal setting based on factory testing
|
||||||
|
-// Set-up PHY Initialization Register
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x32
|
||||||
|
-// Launch initialization (set bit 0)
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x33
|
||||||
|
-
|
||||||
|
-
|
||||||
|
-//-------------------------------------------
|
||||||
|
-// Configure registers for DRAM initialization
|
||||||
|
-//-------------------------------------------
|
||||||
|
-// Set-up Mode Register
|
||||||
|
-// MR0, MR3, MR4, MR5 MR6 are untouched
|
||||||
|
-DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST
|
||||||
|
-DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL
|
||||||
|
-DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength
|
||||||
|
-
|
||||||
|
-DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT
|
||||||
|
-DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks)
|
||||||
|
-/* LPDDR4 mode register writes for CA and DQ VREF settings */
|
||||||
|
-DATA 4 DDR_PHY_MR12_0 0x48
|
||||||
|
-DATA 4 DDR_PHY_MR14_0 0x48
|
||||||
|
-// Set-up DRAM Timing Parameters Register
|
||||||
|
-// DTPR6 is untouched
|
||||||
|
-DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP
|
||||||
|
-DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD
|
||||||
|
-DATA 4 DDR_PHY_DTPR2_0 0x006960E2 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
|
||||||
|
-DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
|
||||||
|
-DATA 4 DDR_PHY_DTPR4_0 0x00D82B0C // tRFC, tWLO, tXP
|
||||||
|
-DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR
|
||||||
|
-// Set-up PHY Timing Register
|
||||||
|
-DATA 4 DDR_PHY_PTR3_0 0x00249F00 // tDINIT0
|
||||||
|
-DATA 4 DDR_PHY_PTR4_0 0x00000960 // tDINIT1
|
||||||
|
-DATA 4 DDR_PHY_PTR5_0 0x0003A980 // tDINIT2
|
||||||
|
-DATA 4 DDR_PHY_PTR6_0 0x027004B0 // tDINIT4, tDINIT3
|
||||||
|
-
|
||||||
|
-
|
||||||
|
-// Set-up ODT Configuration Register
|
||||||
|
-// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
|
||||||
|
-DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write
|
||||||
|
-DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled
|
||||||
|
-DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write
|
||||||
|
-DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled
|
||||||
|
-
|
||||||
|
-
|
||||||
|
-// Set-up AC I/O Configuration Register
|
||||||
|
-// ACIOCR1-4 are untouched
|
||||||
|
-DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2
|
||||||
|
-DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4
|
||||||
|
-// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON.
|
||||||
|
-DATA 4 DDR_PHY_ACIOCR1_0 0x44000000
|
||||||
|
-// Set-up VREF Training Control Registers
|
||||||
|
-DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12
|
||||||
|
-DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0
|
||||||
|
-// Set-up DATX8 General Configuration Registers
|
||||||
|
-// DXnGCR0-4 are untouched
|
||||||
|
-SET_BIT 4 DDR_PHY_PGCR5_0 0x4
|
||||||
|
-DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit
|
||||||
|
-// Set-up DATX8 General Configuration Registers
|
||||||
|
-DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
-DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
-DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
-DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
-DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
-DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
-DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
-DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
-// Set-up DATX8 DX Control Register 2
|
||||||
|
-// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA
|
||||||
|
-DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400
|
||||||
|
-// Set-up DATX8 IO Control Register
|
||||||
|
-DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4
|
||||||
|
-
|
||||||
|
-#if DDR_TRAIN_IN_DCD
|
||||||
|
-// Wait PHY initialization end then launch DRAM initialization
|
||||||
|
-// Wait for bit 0 of PGSR0 to be '1'
|
||||||
|
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured
|
||||||
|
-
|
||||||
|
-// Launch DRAM 0 initialization (set bit 0)
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x180
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x181
|
||||||
|
-
|
||||||
|
-// DRAM 0 initialization end
|
||||||
|
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
|
||||||
|
-
|
||||||
|
-// Launch a second time DRAM initialization due to following Synopsys PHY bug:
|
||||||
|
-// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration"
|
||||||
|
-// Workaround: "Run DRAM Initialization twice"
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x100
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x101
|
||||||
|
-
|
||||||
|
-// Wait (second time) DRAM 0 initialization end
|
||||||
|
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
|
||||||
|
-
|
||||||
|
-//---------------------------------------------------------------//
|
||||||
|
-// DATA training
|
||||||
|
-//---------------------------------------------------------------//
|
||||||
|
-// configure PHY for data training
|
||||||
|
-// The following register writes are recommended by SNPS prior to running training
|
||||||
|
-CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift
|
||||||
|
-SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation
|
||||||
|
-CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation
|
||||||
|
-SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1
|
||||||
|
-// Per SNPS initialize BIST registers for VREF training
|
||||||
|
-DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16)
|
||||||
|
-DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC)
|
||||||
|
-DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC)
|
||||||
|
-
|
||||||
|
-// Set-up Data Training Configuration Register
|
||||||
|
-// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys
|
||||||
|
-// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training).
|
||||||
|
-// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED).
|
||||||
|
-DATA 4 DDR_PHY_DTCR0_0 0x000071C7 // Set DTRPTN to 0x7. RFSHDT=0
|
||||||
|
-DATA 4 DDR_PHY_DTCR1_0 0x00010236 // Set RANKEN
|
||||||
|
-
|
||||||
|
-CLR_BIT 4 DDR_PHY_DX4GCR1_0 0xFF // disable byte 4
|
||||||
|
-
|
||||||
|
-// Launch Write leveling
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x200
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x201
|
||||||
|
-// Wait Write leveling to complete
|
||||||
|
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000
|
||||||
|
-
|
||||||
|
-// Set DQS/DQSn glitch suppression resistor for training PHY0
|
||||||
|
-DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7
|
||||||
|
-// Launch Read DQS training
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x400
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x401
|
||||||
|
-// Wait Read DQS training to complete PHY0
|
||||||
|
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000
|
||||||
|
-// Remove DQS/DQSn glitch suppression resistor PHY0
|
||||||
|
-DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000
|
||||||
|
-
|
||||||
|
-// DQS2DQ training, Write leveling, Deskew and eye trainings
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x0010F800
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x0010F801
|
||||||
|
-// Wait for training to complete
|
||||||
|
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
|
||||||
|
-
|
||||||
|
-// Launch VREF training
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x00020000
|
||||||
|
-DATA 4 DDR_PHY_PIR_0 0x00020001
|
||||||
|
-// Wait for training to complete
|
||||||
|
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00080000
|
||||||
|
-
|
||||||
|
-//Re-allow uMCTL2 to send commands to DDR
|
||||||
|
-CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0
|
||||||
|
-
|
||||||
|
-//DQS Drift Registers PHY0
|
||||||
|
-CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000
|
||||||
|
-CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000
|
||||||
|
-CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000
|
||||||
|
-CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000
|
||||||
|
-// Enable DQS drift detection PHY0
|
||||||
|
-DATA 4 DDR_PHY_DQSDR0_0 0x20188005
|
||||||
|
-DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000
|
||||||
|
-DATA 4 DDR_PHY_DQSDR2_0 0x00070200
|
||||||
|
-
|
||||||
|
-// Enable VT compensation
|
||||||
|
-CLR_BIT 4 DDR_PHY_PGCR6_0 0x1
|
||||||
|
-
|
||||||
|
-//Check that controller is ready to operate
|
||||||
|
-CHECK_BITS_SET 4 DDRC_STAT_0 0x1
|
||||||
|
-
|
||||||
|
-#endif
|
||||||
|
diff --git a/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express1GB b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express1GB
|
||||||
|
new file mode 100644
|
||||||
|
index 0000000..abf0ad8
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express1GB
|
||||||
|
@@ -0,0 +1,284 @@
|
||||||
|
+#define __ASSEMBLY__
|
||||||
|
+
|
||||||
|
+#include <ddrc_mem_map.h>
|
||||||
|
+#include <ddr_phy_mem_map.h>
|
||||||
|
+
|
||||||
|
+/*
|
||||||
|
+ * Device Configuration Data (DCD)
|
||||||
|
+ *
|
||||||
|
+ * Each entry must have the format:
|
||||||
|
+ * Addr-type Address Value
|
||||||
|
+ *
|
||||||
|
+ * where:
|
||||||
|
+ * Addr-type register length (1,2 or 4 bytes)
|
||||||
|
+ * Address absolute address of the register
|
||||||
|
+ * value value to be stored in the register
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+#ifndef SCFW_DCD
|
||||||
|
+/* For 1200MHz DDR, DRC 600MHz operation */
|
||||||
|
+DATA 4 0xff190000 0x00000CC8 /* DRC0 bringup */
|
||||||
|
+#else
|
||||||
|
+/* Set the DRC rate to 600MHz, the PHY PLL will double this for the DRAM rate. */
|
||||||
|
+uint32_t rate2 = SC_600MHZ;
|
||||||
|
+pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2);
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
+DATA 4 0x41C80208 0x1
|
||||||
|
+DATA 4 0x41C80040 0xb
|
||||||
|
+DATA 4 0x41C80204 0x1
|
||||||
|
+
|
||||||
|
+/* DRAM 0 controller configuration begin */
|
||||||
|
+DATA 4 DDRC_MSTR_0 0xC1080020 // Set LPDDR4, BL = 16 and active ranks
|
||||||
|
+DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data
|
||||||
|
+DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read
|
||||||
|
+DATA 4 DDRC_RFSHTMG_0 0x0049006C // tREFI, tRFC
|
||||||
|
+DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us
|
||||||
|
+DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us
|
||||||
|
+DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2
|
||||||
|
+DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13
|
||||||
|
+DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
|
||||||
|
+DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin
|
||||||
|
+DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC
|
||||||
|
+DATA 4 DDRC_DRAMTMG2_0 0x060E1714 // WL, RL, rd2wr, wr2rd
|
||||||
|
+DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod
|
||||||
|
+DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp
|
||||||
|
+DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke
|
||||||
|
+DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx
|
||||||
|
+DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx
|
||||||
|
+DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD
|
||||||
|
+DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD
|
||||||
|
+DATA 4 DDRC_DRAMTMG14_0 0x00000071 // txsr
|
||||||
|
+DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT
|
||||||
|
+DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval
|
||||||
|
+DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat
|
||||||
|
+DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
|
||||||
|
+DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat
|
||||||
|
+DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity
|
||||||
|
+DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation
|
||||||
|
+DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max)
|
||||||
|
+DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en
|
||||||
|
+DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0
|
||||||
|
+DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6
|
||||||
|
+DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated
|
||||||
|
+DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
|
||||||
|
+DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
|
||||||
|
+DATA 4 DDRC_ADDRMAP6_0 0x0F070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12
|
||||||
|
+DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1
|
||||||
|
+DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt
|
||||||
|
+DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0
|
||||||
|
+
|
||||||
|
+DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000
|
||||||
|
+
|
||||||
|
+DATA 4 DDRC_PWRCTL_0 0x0000010D
|
||||||
|
+
|
||||||
|
+DATA 4 0x41c80208 0x1
|
||||||
|
+DATA 4 0x41c80040 0xf
|
||||||
|
+DATA 4 0x41c80204 0x1
|
||||||
|
+
|
||||||
|
+//-------------------------------------------
|
||||||
|
+// Configure registers for PHY initialization
|
||||||
|
+// Timings are computed for 1200MHz DRAM operation
|
||||||
|
+//--------------------------------------------
|
||||||
|
+// Set-up DRAM Configuration Register
|
||||||
|
+DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank
|
||||||
|
+// Set-up byte and bit swapping registers
|
||||||
|
+DATA 4 DDR_PHY_PGCR8_0 0x0001000A
|
||||||
|
+DATA 4 DDR_PHY_DX0DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
+DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
+DATA 4 DDR_PHY_DX1DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
+DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
+DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
+DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
+DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
+DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
+DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
|
||||||
|
+DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
|
||||||
|
+// Set-up PHY General Configuration Register
|
||||||
|
+// PGCR1,4,5,6,7 are untouched
|
||||||
|
+SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1
|
||||||
|
+DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy)
|
||||||
|
+DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD
|
||||||
|
+DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity
|
||||||
|
+// Set-up PHY Timing Register
|
||||||
|
+// PTR2 is untouched
|
||||||
|
+DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST
|
||||||
|
+DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST
|
||||||
|
+// Set-up PLL Control Register
|
||||||
|
+DATA 4 DDR_PHY_PLLCR0_0 0x001C0000
|
||||||
|
+DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000
|
||||||
|
+// Set-up Impedance Control Register
|
||||||
|
+DATA 4 DDR_PHY_ZQCR_0 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup)
|
||||||
|
+// ZPROG_DRAM_ODT and ZPROG_HOST_ODT
|
||||||
|
+DATA 4 DDR_PHY_ZQ0PR0_0 0x1BBBB // Optimal setting based on factory testing
|
||||||
|
+DATA 4 DDR_PHY_ZQ1PR0_0 0x1B9BB // Optimal setting based on factory testing
|
||||||
|
+// Set-up PHY Initialization Register
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x32
|
||||||
|
+// Launch initialization (set bit 0)
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x33
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+//-------------------------------------------
|
||||||
|
+// Configure registers for DRAM initialization
|
||||||
|
+//-------------------------------------------
|
||||||
|
+// Set-up Mode Register
|
||||||
|
+// MR0, MR3, MR4, MR5 MR6 are untouched
|
||||||
|
+DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST
|
||||||
|
+DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL
|
||||||
|
+DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength
|
||||||
|
+
|
||||||
|
+DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT
|
||||||
|
+DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks)
|
||||||
|
+/* LPDDR4 mode register writes for CA and DQ VREF settings */
|
||||||
|
+DATA 4 DDR_PHY_MR12_0 0x48
|
||||||
|
+DATA 4 DDR_PHY_MR14_0 0x48
|
||||||
|
+// Set-up DRAM Timing Parameters Register
|
||||||
|
+// DTPR6 is untouched
|
||||||
|
+DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP
|
||||||
|
+DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD
|
||||||
|
+DATA 4 DDR_PHY_DTPR2_0 0x006960E2 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
|
||||||
|
+DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
|
||||||
|
+DATA 4 DDR_PHY_DTPR4_0 0x00D82B0C // tRFC, tWLO, tXP
|
||||||
|
+DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR
|
||||||
|
+// Set-up PHY Timing Register
|
||||||
|
+DATA 4 DDR_PHY_PTR3_0 0x00249F00 // tDINIT0
|
||||||
|
+DATA 4 DDR_PHY_PTR4_0 0x00000960 // tDINIT1
|
||||||
|
+DATA 4 DDR_PHY_PTR5_0 0x0003A980 // tDINIT2
|
||||||
|
+DATA 4 DDR_PHY_PTR6_0 0x027004B0 // tDINIT4, tDINIT3
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+// Set-up ODT Configuration Register
|
||||||
|
+// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
|
||||||
|
+DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write
|
||||||
|
+DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled
|
||||||
|
+DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write
|
||||||
|
+DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+// Set-up AC I/O Configuration Register
|
||||||
|
+// ACIOCR1-4 are untouched
|
||||||
|
+DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2
|
||||||
|
+DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4
|
||||||
|
+// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON.
|
||||||
|
+DATA 4 DDR_PHY_ACIOCR1_0 0x44000000
|
||||||
|
+// Set-up VREF Training Control Registers
|
||||||
|
+DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12
|
||||||
|
+DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0
|
||||||
|
+// Set-up DATX8 General Configuration Registers
|
||||||
|
+// DXnGCR0-4 are untouched
|
||||||
|
+SET_BIT 4 DDR_PHY_PGCR5_0 0x4
|
||||||
|
+DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit
|
||||||
|
+// Set-up DATX8 General Configuration Registers
|
||||||
|
+DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
+// Set-up DATX8 DX Control Register 2
|
||||||
|
+// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA
|
||||||
|
+DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400
|
||||||
|
+// Set-up DATX8 IO Control Register
|
||||||
|
+DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4
|
||||||
|
+
|
||||||
|
+#if DDR_TRAIN_IN_DCD
|
||||||
|
+// Wait PHY initialization end then launch DRAM initialization
|
||||||
|
+// Wait for bit 0 of PGSR0 to be '1'
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured
|
||||||
|
+
|
||||||
|
+// Launch DRAM 0 initialization (set bit 0)
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x180
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x181
|
||||||
|
+
|
||||||
|
+// DRAM 0 initialization end
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
|
||||||
|
+
|
||||||
|
+// Launch a second time DRAM initialization due to following Synopsys PHY bug:
|
||||||
|
+// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration"
|
||||||
|
+// Workaround: "Run DRAM Initialization twice"
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x100
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x101
|
||||||
|
+
|
||||||
|
+// Wait (second time) DRAM 0 initialization end
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
|
||||||
|
+
|
||||||
|
+//---------------------------------------------------------------//
|
||||||
|
+// DATA training
|
||||||
|
+//---------------------------------------------------------------//
|
||||||
|
+// configure PHY for data training
|
||||||
|
+// The following register writes are recommended by SNPS prior to running training
|
||||||
|
+CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift
|
||||||
|
+SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation
|
||||||
|
+SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1
|
||||||
|
+// Per SNPS initialize BIST registers for VREF training
|
||||||
|
+DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16)
|
||||||
|
+DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC)
|
||||||
|
+DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC)
|
||||||
|
+
|
||||||
|
+// Set-up Data Training Configuration Register
|
||||||
|
+// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys
|
||||||
|
+// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training).
|
||||||
|
+// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED).
|
||||||
|
+DATA 4 DDR_PHY_DTCR0_0 0x000071C7 // Set DTRPTN to 0x7. RFSHDT=0
|
||||||
|
+DATA 4 DDR_PHY_DTCR1_0 0x00010236 // Set RANKEN
|
||||||
|
+
|
||||||
|
+CLR_BIT 4 DDR_PHY_DX4GCR1_0 0xFF // disable byte 4
|
||||||
|
+
|
||||||
|
+// Launch Write leveling
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x200
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x201
|
||||||
|
+// Wait Write leveling to complete
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000
|
||||||
|
+
|
||||||
|
+// Set DQS/DQSn glitch suppression resistor for training PHY0
|
||||||
|
+DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7
|
||||||
|
+// Launch Read DQS training
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x400
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x401
|
||||||
|
+// Wait Read DQS training to complete PHY0
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000
|
||||||
|
+// Remove DQS/DQSn glitch suppression resistor PHY0
|
||||||
|
+DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000
|
||||||
|
+
|
||||||
|
+// DQS2DQ training, Write leveling, Deskew and eye trainings
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x0010F800
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x0010F801
|
||||||
|
+// Wait for training to complete
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
|
||||||
|
+
|
||||||
|
+// Launch VREF training
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x00020000
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x00020001
|
||||||
|
+// Wait for training to complete
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00080000
|
||||||
|
+
|
||||||
|
+//Re-allow uMCTL2 to send commands to DDR
|
||||||
|
+CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0
|
||||||
|
+
|
||||||
|
+//DQS Drift Registers PHY0
|
||||||
|
+CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000
|
||||||
|
+CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000
|
||||||
|
+CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000
|
||||||
|
+CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000
|
||||||
|
+// Enable DQS drift detection PHY0
|
||||||
|
+DATA 4 DDR_PHY_DQSDR0_0 0x20188005
|
||||||
|
+DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000
|
||||||
|
+DATA 4 DDR_PHY_DQSDR2_0 0x00070200
|
||||||
|
+
|
||||||
|
+// Enable VT compensation
|
||||||
|
+CLR_BIT 4 DDR_PHY_PGCR6_0 0x1
|
||||||
|
+
|
||||||
|
+//Check that controller is ready to operate
|
||||||
|
+CHECK_BITS_SET 4 DDRC_STAT_0 0x1
|
||||||
|
+
|
||||||
|
+#endif
|
||||||
|
diff --git a/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express2GB b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express2GB
|
||||||
|
new file mode 100644
|
||||||
|
index 0000000..bb37fd5
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express2GB
|
||||||
|
@@ -0,0 +1,284 @@
|
||||||
|
+#define __ASSEMBLY__
|
||||||
|
+
|
||||||
|
+#include <ddrc_mem_map.h>
|
||||||
|
+#include <ddr_phy_mem_map.h>
|
||||||
|
+
|
||||||
|
+/*
|
||||||
|
+ * Device Configuration Data (DCD)
|
||||||
|
+ *
|
||||||
|
+ * Each entry must have the format:
|
||||||
|
+ * Addr-type Address Value
|
||||||
|
+ *
|
||||||
|
+ * where:
|
||||||
|
+ * Addr-type register length (1,2 or 4 bytes)
|
||||||
|
+ * Address absolute address of the register
|
||||||
|
+ * value value to be stored in the register
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+#ifndef SCFW_DCD
|
||||||
|
+/* For 1200MHz DDR, DRC 600MHz operation */
|
||||||
|
+DATA 4 0xff190000 0x00000CC8 /* DRC0 bringup */
|
||||||
|
+#else
|
||||||
|
+/* Set the DRC rate to 600MHz, the PHY PLL will double this for the DRAM rate. */
|
||||||
|
+uint32_t rate2 = SC_600MHZ;
|
||||||
|
+pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2);
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
+DATA 4 0x41C80208 0x1
|
||||||
|
+DATA 4 0x41C80040 0xb
|
||||||
|
+DATA 4 0x41C80204 0x1
|
||||||
|
+
|
||||||
|
+/* DRAM 0 controller configuration begin */
|
||||||
|
+DATA 4 DDRC_MSTR_0 0xC1080020 // Set LPDDR4, BL = 16 and active ranks
|
||||||
|
+DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data
|
||||||
|
+DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read
|
||||||
|
+DATA 4 DDRC_RFSHTMG_0 0x004900A8 // tREFI, tRFC
|
||||||
|
+DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us
|
||||||
|
+DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us
|
||||||
|
+DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2
|
||||||
|
+DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13
|
||||||
|
+DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
|
||||||
|
+DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin
|
||||||
|
+DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC
|
||||||
|
+DATA 4 DDRC_DRAMTMG2_0 0x060E1714 // WL, RL, rd2wr, wr2rd
|
||||||
|
+DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod
|
||||||
|
+DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp
|
||||||
|
+DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke
|
||||||
|
+DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx
|
||||||
|
+DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx
|
||||||
|
+DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD
|
||||||
|
+DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD
|
||||||
|
+DATA 4 DDRC_DRAMTMG14_0 0x000000AD // txsr
|
||||||
|
+DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT
|
||||||
|
+DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval
|
||||||
|
+DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat
|
||||||
|
+DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
|
||||||
|
+DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat
|
||||||
|
+DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity
|
||||||
|
+DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation
|
||||||
|
+DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max)
|
||||||
|
+DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en
|
||||||
|
+DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0
|
||||||
|
+DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6
|
||||||
|
+DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated
|
||||||
|
+DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
|
||||||
|
+DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
|
||||||
|
+DATA 4 DDRC_ADDRMAP6_0 0x07070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12
|
||||||
|
+DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1
|
||||||
|
+DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt
|
||||||
|
+DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0
|
||||||
|
+
|
||||||
|
+DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000
|
||||||
|
+
|
||||||
|
+DATA 4 DDRC_PWRCTL_0 0x0000010D
|
||||||
|
+
|
||||||
|
+DATA 4 0x41c80208 0x1
|
||||||
|
+DATA 4 0x41c80040 0xf
|
||||||
|
+DATA 4 0x41c80204 0x1
|
||||||
|
+
|
||||||
|
+//-------------------------------------------
|
||||||
|
+// Configure registers for PHY initialization
|
||||||
|
+// Timings are computed for 1200MHz DRAM operation
|
||||||
|
+//--------------------------------------------
|
||||||
|
+// Set-up DRAM Configuration Register
|
||||||
|
+DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank
|
||||||
|
+// Set-up byte and bit swapping registers
|
||||||
|
+DATA 4 DDR_PHY_PGCR8_0 0x0001000A
|
||||||
|
+DATA 4 DDR_PHY_DX0DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
+DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
+DATA 4 DDR_PHY_DX1DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
+DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
+DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
+DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
+DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
|
||||||
|
+DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
|
||||||
|
+DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
|
||||||
|
+DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
|
||||||
|
+// Set-up PHY General Configuration Register
|
||||||
|
+// PGCR1,4,5,6,7 are untouched
|
||||||
|
+SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1
|
||||||
|
+DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy)
|
||||||
|
+DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD
|
||||||
|
+DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity
|
||||||
|
+// Set-up PHY Timing Register
|
||||||
|
+// PTR2 is untouched
|
||||||
|
+DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST
|
||||||
|
+DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST
|
||||||
|
+// Set-up PLL Control Register
|
||||||
|
+DATA 4 DDR_PHY_PLLCR0_0 0x001C0000
|
||||||
|
+DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000
|
||||||
|
+// Set-up Impedance Control Register
|
||||||
|
+DATA 4 DDR_PHY_ZQCR_0 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup)
|
||||||
|
+// ZPROG_DRAM_ODT and ZPROG_HOST_ODT
|
||||||
|
+DATA 4 DDR_PHY_ZQ0PR0_0 0x1BBBB // Optimal setting based on factory testing
|
||||||
|
+DATA 4 DDR_PHY_ZQ1PR0_0 0x1B9BB // Optimal setting based on factory testing
|
||||||
|
+// Set-up PHY Initialization Register
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x32
|
||||||
|
+// Launch initialization (set bit 0)
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x33
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+//-------------------------------------------
|
||||||
|
+// Configure registers for DRAM initialization
|
||||||
|
+//-------------------------------------------
|
||||||
|
+// Set-up Mode Register
|
||||||
|
+// MR0, MR3, MR4, MR5 MR6 are untouched
|
||||||
|
+DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST
|
||||||
|
+DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL
|
||||||
|
+DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength
|
||||||
|
+
|
||||||
|
+DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT
|
||||||
|
+DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks)
|
||||||
|
+/* LPDDR4 mode register writes for CA and DQ VREF settings */
|
||||||
|
+DATA 4 DDR_PHY_MR12_0 0x48
|
||||||
|
+DATA 4 DDR_PHY_MR14_0 0x48
|
||||||
|
+// Set-up DRAM Timing Parameters Register
|
||||||
|
+// DTPR6 is untouched
|
||||||
|
+DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP
|
||||||
|
+DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD
|
||||||
|
+DATA 4 DDR_PHY_DTPR2_0 0x0069615A // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
|
||||||
|
+DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
|
||||||
|
+DATA 4 DDR_PHY_DTPR4_0 0x01502B0C // tRFC, tWLO, tXP
|
||||||
|
+DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR
|
||||||
|
+// Set-up PHY Timing Register
|
||||||
|
+DATA 4 DDR_PHY_PTR3_0 0x00249F00 // tDINIT0
|
||||||
|
+DATA 4 DDR_PHY_PTR4_0 0x00000960 // tDINIT1
|
||||||
|
+DATA 4 DDR_PHY_PTR5_0 0x0003A980 // tDINIT2
|
||||||
|
+DATA 4 DDR_PHY_PTR6_0 0x027004B0 // tDINIT4, tDINIT3
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+// Set-up ODT Configuration Register
|
||||||
|
+// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
|
||||||
|
+DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write
|
||||||
|
+DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled
|
||||||
|
+DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write
|
||||||
|
+DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+// Set-up AC I/O Configuration Register
|
||||||
|
+// ACIOCR1-4 are untouched
|
||||||
|
+DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2
|
||||||
|
+DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4
|
||||||
|
+// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON.
|
||||||
|
+DATA 4 DDR_PHY_ACIOCR1_0 0x44000000
|
||||||
|
+// Set-up VREF Training Control Registers
|
||||||
|
+DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12
|
||||||
|
+DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0
|
||||||
|
+// Set-up DATX8 General Configuration Registers
|
||||||
|
+// DXnGCR0-4 are untouched
|
||||||
|
+SET_BIT 4 DDR_PHY_PGCR5_0 0x4
|
||||||
|
+DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit
|
||||||
|
+// Set-up DATX8 General Configuration Registers
|
||||||
|
+DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
+DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
|
||||||
|
+// Set-up DATX8 DX Control Register 2
|
||||||
|
+// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA
|
||||||
|
+DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400
|
||||||
|
+// Set-up DATX8 IO Control Register
|
||||||
|
+DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4
|
||||||
|
+
|
||||||
|
+#if DDR_TRAIN_IN_DCD
|
||||||
|
+// Wait PHY initialization end then launch DRAM initialization
|
||||||
|
+// Wait for bit 0 of PGSR0 to be '1'
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured
|
||||||
|
+
|
||||||
|
+// Launch DRAM 0 initialization (set bit 0)
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x180
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x181
|
||||||
|
+
|
||||||
|
+// DRAM 0 initialization end
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
|
||||||
|
+
|
||||||
|
+// Launch a second time DRAM initialization due to following Synopsys PHY bug:
|
||||||
|
+// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration"
|
||||||
|
+// Workaround: "Run DRAM Initialization twice"
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x100
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x101
|
||||||
|
+
|
||||||
|
+// Wait (second time) DRAM 0 initialization end
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
|
||||||
|
+
|
||||||
|
+//---------------------------------------------------------------//
|
||||||
|
+// DATA training
|
||||||
|
+//---------------------------------------------------------------//
|
||||||
|
+// configure PHY for data training
|
||||||
|
+// The following register writes are recommended by SNPS prior to running training
|
||||||
|
+CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift
|
||||||
|
+SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation
|
||||||
|
+SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1
|
||||||
|
+// Per SNPS initialize BIST registers for VREF training
|
||||||
|
+DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16)
|
||||||
|
+DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC)
|
||||||
|
+DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC)
|
||||||
|
+
|
||||||
|
+// Set-up Data Training Configuration Register
|
||||||
|
+// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys
|
||||||
|
+// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training).
|
||||||
|
+// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED).
|
||||||
|
+DATA 4 DDR_PHY_DTCR0_0 0x000071C7 // Set DTRPTN to 0x7. RFSHDT=0
|
||||||
|
+DATA 4 DDR_PHY_DTCR1_0 0x00010236 // Set RANKEN
|
||||||
|
+
|
||||||
|
+CLR_BIT 4 DDR_PHY_DX4GCR1_0 0xFF // disable byte 4
|
||||||
|
+
|
||||||
|
+// Launch Write leveling
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x200
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x201
|
||||||
|
+// Wait Write leveling to complete
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000
|
||||||
|
+
|
||||||
|
+// Set DQS/DQSn glitch suppression resistor for training PHY0
|
||||||
|
+DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7
|
||||||
|
+// Launch Read DQS training
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x400
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x401
|
||||||
|
+// Wait Read DQS training to complete PHY0
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000
|
||||||
|
+// Remove DQS/DQSn glitch suppression resistor PHY0
|
||||||
|
+DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000
|
||||||
|
+
|
||||||
|
+// DQS2DQ training, Write leveling, Deskew and eye trainings
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x0010F800
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x0010F801
|
||||||
|
+// Wait for training to complete
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
|
||||||
|
+
|
||||||
|
+// Launch VREF training
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x00020000
|
||||||
|
+DATA 4 DDR_PHY_PIR_0 0x00020001
|
||||||
|
+// Wait for training to complete
|
||||||
|
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||||
|
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00080000
|
||||||
|
+
|
||||||
|
+//Re-allow uMCTL2 to send commands to DDR
|
||||||
|
+CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0
|
||||||
|
+
|
||||||
|
+//DQS Drift Registers PHY0
|
||||||
|
+CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000
|
||||||
|
+CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000
|
||||||
|
+CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000
|
||||||
|
+CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000
|
||||||
|
+// Enable DQS drift detection PHY0
|
||||||
|
+DATA 4 DDR_PHY_DQSDR0_0 0x20188005
|
||||||
|
+DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000
|
||||||
|
+DATA 4 DDR_PHY_DQSDR2_0 0x00070200
|
||||||
|
+
|
||||||
|
+// Enable VT compensation
|
||||||
|
+CLR_BIT 4 DDR_PHY_PGCR6_0 0x1
|
||||||
|
+
|
||||||
|
+//Check that controller is ready to operate
|
||||||
|
+CHECK_BITS_SET 4 DDRC_STAT_0 0x1
|
||||||
|
+
|
||||||
|
+#endif
|
||||||
|
|
@ -0,0 +1,230 @@
|
||||||
|
# Copyright 2017-2018 NXP
|
||||||
|
|
||||||
|
DESCRIPTION = "Generate Boot Loader for i.MX8 device"
|
||||||
|
LICENSE = "GPLv2"
|
||||||
|
LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6"
|
||||||
|
SECTION = "BSP"
|
||||||
|
|
||||||
|
require imx-mkimage_git.inc
|
||||||
|
|
||||||
|
inherit deploy
|
||||||
|
|
||||||
|
SRC_URI_append = " \
|
||||||
|
file://0001-cc8x-configure-DDRC-for-Micron-MT53B256M32D1.patch \
|
||||||
|
file://0002-cc8x-add-second-DCD-for-the-2GB-variant-of-the-cc8x.patch \
|
||||||
|
"
|
||||||
|
|
||||||
|
# Add CFLAGS with native INCDIR & LIBDIR for imx-mkimage build
|
||||||
|
CFLAGS = "-O2 -Wall -std=c99 -static -I ${STAGING_INCDIR_NATIVE} -L ${STAGING_LIBDIR_NATIVE}"
|
||||||
|
|
||||||
|
BOOT_TOOLS = "imx-boot-tools"
|
||||||
|
BOOT_NAME = "imx-boot"
|
||||||
|
PROVIDES = "${BOOT_NAME}"
|
||||||
|
|
||||||
|
IMX_FIRMWARE = "imx-sc-firmware"
|
||||||
|
IMX_FIRMWARE_mx8mq = "firmware-imx"
|
||||||
|
IMX_FIRMWARE_mx8qxp = "firmware-imx imx-sc-firmware"
|
||||||
|
DEPENDS += " \
|
||||||
|
u-boot \
|
||||||
|
${IMX_FIRMWARE} \
|
||||||
|
imx-atf \
|
||||||
|
${@bb.utils.contains('COMBINED_FEATURES', 'optee', 'optee-os-imx', '', d)} \
|
||||||
|
"
|
||||||
|
DEPENDS_append_mx8mq = " dtc-native"
|
||||||
|
|
||||||
|
# For i.MX 8, this package aggregates the imx-m4-demos
|
||||||
|
# output. Note that this aggregation replaces the aggregation
|
||||||
|
# that would otherwise be done in the image build as controlled
|
||||||
|
# by IMAGE_BOOTFILES_DEPENDS and IMAGE_BOOTFILES in image_types_fsl.bbclass
|
||||||
|
IMX_M4_DEMOS = ""
|
||||||
|
IMX_M4_DEMOS_mx8qm = "imx-m4-demos:do_deploy"
|
||||||
|
IMX_M4_DEMOS_mx8qxp = "imx-m4-demos:do_deploy"
|
||||||
|
|
||||||
|
# This package aggregates output deployed by other packages,
|
||||||
|
# so set the appropriate dependencies
|
||||||
|
do_compile[depends] += " \
|
||||||
|
virtual/bootloader:do_deploy \
|
||||||
|
${@' '.join('%s:do_deploy' % r for r in '${IMX_FIRMWARE}'.split() )} \
|
||||||
|
imx-atf:do_deploy \
|
||||||
|
${IMX_M4_DEMOS} \
|
||||||
|
${@bb.utils.contains('COMBINED_FEATURES', 'optee', 'optee-os-imx:do_deploy', '', d)} \
|
||||||
|
"
|
||||||
|
|
||||||
|
SC_FIRMWARE_NAME ?= "scfw_tcm.bin"
|
||||||
|
|
||||||
|
ATF_MACHINE_NAME ?= "bl31-imx8qm.bin"
|
||||||
|
ATF_MACHINE_NAME_mx8qm = "bl31-imx8qm.bin"
|
||||||
|
ATF_MACHINE_NAME_mx8qxp = "bl31-imx8qxp.bin"
|
||||||
|
ATF_MACHINE_NAME_mx8mq = "bl31-imx8mq.bin"
|
||||||
|
|
||||||
|
DCD_NAME ?= "imx8qm_dcd.cfg.tmp"
|
||||||
|
DCD_NAME_mx8qm = "imx8qm_dcd.cfg.tmp"
|
||||||
|
DCD_NAME_mx8qxp = "imx8qx_dcd.cfg.tmp"
|
||||||
|
|
||||||
|
DCD_SRC_NAME = "imx8qx_dcd_1.2GHz.cfg"
|
||||||
|
|
||||||
|
UBOOT_NAME = "u-boot-${MACHINE}.bin"
|
||||||
|
BOOT_CONFIG_MACHINE = "${BOOT_NAME}"
|
||||||
|
|
||||||
|
TOOLS_NAME ?= "mkimage_imx8"
|
||||||
|
|
||||||
|
SOC_TARGET ?= "iMX8QM"
|
||||||
|
SOC_TARGET_mx8qm = "iMX8QM"
|
||||||
|
SOC_TARGET_mx8qxp = "iMX8QX"
|
||||||
|
SOC_TARGET_mx8mq = "iMX8M"
|
||||||
|
|
||||||
|
DEPLOY_OPTEE = "false"
|
||||||
|
DEPLOY_OPTEE_mx8mq = "${@bb.utils.contains('COMBINED_FEATURES', 'optee', 'true', 'false', d)}"
|
||||||
|
|
||||||
|
IMXBOOT_TARGETS ?= "${@bb.utils.contains('UBOOT_CONFIG', 'fspi', 'flash_flexspi', \
|
||||||
|
bb.utils.contains('UBOOT_CONFIG', 'nand', 'flash_nand', \
|
||||||
|
'flash_multi_cores flash flash_dcd', d), d)}"
|
||||||
|
IMXBOOT_TARGETS_mx8qxp = "${@bb.utils.contains('UBOOT_CONFIG', 'fspi', 'flash_flexspi', \
|
||||||
|
bb.utils.contains('UBOOT_CONFIG', 'nand', 'flash_nand', \
|
||||||
|
'flash_all flash', d), d)}"
|
||||||
|
IMXBOOT_TARGETS_ccimx8x = "${@bb.utils.contains('UBOOT_CONFIG', 'fspi', 'flash_flexspi_a0', \
|
||||||
|
bb.utils.contains('UBOOT_CONFIG', 'nand', 'flash_nand_a0', \
|
||||||
|
'flash_dcd_a0 flash_multi_cores_a0', d), d)}"
|
||||||
|
IMXBOOT_TARGETS_imx8qxpddr3arm2 = "flash_ddr3_dcd_a0"
|
||||||
|
|
||||||
|
S = "${WORKDIR}/git"
|
||||||
|
|
||||||
|
do_compile () {
|
||||||
|
if [ "${SOC_TARGET}" = "iMX8M" ]; then
|
||||||
|
echo 8MQ boot binary build
|
||||||
|
for ddr_firmware in ${DDR_FIRMWARE_NAME}; do
|
||||||
|
echo "Copy ddr_firmware: ${ddr_firmware} from ${DEPLOY_DIR_IMAGE} -> ${S}/${SOC_TARGET} "
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/${ddr_firmware} ${S}/${SOC_TARGET}/
|
||||||
|
done
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/signed_hdmi_imx8m.bin ${S}/${SOC_TARGET}/
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/u-boot-spl.bin-${MACHINE}-${UBOOT_CONFIG} ${S}/${SOC_TARGET}/u-boot-spl.bin
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/${BOOT_TOOLS}/${UBOOT_DTB_NAME} ${S}/${SOC_TARGET}/
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/${BOOT_TOOLS}/u-boot-nodtb.bin ${S}/${SOC_TARGET}/
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/${BOOT_TOOLS}/mkimage_uboot ${S}/${SOC_TARGET}/
|
||||||
|
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/${BOOT_TOOLS}/${ATF_MACHINE_NAME} ${S}/${SOC_TARGET}/bl31.bin
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/${UBOOT_NAME} ${S}/${SOC_TARGET}/u-boot.bin
|
||||||
|
|
||||||
|
elif [ "${SOC_TARGET}" = "iMX8QM" ]; then
|
||||||
|
echo 8QM boot binary build
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/${BOOT_TOOLS}/${SC_FIRMWARE_NAME} ${S}/${SOC_TARGET}/scfw_tcm.bin
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/${BOOT_TOOLS}/${ATF_MACHINE_NAME} ${S}/${SOC_TARGET}/bl31.bin
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/${UBOOT_NAME} ${S}/${SOC_TARGET}/u-boot.bin
|
||||||
|
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/imx8qm_m4_0_TCM_rpmsg_lite_pingpong_rtos_linux_remote.bin ${S}/${SOC_TARGET}/m40_tcm.bin
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/imx8qm_m4_1_TCM_rpmsg_lite_pingpong_rtos_linux_remote.bin ${S}/${SOC_TARGET}/m41_tcm.bin
|
||||||
|
|
||||||
|
else
|
||||||
|
echo 8QX boot binary build
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/imx8qx_m4_TCM_rpmsg_lite_pingpong_rtos_linux_remote.bin ${S}/${SOC_TARGET}/m40_tcm.bin
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/imx8qx_m4_TCM_rpmsg_lite_pingpong_rtos_linux_remote.bin ${S}/${SOC_TARGET}/CM4.bin
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/ahab-container.img ${S}/${SOC_TARGET}/
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/${BOOT_TOOLS}/${SC_FIRMWARE_NAME} ${S}/${SOC_TARGET}/scfw_tcm.bin
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/${BOOT_TOOLS}/${ATF_MACHINE_NAME} ${S}/${SOC_TARGET}/bl31.bin
|
||||||
|
for type in ${UBOOT_CONFIG}; do
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/${UBOOT_NAME}-${type} ${S}/${SOC_TARGET}/u-boot.bin-${type}
|
||||||
|
done
|
||||||
|
fi
|
||||||
|
|
||||||
|
# Copy TEE binary to SoC target folder to mkimage
|
||||||
|
if ${DEPLOY_OPTEE}; then
|
||||||
|
cp ${DEPLOY_DIR_IMAGE}/tee.bin ${S}/${SOC_TARGET}/
|
||||||
|
fi
|
||||||
|
|
||||||
|
# mkimage for i.MX8
|
||||||
|
for type in ${UBOOT_CONFIG}; do
|
||||||
|
cd ${S}/${SOC_TARGET}
|
||||||
|
ln -sf u-boot.bin-${type} u-boot.bin
|
||||||
|
ln -sf ${DCD_SRC_NAME}-${type} ${DCD_SRC_NAME}
|
||||||
|
cd -
|
||||||
|
for target in ${IMXBOOT_TARGETS}; do
|
||||||
|
echo "building ${SOC_TARGET} - ${type} - ${target}"
|
||||||
|
make SOC=${SOC_TARGET} ${target}
|
||||||
|
if [ -e "${S}/${SOC_TARGET}/flash.bin" ]; then
|
||||||
|
cp ${S}/${SOC_TARGET}/flash.bin ${S}/${BOOT_CONFIG_MACHINE}-${type}.bin-${target}
|
||||||
|
fi
|
||||||
|
done
|
||||||
|
cp ${S}/${SOC_TARGET}/${DCD_NAME} ${S}/${SOC_TARGET}/${DCD_NAME}-${type}
|
||||||
|
rm ${S}/${SOC_TARGET}/${DCD_SRC_NAME}
|
||||||
|
rm ${S}/${SOC_TARGET}/u-boot.bin
|
||||||
|
# Remove u-boot-atf.bin so it gets generated with the next iteration's U-Boot
|
||||||
|
rm ${S}/${SOC_TARGET}/u-boot-atf.bin
|
||||||
|
done
|
||||||
|
}
|
||||||
|
|
||||||
|
SYSROOT_DIRS += "/boot"
|
||||||
|
|
||||||
|
do_install () {
|
||||||
|
install -d ${D}/boot
|
||||||
|
for type in ${UBOOT_CONFIG}; do
|
||||||
|
for target in ${IMXBOOT_TARGETS}; do
|
||||||
|
install -m 0644 ${S}/${BOOT_CONFIG_MACHINE}-${type}.bin-${target} ${D}/boot/
|
||||||
|
done
|
||||||
|
done
|
||||||
|
}
|
||||||
|
|
||||||
|
DEPLOYDIR_IMXBOOT = "${BOOT_TOOLS}"
|
||||||
|
do_deploy () {
|
||||||
|
install -d ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
|
||||||
|
|
||||||
|
# copy the tool mkimage to deploy path and sc fw, dcd and uboot
|
||||||
|
for type in ${UBOOT_CONFIG}; do
|
||||||
|
install -m 0644 ${DEPLOY_DIR_IMAGE}/${UBOOT_NAME}-${type} ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
|
||||||
|
done
|
||||||
|
if [ "${SOC_TARGET}" = "iMX8M" ]; then
|
||||||
|
install -m 0644 ${DEPLOY_DIR_IMAGE}/u-boot-spl.bin-${MACHINE}-${UBOOT_CONFIG} ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
|
||||||
|
for ddr_firmware in ${DDR_FIRMWARE_NAME}; do
|
||||||
|
install -m 0644 ${DEPLOY_DIR_IMAGE}/${ddr_firmware} ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
|
||||||
|
done
|
||||||
|
install -m 0644 ${DEPLOY_DIR_IMAGE}/signed_hdmi*.bin ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
|
||||||
|
|
||||||
|
install -m 0755 ${S}/${SOC_TARGET}/${TOOLS_NAME} ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
|
||||||
|
|
||||||
|
install -m 0755 ${S}/${SOC_TARGET}/mkimage_fit_atf.sh ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
|
||||||
|
elif [ "${SOC_TARGET}" = "iMX8QM" ]; then
|
||||||
|
install -m 0644 ${S}/${SOC_TARGET}/${DCD_NAME} ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
|
||||||
|
|
||||||
|
install -m 0755 ${S}/${TOOLS_NAME} ${DEPLOYDIR}/${BOOT_TOOLS}
|
||||||
|
else
|
||||||
|
# the DCD only needs to get copied when using an A0 CPU
|
||||||
|
for type in ${UBOOT_CONFIG}; do
|
||||||
|
install -m 0644 ${S}/${SOC_TARGET}/${DCD_NAME}-${type} ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
|
||||||
|
done
|
||||||
|
install -m 0644 ${S}/${SOC_TARGET}/ahab-container.img ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
|
||||||
|
install -m 0644 ${S}/${SOC_TARGET}/m40_tcm.bin ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
|
||||||
|
install -m 0644 ${S}/${SOC_TARGET}/CM4.bin ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
|
||||||
|
|
||||||
|
install -m 0755 ${S}/${TOOLS_NAME} ${DEPLOYDIR}/${BOOT_TOOLS}
|
||||||
|
fi
|
||||||
|
|
||||||
|
# copy tee.bin to deploy path
|
||||||
|
if "${DEPLOY_OPTEE}"; then
|
||||||
|
install -m 0644 ${DEPLOY_DIR_IMAGE}/tee.bin ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
|
||||||
|
fi
|
||||||
|
|
||||||
|
# copy makefile (soc.mak) for reference
|
||||||
|
install -m 0644 ${S}/${SOC_TARGET}/soc.mak ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
|
||||||
|
|
||||||
|
# copy the generated boot image to deploy path
|
||||||
|
for type in ${UBOOT_CONFIG}; do
|
||||||
|
IMAGE_IMXBOOT_TARGET=""
|
||||||
|
for target in ${IMXBOOT_TARGETS}; do
|
||||||
|
# Use first "target" as IMAGE_IMXBOOT_TARGET
|
||||||
|
if [ "$IMAGE_IMXBOOT_TARGET" = "" ]; then
|
||||||
|
IMAGE_IMXBOOT_TARGET="$target"
|
||||||
|
echo "Set boot target as $IMAGE_IMXBOOT_TARGET"
|
||||||
|
fi
|
||||||
|
install -m 0644 ${S}/${BOOT_CONFIG_MACHINE}-${type}.bin-${target} ${DEPLOYDIR}
|
||||||
|
done
|
||||||
|
cd ${DEPLOYDIR}
|
||||||
|
ln -sf ${BOOT_CONFIG_MACHINE}-${type}.bin-${IMAGE_IMXBOOT_TARGET} ${BOOT_CONFIG_MACHINE}-${type}.bin
|
||||||
|
cd -
|
||||||
|
done
|
||||||
|
}
|
||||||
|
|
||||||
|
addtask deploy before do_build after do_compile
|
||||||
|
|
||||||
|
FILES_${PN} = "/boot"
|
||||||
|
|
||||||
|
COMPATIBLE_MACHINE = "(mx8qm|mx8qxp|mx8mq)"
|
||||||
|
PACKAGE_ARCH = "${MACHINE_ARCH}"
|
||||||
|
|
@ -0,0 +1,5 @@
|
||||||
|
# Copyright (C) 2018 Digi International, Inc.
|
||||||
|
|
||||||
|
SRC_URI_append = " \
|
||||||
|
file://0001-cc8x-configure-DDRC-for-Micron-MT53B256M32D1.patch \
|
||||||
|
"
|
||||||
|
|
@ -0,0 +1,43 @@
|
||||||
|
# Copyright (C) 2016 Freescale Semiconductor
|
||||||
|
# Copyright 2017 NXP
|
||||||
|
|
||||||
|
DESCRIPTION = "i.MX make image"
|
||||||
|
LICENSE = "GPLv2"
|
||||||
|
LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6"
|
||||||
|
SECTION = "BSP"
|
||||||
|
|
||||||
|
require imx-mkimage_git.inc
|
||||||
|
|
||||||
|
inherit native deploy
|
||||||
|
|
||||||
|
S = "${WORKDIR}/git"
|
||||||
|
|
||||||
|
CFLAGS = "-O2 -Wall -std=c99 -static -I ${STAGING_INCDIR} -L ${STAGING_LIBDIR}"
|
||||||
|
|
||||||
|
do_compile () {
|
||||||
|
cd ${S}
|
||||||
|
oe_runmake clean
|
||||||
|
oe_runmake bin
|
||||||
|
|
||||||
|
oe_runmake -C iMX8M -f soc.mak mkimage_imx8
|
||||||
|
|
||||||
|
oe_runmake -C iMX8QM -f soc.mak imx8qm_dcd.cfg.tmp
|
||||||
|
oe_runmake -C iMX8QX -f soc.mak imx8qx_dcd.cfg.tmp
|
||||||
|
}
|
||||||
|
|
||||||
|
BOOT_TOOLS = "imx-boot-tools"
|
||||||
|
SYSROOT_DIRS += "/boot"
|
||||||
|
|
||||||
|
do_install () {
|
||||||
|
cd ${S}
|
||||||
|
install -d ${D}${bindir}
|
||||||
|
install -m 0755 iMX8M/mkimage_imx8 ${D}${bindir}/mkimage_imx8m
|
||||||
|
install -m 0755 mkimage_imx8 ${D}${bindir}/mkimage_imx8
|
||||||
|
}
|
||||||
|
|
||||||
|
do_deploy () {
|
||||||
|
install -m 0644 ${S}/iMX8QM/imx8qm_dcd.cfg.tmp ${DEPLOYDIR}
|
||||||
|
install -m 0644 ${S}/iMX8QX/imx8qx_dcd.cfg.tmp ${DEPLOYDIR}
|
||||||
|
}
|
||||||
|
|
||||||
|
addtask deploy before do_build after do_install
|
||||||
|
|
@ -0,0 +1,8 @@
|
||||||
|
# Copyright 2017-2018 NXP
|
||||||
|
|
||||||
|
IMX_MKIMAGE_SRC ?= "git://source.codeaurora.org/external/imx/imx-mkimage.git;protocol=https"
|
||||||
|
SRCBRANCH = "imx_4.9.88_imx8qxp_beta2"
|
||||||
|
SRC_URI = "${IMX_MKIMAGE_SRC};branch=${SRCBRANCH}"
|
||||||
|
SRCREV = "5c18f544c460747daed2844714c49685ed6ce897"
|
||||||
|
|
||||||
|
DEPENDS = "zlib-native openssl-native"
|
||||||
|
|
@ -0,0 +1,48 @@
|
||||||
|
# Copyright (C) 2016 Freescale Semiconductor
|
||||||
|
# Copyright 2017-2018 NXP
|
||||||
|
# Copyright (C) 2018 Digi International.
|
||||||
|
|
||||||
|
DESCRIPTION = "i.MX System Controller Firmware"
|
||||||
|
LICENSE = "MIT"
|
||||||
|
LIC_FILES_CHKSUM = "file://COPYING;md5=ab61cab9599935bfe9f700405ef00f28"
|
||||||
|
SECTION = "BSP"
|
||||||
|
|
||||||
|
inherit pkgconfig deploy
|
||||||
|
|
||||||
|
SRC_URI = "${DIGI_PKG_SRC}/${PN}-${PV}.tar.gz"
|
||||||
|
|
||||||
|
SRC_URI[md5sum] = "2b403986a9a0e47528baa3138015ce02"
|
||||||
|
SRC_URI[sha256sum] = "dbdffdd9b0d527218a1bf90aad2ef8dcee1b4c5170e5a983ae6f5e54b062cddc"
|
||||||
|
|
||||||
|
S = "${WORKDIR}/${PN}-${PV}"
|
||||||
|
|
||||||
|
SC_FIRMWARE_NAME ?= "mx8qx-${DIGI_FAMILY}-scfw-tcm.bin"
|
||||||
|
symlink_name = "scfw_tcm.bin"
|
||||||
|
|
||||||
|
SYSROOT_DIRS += "/boot"
|
||||||
|
|
||||||
|
do_install () {
|
||||||
|
install -d ${D}/boot
|
||||||
|
install -m 0644 ${S}/${SC_FIRMWARE_NAME} ${D}/boot/
|
||||||
|
}
|
||||||
|
|
||||||
|
BOOT_TOOLS = "imx-boot-tools"
|
||||||
|
|
||||||
|
do_deploy () {
|
||||||
|
install -d ${DEPLOYDIR}/${BOOT_TOOLS}
|
||||||
|
install -m 0644 ${S}/${SC_FIRMWARE_NAME} ${DEPLOYDIR}/${BOOT_TOOLS}/
|
||||||
|
cd ${DEPLOYDIR}/${BOOT_TOOLS}/
|
||||||
|
rm -f ${symlink_name}
|
||||||
|
ln -sf ${SC_FIRMWARE_NAME} ${symlink_name}
|
||||||
|
cd -
|
||||||
|
}
|
||||||
|
|
||||||
|
addtask deploy after do_install
|
||||||
|
|
||||||
|
INHIBIT_PACKAGE_STRIP = "1"
|
||||||
|
INHIBIT_PACKAGE_DEBUG_SPLIT = "1"
|
||||||
|
PACKAGE_ARCH = "${MACHINE_ARCH}"
|
||||||
|
|
||||||
|
FILES_${PN} = "/boot"
|
||||||
|
|
||||||
|
COMPATIBLE_MACHINE = "(ccimx8x)"
|
||||||
|
|
@ -0,0 +1,3 @@
|
||||||
|
PLATFORM_mx8 = "IMX8"
|
||||||
|
|
||||||
|
COMPATIBLE_MACHINE = "(mx6|mx8x)"
|
||||||
|
|
@ -13,7 +13,7 @@ else
|
||||||
#
|
#
|
||||||
if test "${module_variant}" = "0x02" || test "${module_variant}" = "0x04"; then
|
if test "${module_variant}" = "0x02" || test "${module_variant}" = "0x04"; then
|
||||||
setenv fdt_file zImage-imx6ul-ccimx6ulsbc-wb.dtb
|
setenv fdt_file zImage-imx6ul-ccimx6ulsbc-wb.dtb
|
||||||
elif test "${module_variant}" = "0x03"; then
|
elif test "${module_variant}" = "0x03" || test "${module_variant}" = "0x05"; then
|
||||||
setenv fdt_file zImage-imx6ul-ccimx6ulsbc.dtb
|
setenv fdt_file zImage-imx6ul-ccimx6ulsbc.dtb
|
||||||
else
|
else
|
||||||
echo "------ Using default fdt_file: $fdt_file"
|
echo "------ Using default fdt_file: $fdt_file"
|
||||||
|
|
@ -23,7 +23,7 @@ fi
|
||||||
if test -n "${module_variant}"; then
|
if test -n "${module_variant}"; then
|
||||||
if test "${module_variant}" = "0x02" || test "${module_variant}" = "0x03"; then
|
if test "${module_variant}" = "0x02" || test "${module_variant}" = "0x03"; then
|
||||||
setenv INSTALL_UBOOT_FILENAME u-boot-ccimx6ulsbc.imx;
|
setenv INSTALL_UBOOT_FILENAME u-boot-ccimx6ulsbc.imx;
|
||||||
elif test "${module_variant}" = "0x04"; then
|
elif test "${module_variant}" = "0x04" || test "${module_variant}" = "0x05"; then
|
||||||
setenv INSTALL_UBOOT_FILENAME u-boot-ccimx6ulsbc1GB.imx;
|
setenv INSTALL_UBOOT_FILENAME u-boot-ccimx6ulsbc1GB.imx;
|
||||||
fi
|
fi
|
||||||
fi
|
fi
|
||||||
|
|
@ -13,7 +13,7 @@ else
|
||||||
#
|
#
|
||||||
if test "${module_variant}" = "0x02" || test "${module_variant}" = "0x04"; then
|
if test "${module_variant}" = "0x02" || test "${module_variant}" = "0x04"; then
|
||||||
setenv fdt_file zImage-imx6ul-ccimx6ulstarter-wb.dtb
|
setenv fdt_file zImage-imx6ul-ccimx6ulstarter-wb.dtb
|
||||||
elif test "${module_variant}" = "0x03"; then
|
elif test "${module_variant}" = "0x03" || test "${module_variant}" = "0x05"; then
|
||||||
setenv fdt_file zImage-imx6ul-ccimx6ulstarter.dtb
|
setenv fdt_file zImage-imx6ul-ccimx6ulstarter.dtb
|
||||||
else
|
else
|
||||||
echo "------ Using default fdt_file: $fdt_file"
|
echo "------ Using default fdt_file: $fdt_file"
|
||||||
|
|
@ -23,7 +23,7 @@ fi
|
||||||
if test -n "${module_variant}"; then
|
if test -n "${module_variant}"; then
|
||||||
if test "${module_variant}" = "0x02" || test "${module_variant}" = "0x03"; then
|
if test "${module_variant}" = "0x02" || test "${module_variant}" = "0x03"; then
|
||||||
setenv INSTALL_UBOOT_FILENAME u-boot-ccimx6ulstarter.imx;
|
setenv INSTALL_UBOOT_FILENAME u-boot-ccimx6ulstarter.imx;
|
||||||
elif test "${module_variant}" = "0x04"; then
|
elif test "${module_variant}" = "0x04" || test "${module_variant}" = "0x05"; then
|
||||||
setenv INSTALL_UBOOT_FILENAME u-boot-ccimx6ulstarter1GB.imx;
|
setenv INSTALL_UBOOT_FILENAME u-boot-ccimx6ulstarter1GB.imx;
|
||||||
fi
|
fi
|
||||||
fi
|
fi
|
||||||
|
|
@ -0,0 +1,43 @@
|
||||||
|
#
|
||||||
|
# U-Boot bootscript for EMMC/SD images created by Yocto.
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# Set device tree filename depending on the board ID (if defined)
|
||||||
|
#
|
||||||
|
if test -n "${board_id}"; then
|
||||||
|
setenv fdt_file Image.gz-ccimx8x-sbc-express-id${board_id}.dtb
|
||||||
|
else
|
||||||
|
#
|
||||||
|
# Set device tree filename depending on the hardware variant
|
||||||
|
#
|
||||||
|
if test "${module_variant}" = "0x01"; then
|
||||||
|
setenv fdt_file Image.gz-ccimx8x-sbc-express-wb.dtb
|
||||||
|
elif test "${module_variant}" = "0x02"; then
|
||||||
|
setenv fdt_file Image.gz-ccimx8x-sbc-express-wb.dtb
|
||||||
|
elif test "${module_variant}" = "0x03"; then
|
||||||
|
setenv fdt_file Image.gz-ccimx8x-sbc-express.dtb
|
||||||
|
elif test "${module_variant}" = "0x04"; then
|
||||||
|
setenv fdt_file Image.gz-ccimx8x-sbc-express-wb.dtb
|
||||||
|
elif test "${module_variant}" = "0x05"; then
|
||||||
|
setenv fdt_file Image.gz-ccimx8x-sbc-express.dtb
|
||||||
|
else
|
||||||
|
echo "------ Using default fdt_file"
|
||||||
|
fi
|
||||||
|
fi
|
||||||
|
|
||||||
|
# Get the UUID of the configured boot partition.
|
||||||
|
part uuid mmc ${mmcbootdev}:${mmcpart} bootpart
|
||||||
|
# Check the boot source.
|
||||||
|
if test "${bootpart}" = "${part1_uuid}"; then
|
||||||
|
# We are booting from the eMMC using 'linux'.
|
||||||
|
true
|
||||||
|
elif test "${bootpart}" = "${part2_uuid}"; then
|
||||||
|
# We are booting from the eMMC using 'recovery'.
|
||||||
|
setenv boot_initrd true
|
||||||
|
setenv initrd_file uramdisk-recovery.img
|
||||||
|
else
|
||||||
|
# We are booting from the SD card.
|
||||||
|
setenv mmcroot /dev/mmcblk${mmcbootdev}p2
|
||||||
|
fi
|
||||||
|
dboot linux mmc ${mmcbootdev}:${mmcpart}
|
||||||
|
|
@ -0,0 +1,162 @@
|
||||||
|
#
|
||||||
|
# U-Boot script for installing Linux images created by Yocto from the SD
|
||||||
|
# card into the eMMC
|
||||||
|
#
|
||||||
|
|
||||||
|
echo "############################################################"
|
||||||
|
echo "# Linux firmware install from micro SD #"
|
||||||
|
echo "############################################################"
|
||||||
|
echo ""
|
||||||
|
echo " This process will erase your eMMC and will install a new"
|
||||||
|
echo " U-Boot and Linux firmware images on the eMMC."
|
||||||
|
echo ""
|
||||||
|
echo " Press CTRL+C now if you wish to abort or wait 10 seconds"
|
||||||
|
echo " to continue."
|
||||||
|
|
||||||
|
sleep 10
|
||||||
|
if test $? -eq 1; then
|
||||||
|
echo "Aborted by user.";
|
||||||
|
exit;
|
||||||
|
fi
|
||||||
|
|
||||||
|
# Determine U-Boot file to program basing on module variant
|
||||||
|
if test -n "${module_variant}"; then
|
||||||
|
if test "${module_variant}" = "0x01"; then
|
||||||
|
setenv INSTALL_UBOOT_FILENAME u-boot-ccimx8x-sbc-express.bin;
|
||||||
|
fi
|
||||||
|
fi
|
||||||
|
# Use 'test -n ...' because 'test -z ...' does not work well on old versions of
|
||||||
|
# u-boot when the checked value is empty.
|
||||||
|
if test -n "${INSTALL_UBOOT_FILENAME}"; then
|
||||||
|
true;
|
||||||
|
else
|
||||||
|
echo "";
|
||||||
|
echo "[ERROR] Cannot determine U-Boot file for this module!";
|
||||||
|
echo "";
|
||||||
|
echo "1. Set variable 'INSTALL_UBOOT_FILENAME' depending on your ConnectCore 8X variant:";
|
||||||
|
echo " - For a QuadXPlus CPU with 1GB DDR3, run:";
|
||||||
|
echo " => setenv INSTALL_UBOOT_FILENAME u-boot-ccimx8x-sbc-express.bin";
|
||||||
|
echo "";
|
||||||
|
echo "2. Run the install script again.";
|
||||||
|
echo "";
|
||||||
|
echo "Aborted";
|
||||||
|
echo "";
|
||||||
|
exit;
|
||||||
|
fi;
|
||||||
|
|
||||||
|
setenv INSTALL_MMCDEV 1
|
||||||
|
setenv INSTALL_LINUX_FILENAME dey-image-qt-##GRAPHICAL_BACKEND##-ccimx8x-sbc-express.boot.vfat
|
||||||
|
setenv INSTALL_RECOVERY_FILENAME dey-image-qt-##GRAPHICAL_BACKEND##-ccimx8x-sbc-express.recovery.vfat
|
||||||
|
setenv INSTALL_ROOTFS_FILENAME dey-image-qt-##GRAPHICAL_BACKEND##-ccimx8x-sbc-express.ext4
|
||||||
|
|
||||||
|
# Check for presence of firmware files on the SD card
|
||||||
|
for install_f in ${INSTALL_UBOOT_FILENAME} ${INSTALL_LINUX_FILENAME} ${INSTALL_RECOVERY_FILENAME} ${INSTALL_ROOTFS_FILENAME}; do
|
||||||
|
if test ! -e mmc ${INSTALL_MMCDEV} ${install_f}; then
|
||||||
|
echo "ERROR: Could not find file ${install_f}";
|
||||||
|
install_abort=1;
|
||||||
|
fi;
|
||||||
|
done
|
||||||
|
if test -n "${install_abort}"; then
|
||||||
|
echo "Aborted.";
|
||||||
|
exit;
|
||||||
|
fi
|
||||||
|
|
||||||
|
# Skip user confirmation for U-Boot update
|
||||||
|
setenv forced_update 1
|
||||||
|
|
||||||
|
# Set bootdelay to zero so that firmware update is run immediately after
|
||||||
|
# the first reset.
|
||||||
|
setenv bootdelay 0
|
||||||
|
|
||||||
|
# Set target MMC device index to eMMC
|
||||||
|
setenv mmcdev 0
|
||||||
|
|
||||||
|
# Update U-Boot
|
||||||
|
echo ""
|
||||||
|
echo ""
|
||||||
|
echo ">> Installing U-Boot boot loader (target will reset)"
|
||||||
|
echo ""
|
||||||
|
echo ""
|
||||||
|
update uboot mmc ${INSTALL_MMCDEV} fat ${INSTALL_UBOOT_FILENAME}
|
||||||
|
if test $? -eq 1; then
|
||||||
|
echo "[ERROR] Failed to update U-Boot boot loader!";
|
||||||
|
echo "";
|
||||||
|
echo "Aborted.";
|
||||||
|
exit;
|
||||||
|
fi
|
||||||
|
|
||||||
|
# Set 'bootcmd' to the second part of the script that will
|
||||||
|
# - Reset environment to defaults
|
||||||
|
# - Save the environment
|
||||||
|
# - Partition the eMMC user data area for Linux
|
||||||
|
# - Update the 'linux' partition
|
||||||
|
# - Update the 'recovery' partition
|
||||||
|
# - Update the 'rootfs' partition
|
||||||
|
# - Configure recovery to wipe 'update' partition
|
||||||
|
# - Run 'recovery' and let the system boot after
|
||||||
|
setenv bootcmd "
|
||||||
|
env default -a;
|
||||||
|
saveenv;
|
||||||
|
echo \"\";
|
||||||
|
echo \"\";
|
||||||
|
echo \">> Creating Linux partition table on the eMMC\";
|
||||||
|
echo \"\";
|
||||||
|
echo \"\";
|
||||||
|
run partition_mmc_linux;
|
||||||
|
if test \$? -eq 1; then
|
||||||
|
echo \"[ERROR] Failed to create Linux partition table!\";
|
||||||
|
echo \"\";
|
||||||
|
echo \"Aborted.\";
|
||||||
|
exit;
|
||||||
|
fi;
|
||||||
|
echo \"\";
|
||||||
|
echo \"\";
|
||||||
|
echo \">> Installing Linux kernel and device tree files\";
|
||||||
|
echo \"\";
|
||||||
|
echo \"\";
|
||||||
|
update linux mmc ${INSTALL_MMCDEV} fat ${INSTALL_LINUX_FILENAME};
|
||||||
|
if test \$? -eq 1; then
|
||||||
|
echo \"[ERROR] Failed to update linux partition!\";
|
||||||
|
echo \"\";
|
||||||
|
echo \"Aborted.\";
|
||||||
|
exit;
|
||||||
|
fi;
|
||||||
|
echo \"\";
|
||||||
|
echo \"\";
|
||||||
|
echo \">> Installing recovery\";
|
||||||
|
echo \"\";
|
||||||
|
echo \"\";
|
||||||
|
update recovery mmc ${INSTALL_MMCDEV} fat ${INSTALL_RECOVERY_FILENAME};
|
||||||
|
if test \$? -eq 1; then
|
||||||
|
echo \"[ERROR] Failed to update recovery partition!\";
|
||||||
|
echo \"\";
|
||||||
|
echo \"Aborted.\";
|
||||||
|
exit;
|
||||||
|
fi;
|
||||||
|
echo \"\";
|
||||||
|
echo \"\";
|
||||||
|
echo \">> Installing Linux root file system\";
|
||||||
|
echo \"\";
|
||||||
|
echo \"\";
|
||||||
|
update rootfs mmc ${INSTALL_MMCDEV} fat ${INSTALL_ROOTFS_FILENAME};
|
||||||
|
if test \$? -eq 1; then
|
||||||
|
echo \"[ERROR] Failed to update rootfs partition!\";
|
||||||
|
echo \"\";
|
||||||
|
echo \"Aborted.\";
|
||||||
|
exit;
|
||||||
|
fi;
|
||||||
|
echo \"\";
|
||||||
|
setenv boot_recovery yes;
|
||||||
|
setenv recovery_command wipe_update;
|
||||||
|
saveenv;
|
||||||
|
echo \"\";
|
||||||
|
echo \"\";
|
||||||
|
echo \">> Firmware installation complete. Rebooting into recovery mode for final deployment.\";
|
||||||
|
echo \"\";
|
||||||
|
echo \"\";
|
||||||
|
sleep 1;
|
||||||
|
reset;
|
||||||
|
"
|
||||||
|
|
||||||
|
saveenv
|
||||||
|
reset
|
||||||
|
|
@ -1,6 +1,6 @@
|
||||||
# Copyright (C) 2012-2018 Digi International
|
# Copyright (C) 2012-2018 Digi International
|
||||||
|
|
||||||
require u-boot.inc
|
require u-boot-2015.04.inc
|
||||||
|
|
||||||
DESCRIPTION = "Bootloader for Digi platforms"
|
DESCRIPTION = "Bootloader for Digi platforms"
|
||||||
LICENSE = "GPLv2+"
|
LICENSE = "GPLv2+"
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,172 @@
|
||||||
|
# Copyright (C) 2018 Digi International
|
||||||
|
|
||||||
|
require recipes-bsp/u-boot/u-boot.inc
|
||||||
|
|
||||||
|
DESCRIPTION = "Bootloader for Digi platforms"
|
||||||
|
LICENSE = "GPLv2+"
|
||||||
|
LIC_FILES_CHKSUM = "file://Licenses/README;md5=a2c678cfd4a4d97135585cad908541c6"
|
||||||
|
SECTION = "bootloaders"
|
||||||
|
|
||||||
|
DEPENDS += "bc-native dtc-native u-boot-mkimage-native"
|
||||||
|
DEPENDS += "${@base_conditional('TRUSTFENCE_SIGN', '1', 'trustfence-sign-tools-native', '', d)}"
|
||||||
|
|
||||||
|
PROVIDES += "u-boot"
|
||||||
|
|
||||||
|
SRCBRANCH = "v2017.03/master"
|
||||||
|
SRCREV = "${AUTOREV}"
|
||||||
|
|
||||||
|
S = "${WORKDIR}/git"
|
||||||
|
|
||||||
|
# Select internal or Github U-Boot repo
|
||||||
|
UBOOT_GIT_URI ?= "${@base_conditional('DIGI_INTERNAL_GIT', '1' , '${DIGI_GIT}u-boot-denx.git', '${DIGI_GITHUB_GIT}/u-boot.git', d)}"
|
||||||
|
|
||||||
|
SRC_URI = " \
|
||||||
|
${UBOOT_GIT_URI};branch=${SRCBRANCH} \
|
||||||
|
"
|
||||||
|
|
||||||
|
SRC_URI_append = " \
|
||||||
|
file://boot.txt \
|
||||||
|
file://install_linux_fw_sd.txt \
|
||||||
|
"
|
||||||
|
|
||||||
|
LOCALVERSION ?= ""
|
||||||
|
inherit fsl-u-boot-localversion
|
||||||
|
|
||||||
|
EXTRA_OEMAKE_append = " KCFLAGS=-fgnu89-inline"
|
||||||
|
|
||||||
|
UBOOT_EXTRA_CONF ?= ""
|
||||||
|
|
||||||
|
python __anonymous() {
|
||||||
|
if (d.getVar("TRUSTFENCE_DEK_PATH", True) not in ["0", None]) and (d.getVar("TRUSTFENCE_SIGN", True) != "1"):
|
||||||
|
bb.fatal("Only signed U-Boot images can be encrypted. Generate signed images (TRUSTFENCE_SIGN = \"1\") or remove encryption (TRUSTFENCE_DEK_PATH = \"0\")")
|
||||||
|
}
|
||||||
|
|
||||||
|
do_compile () {
|
||||||
|
if [ "${@bb.utils.filter('DISTRO_FEATURES', 'ld-is-gold', d)}" ]; then
|
||||||
|
sed -i 's/$(CROSS_COMPILE)ld$/$(CROSS_COMPILE)ld.bfd/g' ${S}/config.mk
|
||||||
|
fi
|
||||||
|
|
||||||
|
unset LDFLAGS
|
||||||
|
unset CFLAGS
|
||||||
|
unset CPPFLAGS
|
||||||
|
|
||||||
|
if [ ! -e ${B}/.scmversion -a ! -e ${S}/.scmversion ]
|
||||||
|
then
|
||||||
|
echo ${UBOOT_LOCALVERSION} > ${B}/.scmversion
|
||||||
|
echo ${UBOOT_LOCALVERSION} > ${S}/.scmversion
|
||||||
|
fi
|
||||||
|
|
||||||
|
if [ -n "${UBOOT_CONFIG}" ]
|
||||||
|
then
|
||||||
|
unset i j k
|
||||||
|
for config in ${UBOOT_MACHINE}; do
|
||||||
|
i=$(expr $i + 1);
|
||||||
|
for type in ${UBOOT_CONFIG}; do
|
||||||
|
j=$(expr $j + 1);
|
||||||
|
if [ $j -eq $i ]
|
||||||
|
then
|
||||||
|
oe_runmake -C ${S} O=${B}/${config} ${config}
|
||||||
|
|
||||||
|
# Reconfigure U-Boot with Digi UBOOT_EXTRA_CONF
|
||||||
|
for var in ${UBOOT_EXTRA_CONF}; do
|
||||||
|
echo "${var}" >> ${B}/${config}/.config
|
||||||
|
done
|
||||||
|
oe_runmake -C ${S} O=${B}/${config} oldconfig
|
||||||
|
|
||||||
|
oe_runmake -C ${S} O=${B}/${config} ${UBOOT_MAKE_TARGET}
|
||||||
|
for binary in ${UBOOT_BINARIES}; do
|
||||||
|
k=$(expr $k + 1);
|
||||||
|
if [ $k -eq $i ]; then
|
||||||
|
cp ${B}/${config}/${binary} ${B}/${config}/u-boot-${type}.${UBOOT_SUFFIX}
|
||||||
|
fi
|
||||||
|
done
|
||||||
|
unset k
|
||||||
|
|
||||||
|
# Secure boot artifacts
|
||||||
|
if [ "${TRUSTFENCE_SIGN}" = "1" ]
|
||||||
|
then
|
||||||
|
cp ${B}/${config}/u-boot-dtb-signed.imx ${B}/${config}/u-boot-dtb-signed-${type}.${UBOOT_SUFFIX}
|
||||||
|
cp ${B}/${config}/u-boot-dtb-usb-signed.imx ${B}/${config}/u-boot-dtb-usb-signed-${type}.${UBOOT_SUFFIX}
|
||||||
|
if [ "${TRUSTFENCE_DEK_PATH}" != "0" ]
|
||||||
|
then
|
||||||
|
cp ${B}/${config}/u-boot-dtb-encrypted.imx ${B}/${config}/u-boot-dtb-encrypted-${type}.${UBOOT_SUFFIX}
|
||||||
|
fi
|
||||||
|
fi
|
||||||
|
fi
|
||||||
|
done
|
||||||
|
unset j
|
||||||
|
done
|
||||||
|
unset i
|
||||||
|
else
|
||||||
|
oe_runmake -C ${S} O=${B} ${UBOOT_MACHINE}
|
||||||
|
oe_runmake -C ${S} O=${B} ${UBOOT_MAKE_TARGET}
|
||||||
|
fi
|
||||||
|
}
|
||||||
|
|
||||||
|
TF_BOOTSCRIPT_SEDFILTER = ""
|
||||||
|
TF_BOOTSCRIPT_SEDFILTER_ccimx6 = "${@tf_bootscript_sedfilter(d)}"
|
||||||
|
TF_BOOTSCRIPT_SEDFILTER_ccimx6ul = "${@tf_bootscript_sedfilter(d)}"
|
||||||
|
|
||||||
|
def tf_bootscript_sedfilter(d):
|
||||||
|
tf_initramfs = d.getVar('TRUSTFENCE_INITRAMFS_IMAGE',True) or ""
|
||||||
|
return "s,\(^[[:blank:]]*\)true.*,\\1setenv boot_initrd true\\n\\1setenv initrd_file %s-${MACHINE}.cpio.gz.u-boot.tf,g" % tf_initramfs if tf_initramfs else ""
|
||||||
|
|
||||||
|
do_deploy_append() {
|
||||||
|
# Remove canonical U-Boot symlinks for ${UBOOT_CONFIG} currently in the form:
|
||||||
|
# u-boot-<platform>.<ext>-<type>
|
||||||
|
# u-boot-<type>
|
||||||
|
# and add a more suitable symlink in the form:
|
||||||
|
# u-boot-<platform>-<config>.<ext>
|
||||||
|
if [ -n "${UBOOT_CONFIG}" ] && [ "${TRUSTFENCE_SIGN}" = "1" ]
|
||||||
|
then
|
||||||
|
for config in ${UBOOT_MACHINE}; do
|
||||||
|
i=$(expr $i + 1);
|
||||||
|
for type in ${UBOOT_CONFIG}; do
|
||||||
|
j=$(expr $j + 1);
|
||||||
|
if [ $j -eq $i ]
|
||||||
|
then
|
||||||
|
install ${B}/${config}/SRK_efuses.bin SRK_efuses-${PV}-${PR}.bin
|
||||||
|
ln -sf SRK_efuses-${PV}-${PR}.bin SRK_efuses.bin
|
||||||
|
|
||||||
|
install ${B}/${config}/u-boot-dtb-signed-${type}.${UBOOT_SUFFIX} u-boot-dtb-signed-${type}-${PV}-${PR}.${UBOOT_SUFFIX}
|
||||||
|
ln -sf u-boot-dtb-signed-${type}-${PV}-${PR}.${UBOOT_SUFFIX} u-boot-dtb-signed-${type}.${UBOOT_SUFFIX}
|
||||||
|
|
||||||
|
install ${B}/${config}/u-boot-dtb-usb-signed-${type}.${UBOOT_SUFFIX} u-boot-dtb-usb-signed-${type}-${PV}-${PR}.${UBOOT_SUFFIX}
|
||||||
|
ln -sf u-boot-dtb-usb-signed-${type}-${PV}-${PR}.${UBOOT_SUFFIX} u-boot-dtb-usb-signed-${type}.${UBOOT_SUFFIX}
|
||||||
|
|
||||||
|
if [ "${TRUSTFENCE_DEK_PATH}" != "0" ]
|
||||||
|
then
|
||||||
|
install ${B}/${config}/u-boot-dtb-encrypted-${type}.${UBOOT_SUFFIX} u-boot-dtb-encrypted-${type}-${PV}-${PR}.${UBOOT_SUFFIX}
|
||||||
|
ln -sf u-boot-dtb-encrypted-${type}-${PV}-${PR}.${UBOOT_SUFFIX} u-boot-dtb-encrypted-${type}.${UBOOT_SUFFIX}
|
||||||
|
fi
|
||||||
|
fi
|
||||||
|
done
|
||||||
|
unset j
|
||||||
|
done
|
||||||
|
unset i
|
||||||
|
fi
|
||||||
|
|
||||||
|
# DEY firmware install script
|
||||||
|
sed -i -e 's,##GRAPHICAL_BACKEND##,${GRAPHICAL_BACKEND},g' ${WORKDIR}/install_linux_fw_sd.txt
|
||||||
|
mkimage -T script -n "DEY firmware install script" -C none -d ${WORKDIR}/install_linux_fw_sd.txt ${DEPLOYDIR}/install_linux_fw_sd.scr
|
||||||
|
|
||||||
|
# Boot script for DEY images (reconfigure on-the-fly if TRUSTFENCE is enabled)
|
||||||
|
TMP_BOOTSCR="$(mktemp ${WORKDIR}/bootscr.XXXXXX)"
|
||||||
|
sed -e "${TF_BOOTSCRIPT_SEDFILTER}" ${WORKDIR}/boot.txt > ${TMP_BOOTSCR}
|
||||||
|
mkimage -T script -n bootscript -C none -d ${TMP_BOOTSCR} ${DEPLOYDIR}/boot.scr
|
||||||
|
|
||||||
|
# Sign the scripts
|
||||||
|
if [ "${TRUSTFENCE_SIGN}" = "1" ]; then
|
||||||
|
export CONFIG_SIGN_KEYS_PATH="${TRUSTFENCE_SIGN_KEYS_PATH}"
|
||||||
|
[ -n "${TRUSTFENCE_KEY_INDEX}" ] && export CONFIG_KEY_INDEX="${TRUSTFENCE_KEY_INDEX}"
|
||||||
|
[ -n "${TRUSTFENCE_DEK_PATH}" ] && [ "${TRUSTFENCE_DEK_PATH}" != "0" ] && export CONFIG_DEK_PATH="${TRUSTFENCE_DEK_PATH}"
|
||||||
|
|
||||||
|
# Sign boot script
|
||||||
|
TMP_SIGNED_BOOTSCR="$(mktemp ${WORKDIR}/bootscr-signed.XXXXXX)"
|
||||||
|
trustfence-sign-kernel.sh -p "${DIGI_FAMILY}" -b "${DEPLOYDIR}/boot.scr" "${TMP_SIGNED_BOOTSCR}"
|
||||||
|
mv "${TMP_SIGNED_BOOTSCR}" "${DEPLOYDIR}/boot.scr"
|
||||||
|
fi
|
||||||
|
rm -f ${TMP_BOOTSCR}
|
||||||
|
}
|
||||||
|
|
||||||
|
COMPATIBLE_MACHINE = "(ccimx6$|ccimx6ul|ccimx8x)"
|
||||||
|
|
@ -0,0 +1,7 @@
|
||||||
|
# Configuration file for fw_(printenv/setenv) utility.
|
||||||
|
# Up to two entries are valid, in this case the redundant
|
||||||
|
# environment sector is assumed present.
|
||||||
|
|
||||||
|
# Device name Offset Size
|
||||||
|
/dev/mmcblk0boot1 0x1C0000 0x4000
|
||||||
|
/dev/mmcblk0boot1 0x1E0000 0x4000
|
||||||
|
|
@ -87,4 +87,4 @@ pkg_postinst_${PN}() {
|
||||||
fi
|
fi
|
||||||
}
|
}
|
||||||
|
|
||||||
COMPATIBLE_MACHINE = "(ccimx6sbc|ccimx6qpsbc|ccimx6ul)"
|
COMPATIBLE_MACHINE = "(ccimx6$|ccimx6ul|ccimx8x)"
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,33 @@
|
||||||
|
# Copyright 2017-2018 NXP
|
||||||
|
# Released under the MIT license (see COPYING.MIT for the terms)
|
||||||
|
|
||||||
|
SUMMARY = "i.MX M4 core Demo images"
|
||||||
|
SECTION = "app"
|
||||||
|
LICENSE = "Proprietary"
|
||||||
|
LIC_FILES_CHKSUM = "file://COPYING;md5=ab61cab9599935bfe9f700405ef00f28"
|
||||||
|
|
||||||
|
inherit deploy fsl-eula-unpack2
|
||||||
|
|
||||||
|
SOC ?= "imx8qm"
|
||||||
|
SOC_mx7ulp= "imx7ulp"
|
||||||
|
SOC_mx8mq= "imx8mq"
|
||||||
|
SOC_mx8qm= "imx8qm"
|
||||||
|
SOC_mx8qxp= "imx8qx"
|
||||||
|
|
||||||
|
IMX_PACKAGE_NAME = "${SOC}-m4-demo-${PV}"
|
||||||
|
SRC_URI_NAME = "${SOC}"
|
||||||
|
|
||||||
|
SRC_URI[imx8qx.md5sum] = "e497c9742c0f20fbc429446c8052ade7"
|
||||||
|
SRC_URI[imx8qx.sha256sum] = "b46ac529c7c0fab9f99d39b094a9c4d6651616643f5df5ac2a4113bef02411fb"
|
||||||
|
|
||||||
|
SCR = "SCR-${SOC}-m4-demo.txt"
|
||||||
|
|
||||||
|
do_deploy () {
|
||||||
|
# Install the demo binaries
|
||||||
|
cp ${D}/* ${DEPLOYDIR}/
|
||||||
|
}
|
||||||
|
|
||||||
|
addtask deploy before do_build after do_install
|
||||||
|
|
||||||
|
PACKAGE_ARCH = "${MACHINE_ARCH}"
|
||||||
|
COMPATIBLE_MACHINE = "(mx8qxp)"
|
||||||
|
|
@ -23,10 +23,9 @@ S = "${WORKDIR}/git"
|
||||||
I2C_BUS = ""
|
I2C_BUS = ""
|
||||||
I2C_BUS_ccimx6qpsbc = "1"
|
I2C_BUS_ccimx6qpsbc = "1"
|
||||||
I2C_BUS_ccimx6ul = "0"
|
I2C_BUS_ccimx6ul = "0"
|
||||||
|
I2C_BUS_ccimx8x = "0"
|
||||||
|
|
||||||
I2C_SPEED = ""
|
I2C_SPEED ?= "100000"
|
||||||
I2C_SPEED_ccimx6qpsbc = "100000"
|
|
||||||
I2C_SPEED_ccimx6ul = "100000"
|
|
||||||
|
|
||||||
CFLAGS += "-DATCA_HAL_I2C_BUS=${I2C_BUS} -DATCA_HAL_I2C_SPEED=${I2C_SPEED}"
|
CFLAGS += "-DATCA_HAL_I2C_BUS=${I2C_BUS} -DATCA_HAL_I2C_SPEED=${I2C_SPEED}"
|
||||||
|
|
||||||
|
|
@ -41,4 +40,4 @@ do_install() {
|
||||||
}
|
}
|
||||||
|
|
||||||
PACKAGE_ARCH = "${MACHINE_ARCH}"
|
PACKAGE_ARCH = "${MACHINE_ARCH}"
|
||||||
COMPATIBLE_MACHINE = "(ccimx6qpsbc|ccimx6ul)"
|
COMPATIBLE_MACHINE = "(ccimx6qpsbc|ccimx6ul|ccimx8x)"
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,16 @@ SECTION = "console/tools"
|
||||||
LICENSE = "CLOSED"
|
LICENSE = "CLOSED"
|
||||||
|
|
||||||
PKGNAME = "mca_tool"
|
PKGNAME = "mca_tool"
|
||||||
SRC_URI = "${DIGI_PKG_SRC}/${PKGNAME}-${PV}.tar.gz"
|
|
||||||
|
|
||||||
SRC_URI[md5sum] = "bf9aff9f04118cceb2afe799ab940af2"
|
# ARM tarball
|
||||||
SRC_URI[sha256sum] = "e74682cb9b0f93b1e5f2e900c1a860df250bbf8733837506df3063124413d51a"
|
SRC_URI_arm = "${DIGI_PKG_SRC}/${PKGNAME}-${PV}-${TUNE_ARCH}.tar.gz;name=arm"
|
||||||
|
SRC_URI[arm.md5sum] = "bf9aff9f04118cceb2afe799ab940af2"
|
||||||
|
SRC_URI[arm.sha256sum] = "e74682cb9b0f93b1e5f2e900c1a860df250bbf8733837506df3063124413d51a"
|
||||||
|
|
||||||
|
# AARCH64 tarball
|
||||||
|
SRC_URI_aarch64 = "${DIGI_PKG_SRC}/${PKGNAME}-${PV}-${TUNE_ARCH}.tar.gz;name=aarch64"
|
||||||
|
SRC_URI[aarch64.md5sum] = "bf14a7a431353c37523149af24fb44d0"
|
||||||
|
SRC_URI[aarch64.sha256sum] = "8646837296b7d80de4ef3a5374d18aaf5a1d5b96345b6ce9e05ee982794ece24"
|
||||||
|
|
||||||
S = "${WORKDIR}/${PKGNAME}-${PV}"
|
S = "${WORKDIR}/${PKGNAME}-${PV}"
|
||||||
|
|
||||||
|
|
@ -16,4 +22,4 @@ inherit bin_package
|
||||||
|
|
||||||
INSANE_SKIP_${PN} = "already-stripped"
|
INSANE_SKIP_${PN} = "already-stripped"
|
||||||
|
|
||||||
COMPATIBLE_MACHINE = "(ccimx6ul)"
|
COMPATIBLE_MACHINE = "(ccimx6ul|ccimx8x)"
|
||||||
|
|
|
||||||
|
|
@ -5,7 +5,7 @@ LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/GPL-2.0;md5=801f80980d171dd6425
|
||||||
|
|
||||||
DEPENDS = "trustfence-cst coreutils util-linux"
|
DEPENDS = "trustfence-cst coreutils util-linux"
|
||||||
|
|
||||||
SRCBRANCH = "v2015.04/maint"
|
SRCBRANCH = "v2017.03/master"
|
||||||
SRCREV = "${AUTOREV}"
|
SRCREV = "${AUTOREV}"
|
||||||
|
|
||||||
S = "${WORKDIR}"
|
S = "${WORKDIR}"
|
||||||
|
|
@ -1,13 +1,16 @@
|
||||||
# Copyright (C) 2016,2017 Digi International.
|
# Copyright (C) 2016-2018 Digi International.
|
||||||
|
|
||||||
SUMMARY = "Qualcomm's wireless driver for qca6564"
|
SUMMARY = "Qualcomm's wireless driver for qca65xx"
|
||||||
DESCRIPTION = "qcacld-2.0 module"
|
DESCRIPTION = "qcacld-2.0 module"
|
||||||
LICENSE = "ISC"
|
LICENSE = "ISC"
|
||||||
LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/ISC;md5=f3b90e78ea0cffb20bf5cca7947a896d"
|
LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/ISC;md5=f3b90e78ea0cffb20bf5cca7947a896d"
|
||||||
|
|
||||||
|
# Reference Qualcomm tag/version
|
||||||
PV = "v4.2.80.63"
|
PV = "v4.2.80.63"
|
||||||
|
PV_ccimx8x = "v4.0.11.208Q"
|
||||||
|
|
||||||
SRCBRANCH = "dey-2.4/maint"
|
SRCBRANCH = "dey-2.4/maint"
|
||||||
|
SRCBRANCH_ccimx8x = "dey-2.4/maint_cc8x"
|
||||||
SRCREV = "${AUTOREV}"
|
SRCREV = "${AUTOREV}"
|
||||||
|
|
||||||
QCOM_GIT_URI = "${@base_conditional('DIGI_INTERNAL_GIT', '1' , '${DIGI_MTK_GIT}linux/qcacld-2.0.git;protocol=ssh', '${DIGI_GITHUB_GIT}/qcacld-2.0.git', d)}"
|
QCOM_GIT_URI = "${@base_conditional('DIGI_INTERNAL_GIT', '1' , '${DIGI_MTK_GIT}linux/qcacld-2.0.git;protocol=ssh', '${DIGI_GITHUB_GIT}/qcacld-2.0.git', d)}"
|
||||||
|
|
@ -16,37 +19,58 @@ SRC_URI = " \
|
||||||
${QCOM_GIT_URI};branch=${SRCBRANCH} \
|
${QCOM_GIT_URI};branch=${SRCBRANCH} \
|
||||||
"
|
"
|
||||||
|
|
||||||
|
# Selects whether the interface is SDIO or PCI
|
||||||
|
QUALCOMM_WIFI_INTERFACE ?= "sdio"
|
||||||
|
QUALCOMM_WIFI_INTERFACE_ccimx8x = "pci"
|
||||||
|
|
||||||
SRC_URI_append = " \
|
SRC_URI_append = " \
|
||||||
file://81-sdio-qcom.rules \
|
file://81-qcom-wifi.rules \
|
||||||
file://modprobe-qualcomm.conf \
|
|
||||||
file://qualcomm.sh \
|
file://qualcomm.sh \
|
||||||
"
|
"
|
||||||
|
|
||||||
|
FILES_SDIO = " \
|
||||||
|
file://modprobe-qualcomm.conf \
|
||||||
|
"
|
||||||
|
|
||||||
|
SRC_URI_append = "${@base_conditional('QUALCOMM_WIFI_INTERFACE', 'sdio' , '${FILES_SDIO}', '', d)}"
|
||||||
|
|
||||||
S = "${WORKDIR}/git"
|
S = "${WORKDIR}/git"
|
||||||
|
|
||||||
inherit module
|
inherit module
|
||||||
|
|
||||||
EXTRA_OEMAKE += "CONFIG_CLD_HL_SDIO_CORE=y CONFIG_LINUX_QCMBR=y WLAN_OPEN_SOURCE=1"
|
EXTRA_OEMAKE += "CONFIG_LINUX_QCMBR=y WLAN_OPEN_SOURCE=1"
|
||||||
# Explicity state it is not a QC platform, if not the driver will try to remap
|
# Explicity state it is not a QC platform, if not the driver will try to remap
|
||||||
# memory that is not allowed in ARMv6 (kernel commit
|
# memory that is not allowed in ARMv6 (kernel commit
|
||||||
# 309caa9cc6ff39d261264ec4ff10e29489afc8f8)
|
# 309caa9cc6ff39d261264ec4ff10e29489afc8f8)
|
||||||
EXTRA_OEMAKE += "CONFIG_NON_QC_PLATFORM=y"
|
EXTRA_OEMAKE += "CONFIG_NON_QC_PLATFORM=y"
|
||||||
# Flag to compile the debug version (1 - enabled, rest of values - disabled)
|
# Flag to compile the debug version (1 - enabled, rest of values - disabled)
|
||||||
EXTRA_OEMAKE += "BUILD_DEBUG_VERSION=0"
|
EXTRA_OEMAKE += "BUILD_DEBUG_VERSION=0"
|
||||||
|
# Flags for SDIO interface with wifi
|
||||||
|
FLAGS_SDIO = "CONFIG_CLD_HL_SDIO_CORE=y"
|
||||||
|
EXTRA_OEMAKE += "${@base_conditional('QUALCOMM_WIFI_INTERFACE', 'sdio' , '${FLAGS_SDIO}', '', d)}"
|
||||||
|
# Flags for PCI interface with wifi
|
||||||
|
FLAGS_PCI = "CONFIG_ROME_IF=pci CONFIG_HIF_PCI=1 CONFIG_ATH_PCIE_ACCESS_DEBUG=1 CONFIG_ATH_PCIE_MAX_PERF=1"
|
||||||
|
EXTRA_OEMAKE += "${@base_conditional('QUALCOMM_WIFI_INTERFACE', 'pci' , '${FLAGS_PCI}', '', d)}"
|
||||||
|
# Flags required for QCA6574
|
||||||
|
EXTRA_OEMAKE_append_ccimx8x = " CONFIG_ARCH_MSM=n CONFIG_ARCH_QCOM=n CONFIG_ATH_11AC_TXCOMPACT=1"
|
||||||
|
|
||||||
do_compile_prepend() {
|
do_compile_prepend() {
|
||||||
export BUILD_VER=${PV}
|
export BUILD_VER=${PV}
|
||||||
}
|
}
|
||||||
|
|
||||||
do_install_append() {
|
do_install_append() {
|
||||||
|
if [ "${QUALCOMM_WIFI_INTERFACE}" = "sdio" ]; then
|
||||||
install -d ${D}${sysconfdir}/modprobe.d
|
install -d ${D}${sysconfdir}/modprobe.d
|
||||||
install -m 0644 ${WORKDIR}/modprobe-qualcomm.conf ${D}${sysconfdir}/modprobe.d/qualcomm.conf
|
install -m 0644 ${WORKDIR}/modprobe-qualcomm.conf ${D}${sysconfdir}/modprobe.d/qualcomm.conf
|
||||||
|
fi
|
||||||
|
|
||||||
install -d ${D}${base_libdir}/firmware/wlan/
|
install -d ${D}${base_libdir}/firmware/wlan/
|
||||||
install -m 0644 ${WORKDIR}/git/firmware_bin/WCNSS_cfg.dat ${D}${base_libdir}/firmware/wlan/cfg.dat
|
install -m 0644 ${WORKDIR}/git/firmware_bin/WCNSS_cfg.dat ${D}${base_libdir}/firmware/wlan/cfg.dat
|
||||||
install -m 0644 ${WORKDIR}/git/firmware_bin/WCNSS_qcom_cfg.ini ${D}${base_libdir}/firmware/wlan/qcom_cfg.ini
|
install -m 0644 ${WORKDIR}/git/firmware_bin/WCNSS_qcom_cfg.ini ${D}${base_libdir}/firmware/wlan/qcom_cfg.ini
|
||||||
install -d ${D}${sysconfdir}/udev/rules.d ${D}${sysconfdir}/udev/scripts
|
install -d ${D}${sysconfdir}/udev/scripts
|
||||||
install -m 0644 ${WORKDIR}/81-sdio-qcom.rules ${D}${sysconfdir}/udev/rules.d/
|
|
||||||
install -m 0755 ${WORKDIR}/qualcomm.sh ${D}${sysconfdir}/udev/scripts/
|
install -m 0755 ${WORKDIR}/qualcomm.sh ${D}${sysconfdir}/udev/scripts/
|
||||||
|
install -d ${D}${sysconfdir}/udev/rules.d
|
||||||
|
install -m 0644 ${WORKDIR}/81-qcom-wifi.rules ${D}${sysconfdir}/udev/rules.d/
|
||||||
}
|
}
|
||||||
|
|
||||||
FILES_${PN} += " \
|
FILES_${PN} += " \
|
||||||
|
|
@ -56,4 +80,4 @@ FILES_${PN} += " \
|
||||||
${base_libdir}/firmware/wlan/qcom_cfg.ini \
|
${base_libdir}/firmware/wlan/qcom_cfg.ini \
|
||||||
"
|
"
|
||||||
|
|
||||||
COMPATIBLE_MACHINE = "(ccimx6qpsbc|ccimx6ul)"
|
COMPATIBLE_MACHINE = "(ccimx6qpsbc|ccimx6ul|ccimx8x)"
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,4 @@
|
||||||
|
# Load Qualcomm wireless module (sdio)
|
||||||
|
SUBSYSTEM=="sdio", ACTION=="add", ENV{MODALIAS}=="sdio:c00v0271d050A", RUN="/etc/udev/scripts/qualcomm.sh"
|
||||||
|
# Load Qualcomm wireless module (pci)
|
||||||
|
SUBSYSTEM=="pci", ACTION=="add", ENV{MODALIAS}=="pci:v0000168Cd0000003Esv*sd*bc*sc*i*", RUN="/etc/udev/scripts/qualcomm.sh"
|
||||||
|
|
@ -1,2 +0,0 @@
|
||||||
# Load Qualcomm wireless module
|
|
||||||
SUBSYSTEM=="sdio", ACTION=="add", ENV{MODALIAS}=="sdio:c00v0271d050A", RUN="/etc/udev/scripts/qualcomm.sh"
|
|
||||||
|
|
@ -1,71 +0,0 @@
|
||||||
From: Javier Viguera <javier.viguera@digi.com>
|
|
||||||
Date: Tue, 10 Nov 2015 17:45:37 +0100
|
|
||||||
Subject: [PATCH] mxc: gpu: use recommended values for minimum GPU frequency
|
|
||||||
divisor
|
|
||||||
|
|
||||||
Freescale recommends the following default minimum GPU frequency divisors
|
|
||||||
depending on the CPU family:
|
|
||||||
- 3 for Dual/Quad
|
|
||||||
- 8 for DualLite/Solo
|
|
||||||
|
|
||||||
Adapted for the external Vivante GPU driver from commit a790ad3 in linux
|
|
||||||
git repository.
|
|
||||||
|
|
||||||
Signed-off-by: Javier Viguera <javier.viguera@digi.com>
|
|
||||||
---
|
|
||||||
.../hal/os/linux/kernel/gc_hal_kernel_driver.c | 14 +++++++++++++-
|
|
||||||
.../platform/freescale/gc_hal_kernel_platform_imx6.c | 2 +-
|
|
||||||
2 files changed, 13 insertions(+), 2 deletions(-)
|
|
||||||
|
|
||||||
diff --git a/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/gc_hal_kernel_driver.c b/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/gc_hal_kernel_driver.c
|
|
||||||
index 816aae0..15a8753 100644
|
|
||||||
--- a/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/gc_hal_kernel_driver.c
|
|
||||||
+++ b/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/gc_hal_kernel_driver.c
|
|
||||||
@@ -54,6 +54,7 @@
|
|
||||||
|
|
||||||
|
|
||||||
#include <linux/device.h>
|
|
||||||
+#include <linux/of.h>
|
|
||||||
#include <linux/slab.h>
|
|
||||||
#include <linux/miscdevice.h>
|
|
||||||
|
|
||||||
@@ -199,7 +200,7 @@ static uint type = 0;
|
|
||||||
module_param(type, uint, 0664);
|
|
||||||
MODULE_PARM_DESC(type, "0 - Char Driver (Default), 1 - Misc Driver");
|
|
||||||
|
|
||||||
-static int gpu3DMinClock = 1;
|
|
||||||
+static int gpu3DMinClock = 0;
|
|
||||||
|
|
||||||
static int contiguousRequested = 0;
|
|
||||||
|
|
||||||
@@ -1138,6 +1139,17 @@ static int __devinit gpu_probe(struct platform_device *pdev)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
+ /* If undefined, set Freescale recommended value. Else use the min freq. */
|
|
||||||
+ if (gpu3DMinClock == 0) {
|
|
||||||
+ if (of_machine_is_compatible("fsl,imx6dl"))
|
|
||||||
+ gpu3DMinClock = 8;
|
|
||||||
+ else if (of_machine_is_compatible("fsl,imx6q") ||
|
|
||||||
+ of_machine_is_compatible("fsl,imx6qp"))
|
|
||||||
+ gpu3DMinClock = 3;
|
|
||||||
+ else
|
|
||||||
+ gpu3DMinClock = 1;
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
ret = drv_init();
|
|
||||||
if (!ret) {
|
|
||||||
platform_set_drvdata(pdev, galDevice);
|
|
||||||
diff --git a/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c b/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c
|
|
||||||
index 89706ec..65a54e2 100644
|
|
||||||
--- a/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c
|
|
||||||
+++ b/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c
|
|
||||||
@@ -123,7 +123,7 @@ extern int unregister_thermal_notifier(struct notifier_block *nb);
|
|
||||||
#define gcdFSL_CONTIGUOUS_SIZE (4 << 20)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
-static int initgpu3DMinClock = 1;
|
|
||||||
+static int initgpu3DMinClock = 0;
|
|
||||||
module_param(initgpu3DMinClock, int, 0644);
|
|
||||||
|
|
||||||
struct platform_device *pdevice;
|
|
||||||
|
|
@ -1,26 +0,0 @@
|
||||||
From: Hector Palacios <hector.palacios@digi.com>
|
|
||||||
Date: Tue, 1 Dec 2015 11:36:24 +0100
|
|
||||||
Subject: [PATCH] Use busfreq-imx6.h up to 3.15 kernel
|
|
||||||
|
|
||||||
For CC6 we're using Freescale 3.14.28 BSP. Even though we apply stability
|
|
||||||
patches that move the kernel version beyond 3.14.29 we still want to use
|
|
||||||
the GPU vivante external module build with the original BSP.
|
|
||||||
|
|
||||||
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
|
|
||||||
---
|
|
||||||
.../os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c | 2 +-
|
|
||||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
||||||
|
|
||||||
diff --git a/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c b/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c
|
|
||||||
index 0eae8262c2ce..f166680affa2 100644
|
|
||||||
--- a/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c
|
|
||||||
+++ b/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c
|
|
||||||
@@ -81,7 +81,7 @@
|
|
||||||
#include <linux/pm_runtime.h>
|
|
||||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
|
|
||||||
#include <mach/busfreq.h>
|
|
||||||
-#elif LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 29)
|
|
||||||
+#elif LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)
|
|
||||||
#include <linux/busfreq-imx6.h>
|
|
||||||
#include <linux/reset.h>
|
|
||||||
#else
|
|
||||||
|
|
@ -1,38 +0,0 @@
|
||||||
From: Mike Engel <Mike.Engel@digi.com>
|
|
||||||
Date: Tue, 11 Apr 2017 11:13:23 +0200
|
|
||||||
Subject: [PATCH] gpu: Get GPU reserved memory from DT.
|
|
||||||
|
|
||||||
This commit adds support to specify the GPU reserved memory in
|
|
||||||
the DT.
|
|
||||||
|
|
||||||
Signed-off-by: Mike Engel <Mike.Engel@digi.com>
|
|
||||||
|
|
||||||
https://jira.digi.com/browse/DEL-3868
|
|
||||||
---
|
|
||||||
.../linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c | 4 +---
|
|
||||||
1 file changed, 1 insertion(+), 3 deletions(-)
|
|
||||||
|
|
||||||
diff --git a/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c b/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c
|
|
||||||
index dc7c976..fd2dbd3 100644
|
|
||||||
--- a/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c
|
|
||||||
+++ b/kernel-module-imx-gpu-viv-src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c
|
|
||||||
@@ -568,7 +568,7 @@ gckPLATFORM_AdjustParam(
|
|
||||||
Args->registerMemSizeVG = res->end - res->start + 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)
|
|
||||||
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
|
|
||||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "contiguous_mem");
|
|
||||||
if (res)
|
|
||||||
{
|
|
||||||
@@ -577,8 +577,6 @@ gckPLATFORM_AdjustParam(
|
|
||||||
if( Args->contiguousSize == ~0U )
|
|
||||||
Args->contiguousSize = res->end - res->start + 1;
|
|
||||||
}
|
|
||||||
-#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
|
|
||||||
- Args->contiguousBase = 0;
|
|
||||||
#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
|
|
||||||
prop = of_get_property(dn, "contiguousbase", NULL);
|
|
||||||
if(prop)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,71 @@
|
||||||
|
From: Javier Viguera <javier.viguera@digi.com>
|
||||||
|
Date: Tue, 10 Nov 2015 17:45:37 +0100
|
||||||
|
Subject: [PATCH] mxc: gpu: use recommended values for minimum GPU frequency
|
||||||
|
divisor
|
||||||
|
|
||||||
|
Freescale recommends the following default minimum GPU frequency divisors
|
||||||
|
depending on the CPU family:
|
||||||
|
- 3 for Dual/Quad
|
||||||
|
- 8 for DualLite/Solo
|
||||||
|
|
||||||
|
Adapted for the external Vivante GPU driver from commit a790ad3 in linux
|
||||||
|
git repository.
|
||||||
|
|
||||||
|
Signed-off-by: Javier Viguera <javier.viguera@digi.com>
|
||||||
|
---
|
||||||
|
.../src/hal/os/linux/kernel/gc_hal_kernel_driver.c | 14 +++++++++++++-
|
||||||
|
.../src/platform/freescale/gc_hal_kernel_platform_imx6.c | 2 +-
|
||||||
|
2 files changed, 13 insertions(+), 2 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/src/hal/os/linux/kernel/gc_hal_kernel_driver.c b/src/hal/os/linux/kernel/gc_hal_kernel_driver.c
|
||||||
|
index 816aae0..15a8753 100644
|
||||||
|
--- a/src/hal/os/linux/kernel/gc_hal_kernel_driver.c
|
||||||
|
+++ b/src/hal/os/linux/kernel/gc_hal_kernel_driver.c
|
||||||
|
@@ -54,6 +54,7 @@
|
||||||
|
|
||||||
|
|
||||||
|
#include <linux/device.h>
|
||||||
|
+#include <linux/of.h>
|
||||||
|
#include <linux/slab.h>
|
||||||
|
#include <linux/miscdevice.h>
|
||||||
|
|
||||||
|
@@ -199,7 +200,7 @@ static uint type = 0;
|
||||||
|
module_param(type, uint, 0664);
|
||||||
|
MODULE_PARM_DESC(type, "0 - Char Driver (Default), 1 - Misc Driver");
|
||||||
|
|
||||||
|
-static int gpu3DMinClock = 1;
|
||||||
|
+static int gpu3DMinClock = 0;
|
||||||
|
|
||||||
|
static int contiguousRequested = 0;
|
||||||
|
|
||||||
|
@@ -959,6 +960,17 @@ static int __devinit gpu_probe(struct platform_device *pdev)
|
||||||
|
_UpdateModuleParam(&moduleParam);
|
||||||
|
}
|
||||||
|
|
||||||
|
+ /* If undefined, set Freescale recommended value. Else use the min freq. */
|
||||||
|
+ if (gpu3DMinClock == 0) {
|
||||||
|
+ if (of_machine_is_compatible("fsl,imx6dl"))
|
||||||
|
+ gpu3DMinClock = 8;
|
||||||
|
+ else if (of_machine_is_compatible("fsl,imx6q") ||
|
||||||
|
+ of_machine_is_compatible("fsl,imx6qp"))
|
||||||
|
+ gpu3DMinClock = 3;
|
||||||
|
+ else
|
||||||
|
+ gpu3DMinClock = 1;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
ret = drv_init();
|
||||||
|
|
||||||
|
if (!ret)
|
||||||
|
diff --git a/src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c b/src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c
|
||||||
|
index 89706ec..65a54e2 100644
|
||||||
|
--- a/src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c
|
||||||
|
+++ b/src/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6.c
|
||||||
|
@@ -123,7 +123,7 @@ extern int unregister_thermal_notifier(struct notifier_block *nb);
|
||||||
|
#define gcdFSL_CONTIGUOUS_SIZE (4 << 20)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
-static int initgpu3DMinClock = 1;
|
||||||
|
+static int initgpu3DMinClock = 0;
|
||||||
|
module_param(initgpu3DMinClock, int, 0644);
|
||||||
|
|
||||||
|
struct platform_device *pdevice;
|
||||||
|
|
@ -0,0 +1,326 @@
|
||||||
|
Index: git/Makefile
|
||||||
|
===================================================================
|
||||||
|
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
|
||||||
|
+++ git/Makefile 2017-06-27 12:07:11.931698672 -0500
|
||||||
|
@@ -0,0 +1,17 @@
|
||||||
|
+obj-m := galcore.o
|
||||||
|
+
|
||||||
|
+SRC := $(shell pwd)
|
||||||
|
+
|
||||||
|
+all:
|
||||||
|
+ $(MAKE) -C $(KERNEL_SRC) M=$(SRC)/src AQROOT=${PWD}/src
|
||||||
|
+ cp $(SRC)/src/Module.symvers $(PWD)
|
||||||
|
+ cp $(SRC)/src/modules.order $(PWD)
|
||||||
|
+
|
||||||
|
+modules_install:
|
||||||
|
+ $(MAKE) -C $(KERNEL_SRC) M=$(SRC)/src modules_install
|
||||||
|
+
|
||||||
|
+clean:
|
||||||
|
+ find . -name '*.o' -delete
|
||||||
|
+ rm -f *.o *~ core .depend .*.cmd *.ko *.mod.c
|
||||||
|
+ rm -f Module.markers Module.symvers modules.order
|
||||||
|
+ rm -rf .tmp_versions Modules.symvers
|
||||||
|
Index: git/src/hal/kernel/arch/makefile.linux
|
||||||
|
===================================================================
|
||||||
|
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
|
||||||
|
+++ git/src/hal/kernel/arch/makefile.linux 2017-06-27 11:44:06.004826232 -0500
|
||||||
|
@@ -0,0 +1,91 @@
|
||||||
|
+##############################################################################
|
||||||
|
+#
|
||||||
|
+# The MIT License (MIT)
|
||||||
|
+#
|
||||||
|
+# Copyright (c) 2014 - 2017 Vivante Corporation
|
||||||
|
+#
|
||||||
|
+# Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
+# copy of this software and associated documentation files (the "Software"),
|
||||||
|
+# to deal in the Software without restriction, including without limitation
|
||||||
|
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
+# and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
+# Software is furnished to do so, subject to the following conditions:
|
||||||
|
+#
|
||||||
|
+# The above copyright notice and this permission notice shall be included in
|
||||||
|
+# all copies or substantial portions of the Software.
|
||||||
|
+#
|
||||||
|
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||||
|
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||||
|
+# DEALINGS IN THE SOFTWARE.
|
||||||
|
+#
|
||||||
|
+##############################################################################
|
||||||
|
+#
|
||||||
|
+# The GPL License (GPL)
|
||||||
|
+#
|
||||||
|
+# Copyright (C) 2014 - 2017 Vivante Corporation
|
||||||
|
+#
|
||||||
|
+# This program is free software; you can redistribute it and/or
|
||||||
|
+# modify it under the terms of the GNU General Public License
|
||||||
|
+# as published by the Free Software Foundation; either version 2
|
||||||
|
+# of the License, or (at your option) any later version.
|
||||||
|
+#
|
||||||
|
+# This program is distributed in the hope that it will be useful,
|
||||||
|
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
+# GNU General Public License for more details.
|
||||||
|
+#
|
||||||
|
+# You should have received a copy of the GNU General Public License
|
||||||
|
+# along with this program; if not, write to the Free Software Foundation,
|
||||||
|
+# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||||
|
+#
|
||||||
|
+##############################################################################
|
||||||
|
+#
|
||||||
|
+# Note: This software is released under dual MIT and GPL licenses. A
|
||||||
|
+# recipient may use this file under the terms of either the MIT license or
|
||||||
|
+# GPL License. If you wish to use only one license not the other, you can
|
||||||
|
+# indicate your decision by deleting one of the above license notices in your
|
||||||
|
+# version of this file.
|
||||||
|
+#
|
||||||
|
+##############################################################################
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+#
|
||||||
|
+# Linux build file for architecture dependent kernel HAL layer.
|
||||||
|
+#
|
||||||
|
+
|
||||||
|
+################################################################################
|
||||||
|
+# Include common definitions.
|
||||||
|
+
|
||||||
|
+include $(AQROOT)/makefile.linux.def
|
||||||
|
+
|
||||||
|
+################################################################################
|
||||||
|
+# Define a shortcut for the main target.
|
||||||
|
+
|
||||||
|
+STATIC = 1
|
||||||
|
+TARGET_NAME = libhalarchkernel.a
|
||||||
|
+
|
||||||
|
+################################################################################
|
||||||
|
+# Supply additional include directories.
|
||||||
|
+
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/kernel/inc
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/kernel/inc
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/kernel
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/kernel/arch
|
||||||
|
+ifeq ($(VIVANTE_ENABLE_VG),1)
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/kernel/archvg
|
||||||
|
+endif
|
||||||
|
+
|
||||||
|
+CFLAGS += $(INCLUDE) -Werror -ansi
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+################################################################################
|
||||||
|
+# Describe object files.
|
||||||
|
+
|
||||||
|
+OBJECTS = $(OBJ_DIR)/gc_hal_kernel_context.o \
|
||||||
|
+ $(OBJ_DIR)/gc_hal_kernel_hardware.o
|
||||||
|
+
|
||||||
|
+include $(AQROOT)/common.target
|
||||||
|
Index: git/src/hal/kernel/archvg/makefile.linux
|
||||||
|
===================================================================
|
||||||
|
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
|
||||||
|
+++ git/src/hal/kernel/archvg/makefile.linux 2017-06-27 11:44:06.004826232 -0500
|
||||||
|
@@ -0,0 +1,91 @@
|
||||||
|
+##############################################################################
|
||||||
|
+#
|
||||||
|
+# The MIT License (MIT)
|
||||||
|
+#
|
||||||
|
+# Copyright (c) 2014 - 2017 Vivante Corporation
|
||||||
|
+#
|
||||||
|
+# Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
+# copy of this software and associated documentation files (the "Software"),
|
||||||
|
+# to deal in the Software without restriction, including without limitation
|
||||||
|
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
+# and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
+# Software is furnished to do so, subject to the following conditions:
|
||||||
|
+#
|
||||||
|
+# The above copyright notice and this permission notice shall be included in
|
||||||
|
+# all copies or substantial portions of the Software.
|
||||||
|
+#
|
||||||
|
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||||
|
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||||
|
+# DEALINGS IN THE SOFTWARE.
|
||||||
|
+#
|
||||||
|
+##############################################################################
|
||||||
|
+#
|
||||||
|
+# The GPL License (GPL)
|
||||||
|
+#
|
||||||
|
+# Copyright (C) 2014 - 2017 Vivante Corporation
|
||||||
|
+#
|
||||||
|
+# This program is free software; you can redistribute it and/or
|
||||||
|
+# modify it under the terms of the GNU General Public License
|
||||||
|
+# as published by the Free Software Foundation; either version 2
|
||||||
|
+# of the License, or (at your option) any later version.
|
||||||
|
+#
|
||||||
|
+# This program is distributed in the hope that it will be useful,
|
||||||
|
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
+# GNU General Public License for more details.
|
||||||
|
+#
|
||||||
|
+# You should have received a copy of the GNU General Public License
|
||||||
|
+# along with this program; if not, write to the Free Software Foundation,
|
||||||
|
+# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||||
|
+#
|
||||||
|
+##############################################################################
|
||||||
|
+#
|
||||||
|
+# Note: This software is released under dual MIT and GPL licenses. A
|
||||||
|
+# recipient may use this file under the terms of either the MIT license or
|
||||||
|
+# GPL License. If you wish to use only one license not the other, you can
|
||||||
|
+# indicate your decision by deleting one of the above license notices in your
|
||||||
|
+# version of this file.
|
||||||
|
+#
|
||||||
|
+##############################################################################
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+#
|
||||||
|
+# Linux build file for architecture dependent kernel HAL layer.
|
||||||
|
+#
|
||||||
|
+
|
||||||
|
+################################################################################
|
||||||
|
+# Include common definitions.
|
||||||
|
+
|
||||||
|
+include $(AQROOT)/makefile.linux.def
|
||||||
|
+
|
||||||
|
+################################################################################
|
||||||
|
+# Define a shortcut for the main target.
|
||||||
|
+
|
||||||
|
+STATIC = 1
|
||||||
|
+
|
||||||
|
+TARGET_NAME = libhalarchkernelvg.a
|
||||||
|
+
|
||||||
|
+################################################################################
|
||||||
|
+# Supply additional include directories.
|
||||||
|
+
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/inc
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/user
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/kernel
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/kernel/arch
|
||||||
|
+ifeq ($(VIVANTE_ENABLE_VG), 1)
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/kernel/archvg
|
||||||
|
+endif
|
||||||
|
+
|
||||||
|
+CFLAGS += $(INCLUDE) -Werror -ansi
|
||||||
|
+
|
||||||
|
+################################################################################
|
||||||
|
+# Describe object files.
|
||||||
|
+
|
||||||
|
+OBJECTS = $(OBJ_DIR)/gc_hal_kernel_hardware_vg.o \
|
||||||
|
+ $(OBJ_DIR)/gc_hal_kernel_hardware_command_vg.o
|
||||||
|
+
|
||||||
|
+include $(AQROOT)/common.target
|
||||||
|
Index: git/src/hal/kernel/makefile.linux
|
||||||
|
===================================================================
|
||||||
|
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
|
||||||
|
+++ git/src/hal/kernel/makefile.linux 2017-06-27 11:44:06.004826232 -0500
|
||||||
|
@@ -0,0 +1,107 @@
|
||||||
|
+##############################################################################
|
||||||
|
+#
|
||||||
|
+# The MIT License (MIT)
|
||||||
|
+#
|
||||||
|
+# Copyright (c) 2014 - 2017 Vivante Corporation
|
||||||
|
+#
|
||||||
|
+# Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
+# copy of this software and associated documentation files (the "Software"),
|
||||||
|
+# to deal in the Software without restriction, including without limitation
|
||||||
|
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
+# and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
+# Software is furnished to do so, subject to the following conditions:
|
||||||
|
+#
|
||||||
|
+# The above copyright notice and this permission notice shall be included in
|
||||||
|
+# all copies or substantial portions of the Software.
|
||||||
|
+#
|
||||||
|
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||||
|
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||||
|
+# DEALINGS IN THE SOFTWARE.
|
||||||
|
+#
|
||||||
|
+##############################################################################
|
||||||
|
+#
|
||||||
|
+# The GPL License (GPL)
|
||||||
|
+#
|
||||||
|
+# Copyright (C) 2014 - 2017 Vivante Corporation
|
||||||
|
+#
|
||||||
|
+# This program is free software; you can redistribute it and/or
|
||||||
|
+# modify it under the terms of the GNU General Public License
|
||||||
|
+# as published by the Free Software Foundation; either version 2
|
||||||
|
+# of the License, or (at your option) any later version.
|
||||||
|
+#
|
||||||
|
+# This program is distributed in the hope that it will be useful,
|
||||||
|
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
+# GNU General Public License for more details.
|
||||||
|
+#
|
||||||
|
+# You should have received a copy of the GNU General Public License
|
||||||
|
+# along with this program; if not, write to the Free Software Foundation,
|
||||||
|
+# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||||
|
+#
|
||||||
|
+##############################################################################
|
||||||
|
+#
|
||||||
|
+# Note: This software is released under dual MIT and GPL licenses. A
|
||||||
|
+# recipient may use this file under the terms of either the MIT license or
|
||||||
|
+# GPL License. If you wish to use only one license not the other, you can
|
||||||
|
+# indicate your decision by deleting one of the above license notices in your
|
||||||
|
+# version of this file.
|
||||||
|
+#
|
||||||
|
+##############################################################################
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+#
|
||||||
|
+# Linux build file for architecture dependent kernel HAL layer.
|
||||||
|
+#
|
||||||
|
+#
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+################################################################################
|
||||||
|
+# Include common definitions.
|
||||||
|
+
|
||||||
|
+include $(AQROOT)/makefile.linux.def
|
||||||
|
+
|
||||||
|
+################################################################################
|
||||||
|
+# Define a shortcut for the main target.
|
||||||
|
+
|
||||||
|
+STATIC = 1
|
||||||
|
+TARGET_NAME = libhalkernel.a
|
||||||
|
+
|
||||||
|
+################################################################################
|
||||||
|
+# Supply additional include directories.
|
||||||
|
+
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/kernel/inc
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/kernel/inc
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/kernel/arch
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/kernel
|
||||||
|
+ifeq ($(VIVANTE_ENABLE_VG),1)
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/kernel/archvg
|
||||||
|
+endif
|
||||||
|
+INCLUDE += -I$(AQROOT)/hal/os/linux/kernel
|
||||||
|
+CFLAGS += $(INCLUDE) -Werror -ansi
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+################################################################################
|
||||||
|
+# Describe object files.
|
||||||
|
+
|
||||||
|
+OBJECTS = $(OBJ_DIR)/gc_hal_kernel_command.o \
|
||||||
|
+ $(OBJ_DIR)/gc_hal_kernel_db.o \
|
||||||
|
+ $(OBJ_DIR)/gc_hal_kernel_debug.o \
|
||||||
|
+ $(OBJ_DIR)/gc_hal_kernel_event.o \
|
||||||
|
+ $(OBJ_DIR)/gc_hal_kernel_heap.o \
|
||||||
|
+ $(OBJ_DIR)/gc_hal_kernel.o \
|
||||||
|
+ $(OBJ_DIR)/gc_hal_kernel_mmu.o \
|
||||||
|
+ $(OBJ_DIR)/gc_hal_kernel_video_memory.o
|
||||||
|
+
|
||||||
|
+ifeq ($(VIVANTE_ENABLE_VG),1)
|
||||||
|
+OBJECTS += \
|
||||||
|
+ $(OBJ_DIR)/gc_hal_kernel_command_vg.o \
|
||||||
|
+ $(OBJ_DIR)/gc_hal_kernel_interrupt_vg.o \
|
||||||
|
+ $(OBJ_DIR)/gc_hal_kernel_mmu_vg.o \
|
||||||
|
+ $(OBJ_DIR)/gc_hal_kernel_vg.o
|
||||||
|
+endif
|
||||||
|
+
|
||||||
|
+include $(AQROOT)/common.target
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
# Copyright (C) 2017 Digi International
|
# Copyright (C) 2017-2018 Digi International
|
||||||
|
|
||||||
VER_DIR = "${@d.getVar('PV', True).split('+git')[0]}"
|
VER_DIR = "${@d.getVar('PV', True).split('+git')[0]}"
|
||||||
|
|
||||||
|
|
@ -6,6 +6,4 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/${BPN}-${VER_DIR}:"
|
||||||
|
|
||||||
SRC_URI += " \
|
SRC_URI += " \
|
||||||
file://0001-mxc-gpu-use-recommended-values-for-minimum-GPU-frequ.patch \
|
file://0001-mxc-gpu-use-recommended-values-for-minimum-GPU-frequ.patch \
|
||||||
file://0002-Use-busfreq-imx6.h-up-to-3.15-kernel.patch \
|
|
||||||
file://0003-gpu-Get-GPU-reserved-memory-from-DT.patch \
|
|
||||||
"
|
"
|
||||||
|
|
@ -1,18 +0,0 @@
|
||||||
# Copyright (C) 2017 Digi International
|
|
||||||
|
|
||||||
SUMMARY = "Kernel loadable module for Vivante GPU"
|
|
||||||
DESCRIPTION = "This package uses an exact copy of the GPU kernel driver source code of \
|
|
||||||
the same version as base and include fixes and improvements developed by FSL Community"
|
|
||||||
LICENSE = "GPLv2"
|
|
||||||
LIC_FILES_CHKSUM = "file://COPYING;md5=12f884d2ae1ff87c09e5b7ccc2c4ca7e"
|
|
||||||
|
|
||||||
PV .= "+git${SRCPV}"
|
|
||||||
|
|
||||||
SRCREV = "3b9e057f29853fd29364aa666328a92b807007d7"
|
|
||||||
SRC_URI = "git://github.com/Freescale/kernel-module-imx-gpu-viv.git;protocol=https"
|
|
||||||
|
|
||||||
S = "${WORKDIR}/git"
|
|
||||||
|
|
||||||
inherit module
|
|
||||||
|
|
||||||
KERNEL_MODULE_AUTOLOAD = "galcore"
|
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
# Copyright (C) 2017-2018 Digi International
|
||||||
|
|
||||||
|
SUMMARY = "Kernel loadable module for Vivante GPU"
|
||||||
|
DESCRIPTION = "Builds the Vivante GPU kernel driver as a loadable kernel module, \
|
||||||
|
allowing flexibility to use a newer graphics release with an older kernel."
|
||||||
|
|
||||||
|
inherit module
|
||||||
|
require recipes-kernel/linux/linux-dey-src.inc
|
||||||
|
|
||||||
|
PV .= "+git${SRCPV}"
|
||||||
|
|
||||||
|
SRC_URI .= \
|
||||||
|
";subpath=drivers/mxc/gpu-viv;destsuffix=git/src \
|
||||||
|
file://Add-makefile.patch \
|
||||||
|
"
|
||||||
|
|
||||||
|
LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6"
|
||||||
|
|
||||||
|
EXTRA_OEMAKE += "CONFIG_MXC_GPU_VIV=m"
|
||||||
|
|
||||||
|
KERNEL_MODULE_AUTOLOAD = "galcore"
|
||||||
|
|
@ -1,331 +0,0 @@
|
||||||
# CONFIG_LOCALVERSION_AUTO is not set
|
|
||||||
CONFIG_KERNEL_LZO=y
|
|
||||||
CONFIG_SYSVIPC=y
|
|
||||||
CONFIG_POSIX_MQUEUE=y
|
|
||||||
CONFIG_NO_HZ=y
|
|
||||||
CONFIG_HIGH_RES_TIMERS=y
|
|
||||||
CONFIG_IKCONFIG=y
|
|
||||||
CONFIG_IKCONFIG_PROC=y
|
|
||||||
CONFIG_LOG_BUF_SHIFT=18
|
|
||||||
CONFIG_CGROUPS=y
|
|
||||||
CONFIG_MEMCG=y
|
|
||||||
CONFIG_MEMCG_SWAP=y
|
|
||||||
CONFIG_BLK_CGROUP=y
|
|
||||||
CONFIG_CGROUP_SCHED=y
|
|
||||||
CONFIG_CFS_BANDWIDTH=y
|
|
||||||
CONFIG_RT_GROUP_SCHED=y
|
|
||||||
CONFIG_CGROUP_FREEZER=y
|
|
||||||
CONFIG_CPUSETS=y
|
|
||||||
CONFIG_CGROUP_DEVICE=y
|
|
||||||
CONFIG_CGROUP_CPUACCT=y
|
|
||||||
CONFIG_CGROUP_PERF=y
|
|
||||||
CONFIG_NAMESPACES=y
|
|
||||||
CONFIG_USER_NS=y
|
|
||||||
CONFIG_BLK_DEV_INITRD=y
|
|
||||||
CONFIG_EMBEDDED=y
|
|
||||||
CONFIG_PERF_EVENTS=y
|
|
||||||
# CONFIG_SLUB_DEBUG is not set
|
|
||||||
# CONFIG_COMPAT_BRK is not set
|
|
||||||
CONFIG_MODULES=y
|
|
||||||
CONFIG_MODULE_UNLOAD=y
|
|
||||||
CONFIG_MODVERSIONS=y
|
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
|
||||||
CONFIG_ARCH_MXC=y
|
|
||||||
CONFIG_SOC_IMX6Q=y
|
|
||||||
CONFIG_SOC_VF610=y
|
|
||||||
CONFIG_ARM_ERRATA_814220=y
|
|
||||||
CONFIG_PCI=y
|
|
||||||
CONFIG_PCI_MSI=y
|
|
||||||
CONFIG_PCI_IMX6=y
|
|
||||||
CONFIG_SMP=y
|
|
||||||
CONFIG_HAVE_ARM_ARCH_TIMER=y
|
|
||||||
CONFIG_VMSPLIT_2G=y
|
|
||||||
CONFIG_PREEMPT_VOLUNTARY=y
|
|
||||||
CONFIG_AEABI=y
|
|
||||||
CONFIG_HIGHMEM=y
|
|
||||||
CONFIG_CMA=y
|
|
||||||
CONFIG_SECCOMP=y
|
|
||||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
|
||||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
|
||||||
CONFIG_CPU_FREQ=y
|
|
||||||
CONFIG_CPU_FREQ_STAT=y
|
|
||||||
CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
|
|
||||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
|
||||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
|
||||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
|
||||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
|
||||||
CONFIG_ARM_IMX6Q_CPUFREQ=y
|
|
||||||
CONFIG_CPU_IDLE=y
|
|
||||||
CONFIG_VFP=y
|
|
||||||
CONFIG_NEON=y
|
|
||||||
CONFIG_PM_DEBUG=y
|
|
||||||
CONFIG_PM_TEST_SUSPEND=y
|
|
||||||
CONFIG_NET=y
|
|
||||||
CONFIG_PACKET=y
|
|
||||||
CONFIG_UNIX=y
|
|
||||||
CONFIG_INET=y
|
|
||||||
CONFIG_IP_PNP=y
|
|
||||||
CONFIG_IP_PNP_DHCP=y
|
|
||||||
CONFIG_SYN_COOKIES=y
|
|
||||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
|
||||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
|
||||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
|
||||||
CONFIG_NETFILTER=y
|
|
||||||
CONFIG_BRIDGE=y
|
|
||||||
CONFIG_NET_SCHED=y
|
|
||||||
CONFIG_CAN=y
|
|
||||||
CONFIG_CAN_FLEXCAN=y
|
|
||||||
CONFIG_BT=y
|
|
||||||
CONFIG_BT_RFCOMM=y
|
|
||||||
CONFIG_BT_RFCOMM_TTY=y
|
|
||||||
CONFIG_BT_BNEP=y
|
|
||||||
CONFIG_BT_BNEP_MC_FILTER=y
|
|
||||||
CONFIG_BT_BNEP_PROTO_FILTER=y
|
|
||||||
CONFIG_BT_HIDP=y
|
|
||||||
CONFIG_BT_HCIUART=y
|
|
||||||
CONFIG_BT_HCIUART_ATH3K=y
|
|
||||||
CONFIG_BT_HCIUART_3WIRE=y
|
|
||||||
CONFIG_BT_HCIUART_IBS=y
|
|
||||||
CONFIG_CFG80211=y
|
|
||||||
CONFIG_CFG80211_CERTIFICATION_ONUS=y
|
|
||||||
CONFIG_CFG80211_WEXT=y
|
|
||||||
CONFIG_RFKILL=y
|
|
||||||
CONFIG_RFKILL_INPUT=y
|
|
||||||
CONFIG_DEVTMPFS=y
|
|
||||||
CONFIG_DEVTMPFS_MOUNT=y
|
|
||||||
# CONFIG_STANDALONE is not set
|
|
||||||
CONFIG_DMA_CMA=y
|
|
||||||
CONFIG_CMA_SIZE_PERCENTAGE=40
|
|
||||||
CONFIG_CMA_SIZE_SEL_PERCENTAGE=y
|
|
||||||
CONFIG_IMX_WEIM=y
|
|
||||||
CONFIG_CONNECTOR=y
|
|
||||||
CONFIG_BLK_DEV_LOOP=y
|
|
||||||
CONFIG_BLK_DEV_RAM=y
|
|
||||||
CONFIG_BLK_DEV_RAM_SIZE=65536
|
|
||||||
CONFIG_EEPROM_AT24=y
|
|
||||||
CONFIG_EEPROM_AT25=y
|
|
||||||
# CONFIG_SCSI_PROC_FS is not set
|
|
||||||
CONFIG_BLK_DEV_SD=y
|
|
||||||
CONFIG_SCSI_CONSTANTS=y
|
|
||||||
CONFIG_SCSI_LOGGING=y
|
|
||||||
CONFIG_SCSI_SCAN_ASYNC=y
|
|
||||||
# CONFIG_SCSI_LOWLEVEL is not set
|
|
||||||
CONFIG_ATA=y
|
|
||||||
CONFIG_SATA_AHCI_PLATFORM=y
|
|
||||||
CONFIG_AHCI_IMX=y
|
|
||||||
CONFIG_PATA_IMX=y
|
|
||||||
CONFIG_MD=y
|
|
||||||
CONFIG_BLK_DEV_DM=y
|
|
||||||
CONFIG_DM_CRYPT=y
|
|
||||||
CONFIG_NETDEVICES=y
|
|
||||||
# CONFIG_NET_CADENCE is not set
|
|
||||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
|
||||||
# CONFIG_NET_VENDOR_CIRRUS is not set
|
|
||||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
|
||||||
# CONFIG_NET_VENDOR_INTEL is not set
|
|
||||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
|
||||||
# CONFIG_NET_VENDOR_MICREL is not set
|
|
||||||
# CONFIG_NET_VENDOR_MICROCHIP is not set
|
|
||||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
|
||||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
|
||||||
# CONFIG_NET_VENDOR_SMSC is not set
|
|
||||||
# CONFIG_NET_VENDOR_STMICRO is not set
|
|
||||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
|
||||||
CONFIG_MICREL_PHY=y
|
|
||||||
CONFIG_SMSC_PHY=y
|
|
||||||
CONFIG_PPP=y
|
|
||||||
CONFIG_PPP_BSDCOMP=y
|
|
||||||
CONFIG_PPP_DEFLATE=y
|
|
||||||
CONFIG_PPP_ASYNC=y
|
|
||||||
CONFIG_USB_USBNET=y
|
|
||||||
CONFIG_USB_NET_CDC_EEM=y
|
|
||||||
CONFIG_USB_NET_CDC_MBIM=y
|
|
||||||
CONFIG_USB_NET_QMI_WWAN=y
|
|
||||||
CONFIG_USB_SIERRA_NET=y
|
|
||||||
CONFIG_ATH6KL=m
|
|
||||||
CONFIG_ATH6KL_SDIO=m
|
|
||||||
CONFIG_ATH6KL_DEBUG=y
|
|
||||||
CONFIG_ATH6KL_REGDOMAIN=y
|
|
||||||
CONFIG_HOSTAP=y
|
|
||||||
CONFIG_HOSTAP_FIRMWARE=y
|
|
||||||
CONFIG_INPUT_EVDEV=y
|
|
||||||
CONFIG_KEYBOARD_GPIO=y
|
|
||||||
CONFIG_KEYBOARD_IMX=y
|
|
||||||
# CONFIG_INPUT_MOUSE is not set
|
|
||||||
CONFIG_INPUT_TOUCHSCREEN=y
|
|
||||||
CONFIG_TOUCHSCREEN_FUSION_7_10=y
|
|
||||||
CONFIG_TOUCHSCREEN_GOODIX=y
|
|
||||||
CONFIG_TOUCHSCREEN_MC13783=y
|
|
||||||
CONFIG_INPUT_MISC=y
|
|
||||||
CONFIG_INPUT_MMA8450=y
|
|
||||||
CONFIG_INPUT_DA9063_ONKEY=y
|
|
||||||
CONFIG_INPUT_ISL29023=y
|
|
||||||
# CONFIG_LEGACY_PTYS is not set
|
|
||||||
# CONFIG_DEVKMEM is not set
|
|
||||||
CONFIG_SERIAL_IMX=y
|
|
||||||
CONFIG_SERIAL_IMX_CONSOLE=y
|
|
||||||
CONFIG_SERIAL_FSL_LPUART=y
|
|
||||||
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
|
|
||||||
CONFIG_FSL_OTP=y
|
|
||||||
# CONFIG_I2C_COMPAT is not set
|
|
||||||
CONFIG_I2C_CHARDEV=y
|
|
||||||
# CONFIG_I2C_HELPER_AUTO is not set
|
|
||||||
CONFIG_I2C_IMX=y
|
|
||||||
CONFIG_I2C_IMX_LPI2C=y
|
|
||||||
CONFIG_SPI=y
|
|
||||||
CONFIG_SPI_IMX=y
|
|
||||||
CONFIG_SPI_FSL_LPSPI=y
|
|
||||||
CONFIG_SPI_SPIDEV=m
|
|
||||||
CONFIG_GPIO_SYSFS=y
|
|
||||||
CONFIG_GPIO_DA9063=y
|
|
||||||
CONFIG_POWER_SUPPLY=y
|
|
||||||
CONFIG_SENSORS_DA9063=y
|
|
||||||
CONFIG_SENSORS_MAG3110=y
|
|
||||||
CONFIG_THERMAL=y
|
|
||||||
CONFIG_THERMAL_WRITABLE_TRIPS=y
|
|
||||||
CONFIG_CPU_THERMAL=y
|
|
||||||
CONFIG_IMX_THERMAL=y
|
|
||||||
CONFIG_DEVICE_THERMAL=y
|
|
||||||
CONFIG_WATCHDOG=y
|
|
||||||
CONFIG_IMX2_WDT=y
|
|
||||||
CONFIG_MFD_DA9052_I2C=y
|
|
||||||
CONFIG_MFD_DA9063=y
|
|
||||||
CONFIG_MFD_MC13XXX_SPI=y
|
|
||||||
CONFIG_MFD_MC13XXX_I2C=y
|
|
||||||
CONFIG_REGULATOR=y
|
|
||||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
|
||||||
CONFIG_REGULATOR_ANATOP=y
|
|
||||||
CONFIG_REGULATOR_DA9052=y
|
|
||||||
CONFIG_REGULATOR_DA9063=y
|
|
||||||
CONFIG_REGULATOR_MC13783=y
|
|
||||||
CONFIG_REGULATOR_MC13892=y
|
|
||||||
CONFIG_REGULATOR_PFUZE100=y
|
|
||||||
CONFIG_MEDIA_SUPPORT=y
|
|
||||||
CONFIG_MEDIA_CAMERA_SUPPORT=y
|
|
||||||
CONFIG_MEDIA_USB_SUPPORT=y
|
|
||||||
CONFIG_USB_VIDEO_CLASS=y
|
|
||||||
# CONFIG_USB_GSPCA is not set
|
|
||||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
|
||||||
CONFIG_VIDEO_MXC_OUTPUT=y
|
|
||||||
CONFIG_VIDEO_MXC_CAPTURE=y
|
|
||||||
CONFIG_MXC_CAMERA_OV5642=y
|
|
||||||
CONFIG_MXC_CAMERA_OV5640_MIPI=y
|
|
||||||
CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=y
|
|
||||||
CONFIG_VIDEO_MXC_IPU_OUTPUT=y
|
|
||||||
CONFIG_VIDEO_MXC_PXP_V4L2=y
|
|
||||||
CONFIG_SOC_CAMERA=y
|
|
||||||
CONFIG_SOC_CAMERA_OV2640=y
|
|
||||||
# CONFIG_VGA_ARB is not set
|
|
||||||
CONFIG_DRM=y
|
|
||||||
CONFIG_DRM_VIVANTE=y
|
|
||||||
CONFIG_FB_MXS=y
|
|
||||||
CONFIG_FB_MXC_SYNC_PANEL=y
|
|
||||||
CONFIG_FB_MXC_OVERLAY=y
|
|
||||||
CONFIG_FB_MXC_MIPI_DSI=y
|
|
||||||
CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
|
|
||||||
CONFIG_FB_MXC_LDB=y
|
|
||||||
CONFIG_FB_MXC_HDMI=y
|
|
||||||
CONFIG_LCD_CLASS_DEVICE=y
|
|
||||||
CONFIG_LCD_L4F00242T03=y
|
|
||||||
CONFIG_LCD_PLATFORM=y
|
|
||||||
CONFIG_BACKLIGHT_PWM=y
|
|
||||||
CONFIG_BACKLIGHT_GPIO=y
|
|
||||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
|
||||||
CONFIG_LOGO=y
|
|
||||||
CONFIG_FB_LOGO_CENTERED=y
|
|
||||||
CONFIG_FB_LOGO_FORCE_SINGLE=y
|
|
||||||
# CONFIG_LOGO_LINUX_MONO is not set
|
|
||||||
# CONFIG_LOGO_LINUX_VGA16 is not set
|
|
||||||
# CONFIG_LOGO_LINUX_CLUT224 is not set
|
|
||||||
CONFIG_SOUND=y
|
|
||||||
CONFIG_SND=y
|
|
||||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
|
||||||
# CONFIG_SND_VERBOSE_PROCFS is not set
|
|
||||||
# CONFIG_SND_DRIVERS is not set
|
|
||||||
# CONFIG_SND_PCI is not set
|
|
||||||
# CONFIG_SND_ARM is not set
|
|
||||||
# CONFIG_SND_SPI is not set
|
|
||||||
# CONFIG_SND_USB is not set
|
|
||||||
CONFIG_SND_SOC=y
|
|
||||||
CONFIG_SND_IMX_SOC=y
|
|
||||||
CONFIG_SND_SOC_IMX_SGTL5000=y
|
|
||||||
CONFIG_SND_SOC_IMX_HDMI=y
|
|
||||||
CONFIG_HID_MULTITOUCH=y
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_USB_OTG=y
|
|
||||||
CONFIG_USB_EHCI_HCD=y
|
|
||||||
CONFIG_USB_ACM=y
|
|
||||||
CONFIG_USB_STORAGE=y
|
|
||||||
CONFIG_USB_CHIPIDEA=y
|
|
||||||
CONFIG_USB_CHIPIDEA_UDC=y
|
|
||||||
CONFIG_USB_CHIPIDEA_HOST=y
|
|
||||||
CONFIG_USB_SERIAL=y
|
|
||||||
CONFIG_USB_SERIAL_QUALCOMM=y
|
|
||||||
CONFIG_USB_SERIAL_SIERRAWIRELESS=y
|
|
||||||
CONFIG_USB_SERIAL_OPTION=y
|
|
||||||
CONFIG_USB_MXS_PHY=y
|
|
||||||
CONFIG_USB_GADGET=y
|
|
||||||
CONFIG_USB_ETH=m
|
|
||||||
CONFIG_USB_MASS_STORAGE=m
|
|
||||||
CONFIG_USB_G_SERIAL=m
|
|
||||||
CONFIG_USB_CDC_COMPOSITE=m
|
|
||||||
CONFIG_MMC=y
|
|
||||||
CONFIG_MMC_SDHCI=y
|
|
||||||
CONFIG_MMC_SDHCI_PLTFM=y
|
|
||||||
CONFIG_MMC_SDHCI_ESDHC_IMX=y
|
|
||||||
CONFIG_MXC_IPU=y
|
|
||||||
CONFIG_MXC_IPU_V3_PRE=y
|
|
||||||
CONFIG_MXC_MIPI_CSI2=y
|
|
||||||
CONFIG_NEW_LEDS=y
|
|
||||||
CONFIG_LEDS_CLASS=y
|
|
||||||
CONFIG_LEDS_DA9063=y
|
|
||||||
CONFIG_RTC_CLASS=y
|
|
||||||
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
|
|
||||||
CONFIG_RTC_DRV_DA9063=y
|
|
||||||
CONFIG_RTC_DRV_MC13XXX=y
|
|
||||||
CONFIG_RTC_DRV_MXC=y
|
|
||||||
CONFIG_RTC_DRV_SNVS=y
|
|
||||||
CONFIG_DMADEVICES=y
|
|
||||||
CONFIG_IMX_SDMA=y
|
|
||||||
CONFIG_MXS_DMA=y
|
|
||||||
CONFIG_MXC_PXP_V2=y
|
|
||||||
# CONFIG_IOMMU_SUPPORT is not set
|
|
||||||
CONFIG_EXTCON_USB_GPIO=y
|
|
||||||
CONFIG_PWM=y
|
|
||||||
CONFIG_PWM_IMX=y
|
|
||||||
CONFIG_EXT4_FS=y
|
|
||||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
|
||||||
CONFIG_EXT4_FS_SECURITY=y
|
|
||||||
CONFIG_OVERLAY_FS=y
|
|
||||||
CONFIG_MSDOS_FS=y
|
|
||||||
CONFIG_VFAT_FS=y
|
|
||||||
CONFIG_TMPFS=y
|
|
||||||
CONFIG_TMPFS_POSIX_ACL=y
|
|
||||||
# CONFIG_MISC_FILESYSTEMS is not set
|
|
||||||
CONFIG_NFS_FS=y
|
|
||||||
CONFIG_NFS_V3_ACL=y
|
|
||||||
CONFIG_NFS_V4=y
|
|
||||||
CONFIG_ROOT_NFS=y
|
|
||||||
CONFIG_NLS_DEFAULT="cp437"
|
|
||||||
CONFIG_NLS_CODEPAGE_437=y
|
|
||||||
CONFIG_NLS_CODEPAGE_850=y
|
|
||||||
CONFIG_NLS_ASCII=y
|
|
||||||
CONFIG_NLS_ISO8859_1=y
|
|
||||||
CONFIG_NLS_ISO8859_15=y
|
|
||||||
CONFIG_NLS_UTF8=y
|
|
||||||
CONFIG_DYNAMIC_DEBUG=y
|
|
||||||
CONFIG_DEBUG_FS=y
|
|
||||||
# CONFIG_SCHED_DEBUG is not set
|
|
||||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
|
||||||
# CONFIG_FTRACE is not set
|
|
||||||
# CONFIG_ARM_UNWIND is not set
|
|
||||||
CONFIG_SECURITYFS=y
|
|
||||||
CONFIG_CRYPTO_TEST=m
|
|
||||||
CONFIG_CRYPTO_XTS=y
|
|
||||||
CONFIG_CRYPTO_DEFLATE=y
|
|
||||||
CONFIG_CRYPTO_LZO=y
|
|
||||||
CONFIG_CRYPTO_USER_API_HASH=y
|
|
||||||
CONFIG_CRYPTO_USER_API_SKCIPHER=y
|
|
||||||
CONFIG_CRYPTO_DEV_FSL_CAAM=y
|
|
||||||
CONFIG_FONTS=y
|
|
||||||
CONFIG_VIRTUALIZATION=y
|
|
||||||
|
|
@ -1,331 +0,0 @@
|
||||||
# CONFIG_LOCALVERSION_AUTO is not set
|
|
||||||
CONFIG_KERNEL_LZO=y
|
|
||||||
CONFIG_SYSVIPC=y
|
|
||||||
CONFIG_POSIX_MQUEUE=y
|
|
||||||
CONFIG_NO_HZ=y
|
|
||||||
CONFIG_HIGH_RES_TIMERS=y
|
|
||||||
CONFIG_IKCONFIG=y
|
|
||||||
CONFIG_IKCONFIG_PROC=y
|
|
||||||
CONFIG_LOG_BUF_SHIFT=18
|
|
||||||
CONFIG_CGROUPS=y
|
|
||||||
CONFIG_MEMCG=y
|
|
||||||
CONFIG_MEMCG_SWAP=y
|
|
||||||
CONFIG_BLK_CGROUP=y
|
|
||||||
CONFIG_CGROUP_SCHED=y
|
|
||||||
CONFIG_CFS_BANDWIDTH=y
|
|
||||||
CONFIG_RT_GROUP_SCHED=y
|
|
||||||
CONFIG_CGROUP_FREEZER=y
|
|
||||||
CONFIG_CPUSETS=y
|
|
||||||
CONFIG_CGROUP_DEVICE=y
|
|
||||||
CONFIG_CGROUP_CPUACCT=y
|
|
||||||
CONFIG_CGROUP_PERF=y
|
|
||||||
CONFIG_NAMESPACES=y
|
|
||||||
CONFIG_USER_NS=y
|
|
||||||
CONFIG_BLK_DEV_INITRD=y
|
|
||||||
CONFIG_EMBEDDED=y
|
|
||||||
CONFIG_PERF_EVENTS=y
|
|
||||||
# CONFIG_SLUB_DEBUG is not set
|
|
||||||
# CONFIG_COMPAT_BRK is not set
|
|
||||||
CONFIG_MODULES=y
|
|
||||||
CONFIG_MODULE_UNLOAD=y
|
|
||||||
CONFIG_MODVERSIONS=y
|
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
|
||||||
CONFIG_ARCH_MXC=y
|
|
||||||
CONFIG_SOC_IMX6Q=y
|
|
||||||
CONFIG_SOC_VF610=y
|
|
||||||
CONFIG_ARM_ERRATA_814220=y
|
|
||||||
CONFIG_PCI=y
|
|
||||||
CONFIG_PCI_MSI=y
|
|
||||||
CONFIG_PCI_IMX6=y
|
|
||||||
CONFIG_SMP=y
|
|
||||||
CONFIG_HAVE_ARM_ARCH_TIMER=y
|
|
||||||
CONFIG_VMSPLIT_2G=y
|
|
||||||
CONFIG_PREEMPT_VOLUNTARY=y
|
|
||||||
CONFIG_AEABI=y
|
|
||||||
CONFIG_HIGHMEM=y
|
|
||||||
CONFIG_CMA=y
|
|
||||||
CONFIG_SECCOMP=y
|
|
||||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
|
||||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
|
||||||
CONFIG_CPU_FREQ=y
|
|
||||||
CONFIG_CPU_FREQ_STAT=y
|
|
||||||
CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
|
|
||||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
|
||||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
|
||||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
|
||||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
|
||||||
CONFIG_ARM_IMX6Q_CPUFREQ=y
|
|
||||||
CONFIG_CPU_IDLE=y
|
|
||||||
CONFIG_VFP=y
|
|
||||||
CONFIG_NEON=y
|
|
||||||
CONFIG_PM_DEBUG=y
|
|
||||||
CONFIG_PM_TEST_SUSPEND=y
|
|
||||||
CONFIG_NET=y
|
|
||||||
CONFIG_PACKET=y
|
|
||||||
CONFIG_UNIX=y
|
|
||||||
CONFIG_INET=y
|
|
||||||
CONFIG_IP_PNP=y
|
|
||||||
CONFIG_IP_PNP_DHCP=y
|
|
||||||
CONFIG_SYN_COOKIES=y
|
|
||||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
|
||||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
|
||||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
|
||||||
CONFIG_NETFILTER=y
|
|
||||||
CONFIG_BRIDGE=y
|
|
||||||
CONFIG_NET_SCHED=y
|
|
||||||
CONFIG_CAN=y
|
|
||||||
CONFIG_CAN_FLEXCAN=y
|
|
||||||
CONFIG_BT=y
|
|
||||||
CONFIG_BT_RFCOMM=y
|
|
||||||
CONFIG_BT_RFCOMM_TTY=y
|
|
||||||
CONFIG_BT_BNEP=y
|
|
||||||
CONFIG_BT_BNEP_MC_FILTER=y
|
|
||||||
CONFIG_BT_BNEP_PROTO_FILTER=y
|
|
||||||
CONFIG_BT_HIDP=y
|
|
||||||
CONFIG_BT_HCIUART=y
|
|
||||||
CONFIG_BT_HCIUART_ATH3K=y
|
|
||||||
CONFIG_BT_HCIUART_3WIRE=y
|
|
||||||
CONFIG_BT_HCIUART_IBS=y
|
|
||||||
CONFIG_CFG80211=y
|
|
||||||
CONFIG_CFG80211_CERTIFICATION_ONUS=y
|
|
||||||
CONFIG_CFG80211_WEXT=y
|
|
||||||
CONFIG_RFKILL=y
|
|
||||||
CONFIG_RFKILL_INPUT=y
|
|
||||||
CONFIG_DEVTMPFS=y
|
|
||||||
CONFIG_DEVTMPFS_MOUNT=y
|
|
||||||
# CONFIG_STANDALONE is not set
|
|
||||||
CONFIG_DMA_CMA=y
|
|
||||||
CONFIG_CMA_SIZE_PERCENTAGE=40
|
|
||||||
CONFIG_CMA_SIZE_SEL_PERCENTAGE=y
|
|
||||||
CONFIG_IMX_WEIM=y
|
|
||||||
CONFIG_CONNECTOR=y
|
|
||||||
CONFIG_BLK_DEV_LOOP=y
|
|
||||||
CONFIG_BLK_DEV_RAM=y
|
|
||||||
CONFIG_BLK_DEV_RAM_SIZE=65536
|
|
||||||
CONFIG_EEPROM_AT24=y
|
|
||||||
CONFIG_EEPROM_AT25=y
|
|
||||||
# CONFIG_SCSI_PROC_FS is not set
|
|
||||||
CONFIG_BLK_DEV_SD=y
|
|
||||||
CONFIG_SCSI_CONSTANTS=y
|
|
||||||
CONFIG_SCSI_LOGGING=y
|
|
||||||
CONFIG_SCSI_SCAN_ASYNC=y
|
|
||||||
# CONFIG_SCSI_LOWLEVEL is not set
|
|
||||||
CONFIG_ATA=y
|
|
||||||
CONFIG_SATA_AHCI_PLATFORM=y
|
|
||||||
CONFIG_AHCI_IMX=y
|
|
||||||
CONFIG_PATA_IMX=y
|
|
||||||
CONFIG_MD=y
|
|
||||||
CONFIG_BLK_DEV_DM=y
|
|
||||||
CONFIG_DM_CRYPT=y
|
|
||||||
CONFIG_NETDEVICES=y
|
|
||||||
# CONFIG_NET_CADENCE is not set
|
|
||||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
|
||||||
# CONFIG_NET_VENDOR_CIRRUS is not set
|
|
||||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
|
||||||
# CONFIG_NET_VENDOR_INTEL is not set
|
|
||||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
|
||||||
# CONFIG_NET_VENDOR_MICREL is not set
|
|
||||||
# CONFIG_NET_VENDOR_MICROCHIP is not set
|
|
||||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
|
||||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
|
||||||
# CONFIG_NET_VENDOR_SMSC is not set
|
|
||||||
# CONFIG_NET_VENDOR_STMICRO is not set
|
|
||||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
|
||||||
CONFIG_MICREL_PHY=y
|
|
||||||
CONFIG_SMSC_PHY=y
|
|
||||||
CONFIG_PPP=y
|
|
||||||
CONFIG_PPP_BSDCOMP=y
|
|
||||||
CONFIG_PPP_DEFLATE=y
|
|
||||||
CONFIG_PPP_ASYNC=y
|
|
||||||
CONFIG_USB_USBNET=y
|
|
||||||
CONFIG_USB_NET_CDC_EEM=y
|
|
||||||
CONFIG_USB_NET_CDC_MBIM=y
|
|
||||||
CONFIG_USB_NET_QMI_WWAN=y
|
|
||||||
CONFIG_USB_SIERRA_NET=y
|
|
||||||
CONFIG_ATH6KL=m
|
|
||||||
CONFIG_ATH6KL_SDIO=m
|
|
||||||
CONFIG_ATH6KL_DEBUG=y
|
|
||||||
CONFIG_ATH6KL_REGDOMAIN=y
|
|
||||||
CONFIG_HOSTAP=y
|
|
||||||
CONFIG_HOSTAP_FIRMWARE=y
|
|
||||||
CONFIG_INPUT_EVDEV=y
|
|
||||||
CONFIG_KEYBOARD_GPIO=y
|
|
||||||
CONFIG_KEYBOARD_IMX=y
|
|
||||||
# CONFIG_INPUT_MOUSE is not set
|
|
||||||
CONFIG_INPUT_TOUCHSCREEN=y
|
|
||||||
CONFIG_TOUCHSCREEN_FUSION_7_10=y
|
|
||||||
CONFIG_TOUCHSCREEN_GOODIX=y
|
|
||||||
CONFIG_TOUCHSCREEN_MC13783=y
|
|
||||||
CONFIG_INPUT_MISC=y
|
|
||||||
CONFIG_INPUT_MMA8450=y
|
|
||||||
CONFIG_INPUT_DA9063_ONKEY=y
|
|
||||||
CONFIG_INPUT_ISL29023=y
|
|
||||||
# CONFIG_LEGACY_PTYS is not set
|
|
||||||
# CONFIG_DEVKMEM is not set
|
|
||||||
CONFIG_SERIAL_IMX=y
|
|
||||||
CONFIG_SERIAL_IMX_CONSOLE=y
|
|
||||||
CONFIG_SERIAL_FSL_LPUART=y
|
|
||||||
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
|
|
||||||
CONFIG_FSL_OTP=y
|
|
||||||
# CONFIG_I2C_COMPAT is not set
|
|
||||||
CONFIG_I2C_CHARDEV=y
|
|
||||||
# CONFIG_I2C_HELPER_AUTO is not set
|
|
||||||
CONFIG_I2C_IMX=y
|
|
||||||
CONFIG_I2C_IMX_LPI2C=y
|
|
||||||
CONFIG_SPI=y
|
|
||||||
CONFIG_SPI_IMX=y
|
|
||||||
CONFIG_SPI_FSL_LPSPI=y
|
|
||||||
CONFIG_SPI_SPIDEV=m
|
|
||||||
CONFIG_GPIO_SYSFS=y
|
|
||||||
CONFIG_GPIO_DA9063=y
|
|
||||||
CONFIG_POWER_SUPPLY=y
|
|
||||||
CONFIG_SENSORS_DA9063=y
|
|
||||||
CONFIG_SENSORS_MAG3110=y
|
|
||||||
CONFIG_THERMAL=y
|
|
||||||
CONFIG_THERMAL_WRITABLE_TRIPS=y
|
|
||||||
CONFIG_CPU_THERMAL=y
|
|
||||||
CONFIG_IMX_THERMAL=y
|
|
||||||
CONFIG_DEVICE_THERMAL=y
|
|
||||||
CONFIG_WATCHDOG=y
|
|
||||||
CONFIG_IMX2_WDT=y
|
|
||||||
CONFIG_MFD_DA9052_I2C=y
|
|
||||||
CONFIG_MFD_DA9063=y
|
|
||||||
CONFIG_MFD_MC13XXX_SPI=y
|
|
||||||
CONFIG_MFD_MC13XXX_I2C=y
|
|
||||||
CONFIG_REGULATOR=y
|
|
||||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
|
||||||
CONFIG_REGULATOR_ANATOP=y
|
|
||||||
CONFIG_REGULATOR_DA9052=y
|
|
||||||
CONFIG_REGULATOR_DA9063=y
|
|
||||||
CONFIG_REGULATOR_MC13783=y
|
|
||||||
CONFIG_REGULATOR_MC13892=y
|
|
||||||
CONFIG_REGULATOR_PFUZE100=y
|
|
||||||
CONFIG_MEDIA_SUPPORT=y
|
|
||||||
CONFIG_MEDIA_CAMERA_SUPPORT=y
|
|
||||||
CONFIG_MEDIA_USB_SUPPORT=y
|
|
||||||
CONFIG_USB_VIDEO_CLASS=y
|
|
||||||
# CONFIG_USB_GSPCA is not set
|
|
||||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
|
||||||
CONFIG_VIDEO_MXC_OUTPUT=y
|
|
||||||
CONFIG_VIDEO_MXC_CAPTURE=y
|
|
||||||
CONFIG_MXC_CAMERA_OV5642=y
|
|
||||||
CONFIG_MXC_CAMERA_OV5640_MIPI=y
|
|
||||||
CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=y
|
|
||||||
CONFIG_VIDEO_MXC_IPU_OUTPUT=y
|
|
||||||
CONFIG_VIDEO_MXC_PXP_V4L2=y
|
|
||||||
CONFIG_SOC_CAMERA=y
|
|
||||||
CONFIG_SOC_CAMERA_OV2640=y
|
|
||||||
# CONFIG_VGA_ARB is not set
|
|
||||||
CONFIG_DRM=y
|
|
||||||
CONFIG_DRM_VIVANTE=y
|
|
||||||
CONFIG_FB_MXS=y
|
|
||||||
CONFIG_FB_MXC_SYNC_PANEL=y
|
|
||||||
CONFIG_FB_MXC_OVERLAY=y
|
|
||||||
CONFIG_FB_MXC_MIPI_DSI=y
|
|
||||||
CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
|
|
||||||
CONFIG_FB_MXC_LDB=y
|
|
||||||
CONFIG_FB_MXC_HDMI=y
|
|
||||||
CONFIG_LCD_CLASS_DEVICE=y
|
|
||||||
CONFIG_LCD_L4F00242T03=y
|
|
||||||
CONFIG_LCD_PLATFORM=y
|
|
||||||
CONFIG_BACKLIGHT_PWM=y
|
|
||||||
CONFIG_BACKLIGHT_GPIO=y
|
|
||||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
|
||||||
CONFIG_LOGO=y
|
|
||||||
CONFIG_FB_LOGO_CENTERED=y
|
|
||||||
CONFIG_FB_LOGO_FORCE_SINGLE=y
|
|
||||||
# CONFIG_LOGO_LINUX_MONO is not set
|
|
||||||
# CONFIG_LOGO_LINUX_VGA16 is not set
|
|
||||||
# CONFIG_LOGO_LINUX_CLUT224 is not set
|
|
||||||
CONFIG_SOUND=y
|
|
||||||
CONFIG_SND=y
|
|
||||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
|
||||||
# CONFIG_SND_VERBOSE_PROCFS is not set
|
|
||||||
# CONFIG_SND_DRIVERS is not set
|
|
||||||
# CONFIG_SND_PCI is not set
|
|
||||||
# CONFIG_SND_ARM is not set
|
|
||||||
# CONFIG_SND_SPI is not set
|
|
||||||
# CONFIG_SND_USB is not set
|
|
||||||
CONFIG_SND_SOC=y
|
|
||||||
CONFIG_SND_IMX_SOC=y
|
|
||||||
CONFIG_SND_SOC_IMX_SGTL5000=y
|
|
||||||
CONFIG_SND_SOC_IMX_HDMI=y
|
|
||||||
CONFIG_HID_MULTITOUCH=y
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_USB_OTG=y
|
|
||||||
CONFIG_USB_EHCI_HCD=y
|
|
||||||
CONFIG_USB_ACM=y
|
|
||||||
CONFIG_USB_STORAGE=y
|
|
||||||
CONFIG_USB_CHIPIDEA=y
|
|
||||||
CONFIG_USB_CHIPIDEA_UDC=y
|
|
||||||
CONFIG_USB_CHIPIDEA_HOST=y
|
|
||||||
CONFIG_USB_SERIAL=y
|
|
||||||
CONFIG_USB_SERIAL_QUALCOMM=y
|
|
||||||
CONFIG_USB_SERIAL_SIERRAWIRELESS=y
|
|
||||||
CONFIG_USB_SERIAL_OPTION=y
|
|
||||||
CONFIG_USB_MXS_PHY=y
|
|
||||||
CONFIG_USB_GADGET=y
|
|
||||||
CONFIG_USB_ETH=m
|
|
||||||
CONFIG_USB_MASS_STORAGE=m
|
|
||||||
CONFIG_USB_G_SERIAL=m
|
|
||||||
CONFIG_USB_CDC_COMPOSITE=m
|
|
||||||
CONFIG_MMC=y
|
|
||||||
CONFIG_MMC_SDHCI=y
|
|
||||||
CONFIG_MMC_SDHCI_PLTFM=y
|
|
||||||
CONFIG_MMC_SDHCI_ESDHC_IMX=y
|
|
||||||
CONFIG_MXC_IPU=y
|
|
||||||
CONFIG_MXC_IPU_V3_PRE=y
|
|
||||||
CONFIG_MXC_MIPI_CSI2=y
|
|
||||||
CONFIG_NEW_LEDS=y
|
|
||||||
CONFIG_LEDS_CLASS=y
|
|
||||||
CONFIG_LEDS_DA9063=y
|
|
||||||
CONFIG_RTC_CLASS=y
|
|
||||||
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
|
|
||||||
CONFIG_RTC_DRV_DA9063=y
|
|
||||||
CONFIG_RTC_DRV_MC13XXX=y
|
|
||||||
CONFIG_RTC_DRV_MXC=y
|
|
||||||
CONFIG_RTC_DRV_SNVS=y
|
|
||||||
CONFIG_DMADEVICES=y
|
|
||||||
CONFIG_IMX_SDMA=y
|
|
||||||
CONFIG_MXS_DMA=y
|
|
||||||
CONFIG_MXC_PXP_V2=y
|
|
||||||
# CONFIG_IOMMU_SUPPORT is not set
|
|
||||||
CONFIG_EXTCON_USB_GPIO=y
|
|
||||||
CONFIG_PWM=y
|
|
||||||
CONFIG_PWM_IMX=y
|
|
||||||
CONFIG_EXT4_FS=y
|
|
||||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
|
||||||
CONFIG_EXT4_FS_SECURITY=y
|
|
||||||
CONFIG_OVERLAY_FS=y
|
|
||||||
CONFIG_MSDOS_FS=y
|
|
||||||
CONFIG_VFAT_FS=y
|
|
||||||
CONFIG_TMPFS=y
|
|
||||||
CONFIG_TMPFS_POSIX_ACL=y
|
|
||||||
# CONFIG_MISC_FILESYSTEMS is not set
|
|
||||||
CONFIG_NFS_FS=y
|
|
||||||
CONFIG_NFS_V3_ACL=y
|
|
||||||
CONFIG_NFS_V4=y
|
|
||||||
CONFIG_ROOT_NFS=y
|
|
||||||
CONFIG_NLS_DEFAULT="cp437"
|
|
||||||
CONFIG_NLS_CODEPAGE_437=y
|
|
||||||
CONFIG_NLS_CODEPAGE_850=y
|
|
||||||
CONFIG_NLS_ASCII=y
|
|
||||||
CONFIG_NLS_ISO8859_1=y
|
|
||||||
CONFIG_NLS_ISO8859_15=y
|
|
||||||
CONFIG_NLS_UTF8=y
|
|
||||||
CONFIG_DYNAMIC_DEBUG=y
|
|
||||||
CONFIG_DEBUG_FS=y
|
|
||||||
# CONFIG_SCHED_DEBUG is not set
|
|
||||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
|
||||||
# CONFIG_FTRACE is not set
|
|
||||||
# CONFIG_ARM_UNWIND is not set
|
|
||||||
CONFIG_SECURITYFS=y
|
|
||||||
CONFIG_CRYPTO_TEST=m
|
|
||||||
CONFIG_CRYPTO_XTS=y
|
|
||||||
CONFIG_CRYPTO_DEFLATE=y
|
|
||||||
CONFIG_CRYPTO_LZO=y
|
|
||||||
CONFIG_CRYPTO_USER_API_HASH=y
|
|
||||||
CONFIG_CRYPTO_USER_API_SKCIPHER=y
|
|
||||||
CONFIG_CRYPTO_DEV_FSL_CAAM=y
|
|
||||||
CONFIG_FONTS=y
|
|
||||||
CONFIG_VIRTUALIZATION=y
|
|
||||||
|
|
@ -1,365 +0,0 @@
|
||||||
CONFIG_KERNEL_LZO=y
|
|
||||||
CONFIG_SYSVIPC=y
|
|
||||||
CONFIG_POSIX_MQUEUE=y
|
|
||||||
CONFIG_NO_HZ=y
|
|
||||||
CONFIG_HIGH_RES_TIMERS=y
|
|
||||||
CONFIG_IKCONFIG=y
|
|
||||||
CONFIG_IKCONFIG_PROC=y
|
|
||||||
CONFIG_LOG_BUF_SHIFT=18
|
|
||||||
CONFIG_CGROUPS=y
|
|
||||||
CONFIG_MEMCG=y
|
|
||||||
CONFIG_MEMCG_SWAP=y
|
|
||||||
CONFIG_BLK_CGROUP=y
|
|
||||||
CONFIG_CGROUP_SCHED=y
|
|
||||||
CONFIG_CFS_BANDWIDTH=y
|
|
||||||
CONFIG_RT_GROUP_SCHED=y
|
|
||||||
CONFIG_CGROUP_FREEZER=y
|
|
||||||
CONFIG_CPUSETS=y
|
|
||||||
CONFIG_CGROUP_DEVICE=y
|
|
||||||
CONFIG_CGROUP_CPUACCT=y
|
|
||||||
CONFIG_CGROUP_PERF=y
|
|
||||||
CONFIG_NAMESPACES=y
|
|
||||||
CONFIG_USER_NS=y
|
|
||||||
CONFIG_RELAY=y
|
|
||||||
CONFIG_BLK_DEV_INITRD=y
|
|
||||||
# CONFIG_RD_LZMA is not set
|
|
||||||
# CONFIG_RD_XZ is not set
|
|
||||||
# CONFIG_RD_LZ4 is not set
|
|
||||||
CONFIG_EXPERT=y
|
|
||||||
CONFIG_KALLSYMS_ALL=y
|
|
||||||
CONFIG_PERF_EVENTS=y
|
|
||||||
# CONFIG_SLUB_DEBUG is not set
|
|
||||||
# CONFIG_COMPAT_BRK is not set
|
|
||||||
CONFIG_MODULES=y
|
|
||||||
CONFIG_MODULE_UNLOAD=y
|
|
||||||
CONFIG_MODVERSIONS=y
|
|
||||||
CONFIG_MODULE_SRCVERSION_ALL=y
|
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
|
||||||
CONFIG_ARCH_MXC=y
|
|
||||||
CONFIG_SOC_IMX6UL=y
|
|
||||||
# CONFIG_SWP_EMULATE is not set
|
|
||||||
CONFIG_ARM_ERRATA_764369=y
|
|
||||||
CONFIG_SMP=y
|
|
||||||
CONFIG_HAVE_ARM_ARCH_TIMER=y
|
|
||||||
CONFIG_VMSPLIT_2G=y
|
|
||||||
CONFIG_PREEMPT=y
|
|
||||||
CONFIG_AEABI=y
|
|
||||||
CONFIG_HIGHMEM=y
|
|
||||||
CONFIG_CMA=y
|
|
||||||
CONFIG_SECCOMP=y
|
|
||||||
CONFIG_CPU_FREQ=y
|
|
||||||
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
|
||||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
|
||||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
|
||||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
|
||||||
CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
|
|
||||||
CONFIG_ARM_IMX6Q_CPUFREQ=y
|
|
||||||
CONFIG_CPU_IDLE=y
|
|
||||||
CONFIG_VFP=y
|
|
||||||
CONFIG_NEON=y
|
|
||||||
CONFIG_PM_DEBUG=y
|
|
||||||
CONFIG_NET=y
|
|
||||||
CONFIG_PACKET=y
|
|
||||||
CONFIG_UNIX=y
|
|
||||||
CONFIG_INET=y
|
|
||||||
CONFIG_IP_PNP=y
|
|
||||||
CONFIG_IP_PNP_DHCP=y
|
|
||||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
|
||||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
|
||||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
|
||||||
CONFIG_BRIDGE=y
|
|
||||||
CONFIG_VLAN_8021Q=y
|
|
||||||
CONFIG_LLC2=y
|
|
||||||
CONFIG_CAN=y
|
|
||||||
CONFIG_CAN_FLEXCAN=y
|
|
||||||
CONFIG_BT=y
|
|
||||||
CONFIG_BT_RFCOMM=y
|
|
||||||
CONFIG_BT_RFCOMM_TTY=y
|
|
||||||
CONFIG_BT_BNEP=y
|
|
||||||
CONFIG_BT_BNEP_MC_FILTER=y
|
|
||||||
CONFIG_BT_BNEP_PROTO_FILTER=y
|
|
||||||
CONFIG_BT_HIDP=y
|
|
||||||
CONFIG_BT_HCIUART=y
|
|
||||||
CONFIG_BT_HCIUART_ATH3K=y
|
|
||||||
CONFIG_BT_HCIUART_IBS=y
|
|
||||||
CONFIG_CFG80211=y
|
|
||||||
CONFIG_CFG80211_CERTIFICATION_ONUS=y
|
|
||||||
CONFIG_CFG80211_DEBUGFS=y
|
|
||||||
CONFIG_CFG80211_WEXT=y
|
|
||||||
CONFIG_RFKILL=y
|
|
||||||
CONFIG_RFKILL_INPUT=y
|
|
||||||
CONFIG_RFKILL_REGULATOR=y
|
|
||||||
CONFIG_RFKILL_GPIO=y
|
|
||||||
CONFIG_DEVTMPFS=y
|
|
||||||
CONFIG_DEVTMPFS_MOUNT=y
|
|
||||||
# CONFIG_STANDALONE is not set
|
|
||||||
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
|
|
||||||
CONFIG_DMA_CMA=y
|
|
||||||
CONFIG_CMA_SIZE_MBYTES=0
|
|
||||||
CONFIG_IMX_WEIM=y
|
|
||||||
CONFIG_CONNECTOR=y
|
|
||||||
CONFIG_MTD=y
|
|
||||||
CONFIG_MTD_CMDLINE_PARTS=y
|
|
||||||
CONFIG_MTD_BLOCK=y
|
|
||||||
CONFIG_MTD_CFI=y
|
|
||||||
CONFIG_MTD_JEDECPROBE=y
|
|
||||||
CONFIG_MTD_CFI_INTELEXT=y
|
|
||||||
CONFIG_MTD_CFI_AMDSTD=y
|
|
||||||
CONFIG_MTD_CFI_STAA=y
|
|
||||||
CONFIG_MTD_PHYSMAP_OF=y
|
|
||||||
CONFIG_MTD_NAND=y
|
|
||||||
CONFIG_MTD_NAND_GPMI_NAND=y
|
|
||||||
CONFIG_MTD_UBI=y
|
|
||||||
CONFIG_MTD_UBI_FASTMAP=y
|
|
||||||
CONFIG_MTD_UBI_BLOCK=y
|
|
||||||
CONFIG_BLK_DEV_LOOP=y
|
|
||||||
CONFIG_BLK_DEV_RAM=y
|
|
||||||
CONFIG_BLK_DEV_RAM_SIZE=65536
|
|
||||||
CONFIG_EEPROM_AT24=y
|
|
||||||
CONFIG_EEPROM_AT25=y
|
|
||||||
CONFIG_SCSI=y
|
|
||||||
# CONFIG_SCSI_PROC_FS is not set
|
|
||||||
CONFIG_BLK_DEV_SD=y
|
|
||||||
CONFIG_NETDEVICES=y
|
|
||||||
# CONFIG_NET_VENDOR_ARC is not set
|
|
||||||
# CONFIG_NET_CADENCE is not set
|
|
||||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
|
||||||
# CONFIG_NET_VENDOR_CIRRUS is not set
|
|
||||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
|
||||||
# CONFIG_NET_VENDOR_HISILICON is not set
|
|
||||||
# CONFIG_NET_VENDOR_INTEL is not set
|
|
||||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
|
||||||
# CONFIG_NET_VENDOR_MICREL is not set
|
|
||||||
# CONFIG_NET_VENDOR_MICROCHIP is not set
|
|
||||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
|
||||||
# CONFIG_NET_VENDOR_QUALCOMM is not set
|
|
||||||
# CONFIG_NET_VENDOR_ROCKER is not set
|
|
||||||
# CONFIG_NET_VENDOR_SAMSUNG is not set
|
|
||||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
|
||||||
# CONFIG_NET_VENDOR_SMSC is not set
|
|
||||||
# CONFIG_NET_VENDOR_STMICRO is not set
|
|
||||||
# CONFIG_NET_VENDOR_VIA is not set
|
|
||||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
|
||||||
CONFIG_SMSC_PHY=y
|
|
||||||
CONFIG_PPP=y
|
|
||||||
CONFIG_PPP_BSDCOMP=y
|
|
||||||
CONFIG_PPP_DEFLATE=y
|
|
||||||
CONFIG_PPP_ASYNC=y
|
|
||||||
CONFIG_USB_USBNET=y
|
|
||||||
# CONFIG_USB_NET_AX8817X is not set
|
|
||||||
# CONFIG_USB_NET_AX88179_178A is not set
|
|
||||||
CONFIG_USB_NET_CDC_EEM=y
|
|
||||||
CONFIG_USB_NET_CDC_MBIM=y
|
|
||||||
# CONFIG_USB_NET_NET1080 is not set
|
|
||||||
# CONFIG_USB_NET_CDC_SUBSET is not set
|
|
||||||
# CONFIG_USB_NET_ZAURUS is not set
|
|
||||||
CONFIG_USB_NET_QMI_WWAN=y
|
|
||||||
CONFIG_USB_SIERRA_NET=y
|
|
||||||
CONFIG_HOSTAP=y
|
|
||||||
CONFIG_HOSTAP_FIRMWARE=y
|
|
||||||
CONFIG_HOSTAP_FIRMWARE_NVRAM=y
|
|
||||||
CONFIG_INPUT_POLLDEV=y
|
|
||||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
|
||||||
CONFIG_INPUT_EVDEV=y
|
|
||||||
CONFIG_KEYBOARD_GPIO=y
|
|
||||||
CONFIG_KEYBOARD_IMX=y
|
|
||||||
# CONFIG_INPUT_MOUSE is not set
|
|
||||||
CONFIG_INPUT_TOUCHSCREEN=y
|
|
||||||
CONFIG_TOUCHSCREEN_FUSION_7_10=y
|
|
||||||
CONFIG_TOUCHSCREEN_GOODIX=y
|
|
||||||
CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
|
|
||||||
CONFIG_INPUT_MISC=y
|
|
||||||
CONFIG_INPUT_MCA_CC6UL_PWRKEY=y
|
|
||||||
# CONFIG_SERIO_SERPORT is not set
|
|
||||||
# CONFIG_LEGACY_PTYS is not set
|
|
||||||
# CONFIG_DEVKMEM is not set
|
|
||||||
CONFIG_SERIAL_IMX=y
|
|
||||||
CONFIG_SERIAL_IMX_CONSOLE=y
|
|
||||||
CONFIG_SERIAL_MCA_CC6UL=y
|
|
||||||
CONFIG_FSL_OTP=y
|
|
||||||
# CONFIG_I2C_COMPAT is not set
|
|
||||||
CONFIG_I2C_CHARDEV=y
|
|
||||||
# CONFIG_I2C_HELPER_AUTO is not set
|
|
||||||
CONFIG_I2C_ALGOBIT=y
|
|
||||||
CONFIG_I2C_IMX=y
|
|
||||||
CONFIG_I2C_IMX_LPI2C=y
|
|
||||||
CONFIG_SPI=y
|
|
||||||
CONFIG_SPI_GPIO=y
|
|
||||||
CONFIG_SPI_IMX=y
|
|
||||||
CONFIG_SPI_FSL_LPSPI=y
|
|
||||||
CONFIG_SPI_SPIDEV=m
|
|
||||||
CONFIG_GPIO_SYSFS=y
|
|
||||||
CONFIG_GPIO_MCA_CC6UL=y
|
|
||||||
CONFIG_POWER_RESET=y
|
|
||||||
CONFIG_POWER_RESET_SYSCON=y
|
|
||||||
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
|
|
||||||
CONFIG_POWER_SUPPLY=y
|
|
||||||
# CONFIG_MXC_MMA8451 is not set
|
|
||||||
CONFIG_THERMAL=y
|
|
||||||
CONFIG_THERMAL_WRITABLE_TRIPS=y
|
|
||||||
CONFIG_CPU_THERMAL=y
|
|
||||||
CONFIG_IMX_THERMAL=y
|
|
||||||
CONFIG_DEVICE_THERMAL=y
|
|
||||||
CONFIG_WATCHDOG=y
|
|
||||||
CONFIG_WATCHDOG_NOWAYOUT=y
|
|
||||||
CONFIG_MCA_CC6UL_WATCHDOG=y
|
|
||||||
CONFIG_IMX2_WDT=y
|
|
||||||
CONFIG_MFD_MCA_IOEXP=y
|
|
||||||
CONFIG_REGULATOR=y
|
|
||||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
|
||||||
CONFIG_REGULATOR_ANATOP=y
|
|
||||||
CONFIG_REGULATOR_GPIO=y
|
|
||||||
CONFIG_REGULATOR_PFUZE100=y
|
|
||||||
CONFIG_MEDIA_SUPPORT=y
|
|
||||||
CONFIG_MEDIA_CAMERA_SUPPORT=y
|
|
||||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
|
||||||
CONFIG_VIDEO_MXC_OUTPUT=y
|
|
||||||
CONFIG_VIDEO_MXC_CAPTURE=y
|
|
||||||
CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=y
|
|
||||||
# CONFIG_MXC_IPU_PRP_ENC is not set
|
|
||||||
CONFIG_VIDEO_MXC_PXP_V4L2=y
|
|
||||||
CONFIG_VIDEO_MXC_CSI_CAMERA=y
|
|
||||||
CONFIG_MXC_SUBDEV_CAMERA_OV5640=y
|
|
||||||
CONFIG_MXC_SUBDEV_CAMERA_OV5642=y
|
|
||||||
CONFIG_SOC_CAMERA=y
|
|
||||||
CONFIG_V4L_MEM2MEM_DRIVERS=y
|
|
||||||
CONFIG_VIDEO_CODA=y
|
|
||||||
CONFIG_FB=y
|
|
||||||
# CONFIG_FB_MX3 is not set
|
|
||||||
CONFIG_FB_MXS=y
|
|
||||||
CONFIG_FB_MXC_SYNC_PANEL=y
|
|
||||||
CONFIG_FB_MXC_LDB=y
|
|
||||||
# CONFIG_FB_MXC_EDID is not set
|
|
||||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
|
||||||
CONFIG_LCD_CLASS_DEVICE=y
|
|
||||||
CONFIG_LCD_PLATFORM=y
|
|
||||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
|
||||||
CONFIG_BACKLIGHT_PWM=y
|
|
||||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
|
||||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
|
||||||
CONFIG_LOGO=y
|
|
||||||
CONFIG_FB_LOGO_CENTERED=y
|
|
||||||
# CONFIG_LOGO_LINUX_MONO is not set
|
|
||||||
# CONFIG_LOGO_LINUX_VGA16 is not set
|
|
||||||
# CONFIG_LOGO_LINUX_CLUT224 is not set
|
|
||||||
CONFIG_SOUND=y
|
|
||||||
CONFIG_SND=y
|
|
||||||
# CONFIG_SND_SPI is not set
|
|
||||||
# CONFIG_SND_USB is not set
|
|
||||||
CONFIG_SND_SOC=y
|
|
||||||
CONFIG_SND_SOC_FSL_ASRC=y
|
|
||||||
CONFIG_SND_IMX_SOC=y
|
|
||||||
CONFIG_SND_SOC_IMX_MAX98088=y
|
|
||||||
CONFIG_SND_SOC_IMX_SPDIF=y
|
|
||||||
CONFIG_SND_SOC_FSL_ASOC_CARD=y
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_USB_OTG_WHITELIST=y
|
|
||||||
CONFIG_USB_EHCI_HCD=y
|
|
||||||
CONFIG_USB_EHCI_MXC=y
|
|
||||||
CONFIG_USB_HCD_TEST_MODE=y
|
|
||||||
CONFIG_USB_ACM=y
|
|
||||||
CONFIG_USB_STORAGE=y
|
|
||||||
CONFIG_USB_CHIPIDEA=y
|
|
||||||
CONFIG_USB_CHIPIDEA_UDC=y
|
|
||||||
CONFIG_USB_CHIPIDEA_HOST=y
|
|
||||||
CONFIG_USB_SERIAL=y
|
|
||||||
CONFIG_USB_SERIAL_GENERIC=y
|
|
||||||
CONFIG_USB_SERIAL_QUALCOMM=y
|
|
||||||
CONFIG_USB_SERIAL_SIERRAWIRELESS=y
|
|
||||||
CONFIG_USB_SERIAL_OPTION=y
|
|
||||||
CONFIG_USB_EHSET_TEST_FIXTURE=y
|
|
||||||
CONFIG_NOP_USB_XCEIV=y
|
|
||||||
CONFIG_USB_MXS_PHY=y
|
|
||||||
CONFIG_USB_GADGET=y
|
|
||||||
CONFIG_USB_FSL_USB2=y
|
|
||||||
CONFIG_USB_ETH=m
|
|
||||||
CONFIG_USB_MASS_STORAGE=m
|
|
||||||
CONFIG_USB_G_SERIAL=m
|
|
||||||
CONFIG_USB_CDC_COMPOSITE=m
|
|
||||||
CONFIG_MMC=y
|
|
||||||
CONFIG_MMC_SDHCI=y
|
|
||||||
CONFIG_MMC_SDHCI_PLTFM=y
|
|
||||||
CONFIG_MMC_SDHCI_ESDHC_IMX=y
|
|
||||||
CONFIG_MXC_IPU=y
|
|
||||||
CONFIG_MXC_SIM=y
|
|
||||||
CONFIG_NEW_LEDS=y
|
|
||||||
CONFIG_LEDS_CLASS=y
|
|
||||||
CONFIG_LEDS_GPIO=y
|
|
||||||
CONFIG_LEDS_PWM=y
|
|
||||||
CONFIG_LEDS_TRIGGERS=y
|
|
||||||
CONFIG_LEDS_TRIGGER_TIMER=y
|
|
||||||
CONFIG_LEDS_TRIGGER_ONESHOT=y
|
|
||||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
|
||||||
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
|
|
||||||
CONFIG_LEDS_TRIGGER_GPIO=y
|
|
||||||
CONFIG_RTC_CLASS=y
|
|
||||||
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
|
|
||||||
CONFIG_RTC_DRV_MCA_CC6UL=y
|
|
||||||
CONFIG_RTC_DRV_MXC=y
|
|
||||||
CONFIG_RTC_DRV_SNVS=y
|
|
||||||
CONFIG_DMADEVICES=y
|
|
||||||
CONFIG_IMX_SDMA=y
|
|
||||||
CONFIG_MXS_DMA=y
|
|
||||||
CONFIG_MXC_PXP_V2=y
|
|
||||||
CONFIG_MXC_PXP_V3=y
|
|
||||||
CONFIG_STAGING=y
|
|
||||||
CONFIG_STAGING_MEDIA=y
|
|
||||||
# CONFIG_IOMMU_SUPPORT is not set
|
|
||||||
CONFIG_IIO=y
|
|
||||||
CONFIG_MCA_CC6UL_ADC=y
|
|
||||||
CONFIG_VF610_ADC=y
|
|
||||||
CONFIG_TAMPER_MCA_CC6UL=y
|
|
||||||
CONFIG_PWM=y
|
|
||||||
CONFIG_PWM_IMX=y
|
|
||||||
# CONFIG_RESET_GPIO is not set
|
|
||||||
CONFIG_NVMEM_IMX_OCOTP=y
|
|
||||||
CONFIG_EXT4_FS=y
|
|
||||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
|
||||||
CONFIG_EXT4_FS_SECURITY=y
|
|
||||||
CONFIG_AUTOFS4_FS=y
|
|
||||||
CONFIG_OVERLAY_FS=y
|
|
||||||
CONFIG_VFAT_FS=y
|
|
||||||
CONFIG_TMPFS=y
|
|
||||||
CONFIG_UBIFS_FS=y
|
|
||||||
CONFIG_NFS_FS=y
|
|
||||||
CONFIG_NFS_V3_ACL=y
|
|
||||||
CONFIG_NFS_V4=y
|
|
||||||
CONFIG_ROOT_NFS=y
|
|
||||||
CONFIG_NLS_DEFAULT="cp437"
|
|
||||||
CONFIG_NLS_CODEPAGE_437=y
|
|
||||||
CONFIG_NLS_ASCII=y
|
|
||||||
CONFIG_NLS_ISO8859_1=y
|
|
||||||
CONFIG_NLS_UTF8=y
|
|
||||||
CONFIG_DEBUG_FS=y
|
|
||||||
CONFIG_MAGIC_SYSRQ=y
|
|
||||||
# CONFIG_SCHED_DEBUG is not set
|
|
||||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
|
||||||
# CONFIG_FTRACE is not set
|
|
||||||
CONFIG_CRYPTO_USER=y
|
|
||||||
CONFIG_CRYPTO_CBC=y
|
|
||||||
CONFIG_CRYPTO_CTR=y
|
|
||||||
CONFIG_CRYPTO_CTS=y
|
|
||||||
CONFIG_CRYPTO_LRW=y
|
|
||||||
CONFIG_CRYPTO_XTS=y
|
|
||||||
CONFIG_CRYPTO_GHASH=y
|
|
||||||
CONFIG_CRYPTO_MD4=y
|
|
||||||
CONFIG_CRYPTO_MD5=y
|
|
||||||
CONFIG_CRYPTO_RMD128=y
|
|
||||||
CONFIG_CRYPTO_RMD160=y
|
|
||||||
CONFIG_CRYPTO_RMD256=y
|
|
||||||
CONFIG_CRYPTO_RMD320=y
|
|
||||||
CONFIG_CRYPTO_SHA1=y
|
|
||||||
CONFIG_CRYPTO_SHA512=y
|
|
||||||
CONFIG_CRYPTO_TGR192=y
|
|
||||||
CONFIG_CRYPTO_WP512=y
|
|
||||||
CONFIG_CRYPTO_BLOWFISH=y
|
|
||||||
CONFIG_CRYPTO_CAMELLIA=y
|
|
||||||
CONFIG_CRYPTO_TWOFISH=y
|
|
||||||
CONFIG_CRYPTO_DEV_FSL_CAAM=y
|
|
||||||
CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
|
|
||||||
CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
|
|
||||||
CONFIG_CRC_T10DIF=y
|
|
||||||
CONFIG_FONTS=y
|
|
||||||
CONFIG_FONT_8x8=y
|
|
||||||
CONFIG_FONT_8x16=y
|
|
||||||
CONFIG_VIRTUALIZATION=y
|
|
||||||
|
|
@ -0,0 +1,15 @@
|
||||||
|
# Copyright (C) 2018 Digi International
|
||||||
|
|
||||||
|
LICENSE = "GPLv2"
|
||||||
|
LIC_FILES_CHKSUM = "file://COPYING;md5=d7810fab7487fb0aad327b76f1be7cd7"
|
||||||
|
|
||||||
|
LOCALVERSION = "-dey"
|
||||||
|
SRCBRANCH = "v4.9/dey-2.4/maint"
|
||||||
|
SRCBRANCH_ccimx8x = "v4.9.88/master"
|
||||||
|
SRCREV = "${AUTOREV}"
|
||||||
|
|
||||||
|
# Select internal or Github Linux repo
|
||||||
|
LINUX_GIT_URI ?= "${@base_conditional('DIGI_INTERNAL_GIT', '1' , '${DIGI_GIT}linux-2.6.git', '${DIGI_GITHUB_GIT}/linux.git', d)}"
|
||||||
|
SRC_URI = "${LINUX_GIT_URI};branch=${SRCBRANCH}"
|
||||||
|
|
||||||
|
S = "${WORKDIR}/git"
|
||||||
|
|
@ -9,17 +9,10 @@ DEPENDS += "${@base_conditional('TRUSTFENCE_SIGN', '1', 'trustfence-sign-tools-n
|
||||||
|
|
||||||
inherit kernel fsl-kernel-localversion
|
inherit kernel fsl-kernel-localversion
|
||||||
|
|
||||||
LOCALVERSION = "-dey"
|
require recipes-kernel/linux/linux-dey-src.inc
|
||||||
|
|
||||||
# Select internal or Github Linux repo
|
# Use custom provided 'defconfig' if variable KERNEL_DEFCONFIG is cleared
|
||||||
LINUX_GIT_URI ?= "${@base_conditional('DIGI_INTERNAL_GIT', '1' , '${DIGI_GIT}linux-2.6.git', '${DIGI_GITHUB_GIT}/linux.git', d)}"
|
SRC_URI += "${@base_conditional('KERNEL_DEFCONFIG', '', 'file://defconfig', '', d)}"
|
||||||
|
|
||||||
SRC_URI = " \
|
|
||||||
${LINUX_GIT_URI};branch=${SRCBRANCH} \
|
|
||||||
file://defconfig \
|
|
||||||
"
|
|
||||||
|
|
||||||
S = "${WORKDIR}/git"
|
|
||||||
|
|
||||||
do_deploy[postfuncs] += "${@base_conditional('TRUSTFENCE_SIGN', '1', 'trustfence_sign', '', d)}"
|
do_deploy[postfuncs] += "${@base_conditional('TRUSTFENCE_SIGN', '1', 'trustfence_sign', '', d)}"
|
||||||
|
|
||||||
|
|
@ -58,3 +51,21 @@ FILES_kernel-image += "/boot/config-${KERNEL_VERSION}"
|
||||||
|
|
||||||
# Don't include kernels in standard images
|
# Don't include kernels in standard images
|
||||||
RDEPENDS_kernel-base = ""
|
RDEPENDS_kernel-base = ""
|
||||||
|
|
||||||
|
# A user can provide his own kernel 'defconfig' file by:
|
||||||
|
# - setting the variable KERNEL_DEFCONFIG to a custom kernel configuration file
|
||||||
|
# inside the kernel repository.
|
||||||
|
# - setting the variable KERNEL_DEFCONFIG to a kernel configuration file using
|
||||||
|
# the full path to the file.
|
||||||
|
# - clearing the variable KERNEL_DEFCONFIG and providing a kernel configuration
|
||||||
|
# file in the layer (in this case the file must be named 'defconfig').
|
||||||
|
# Otherwise the default platform's kernel configuration file will be taken from
|
||||||
|
# the Linux source code tree.
|
||||||
|
do_copy_defconfig[vardeps] += "KERNEL_DEFCONFIG"
|
||||||
|
do_copy_defconfig[dirs] = "${S}"
|
||||||
|
do_copy_defconfig () {
|
||||||
|
if [ -n "${KERNEL_DEFCONFIG}" ]; then
|
||||||
|
cp -f ${KERNEL_DEFCONFIG} ${WORKDIR}/defconfig
|
||||||
|
fi
|
||||||
|
}
|
||||||
|
addtask copy_defconfig after do_patch before do_preconfigure
|
||||||
|
|
|
||||||
|
|
@ -2,7 +2,4 @@
|
||||||
|
|
||||||
require recipes-kernel/linux/linux-dey.inc
|
require recipes-kernel/linux/linux-dey.inc
|
||||||
|
|
||||||
SRCBRANCH = "v4.9/dey-2.4/maint"
|
COMPATIBLE_MACHINE = "(ccimx6|ccimx6ul|ccimx8x)"
|
||||||
SRCREV = "${AUTOREV}"
|
|
||||||
|
|
||||||
COMPATIBLE_MACHINE = "(ccimx6|ccimx6ul)"
|
|
||||||
|
|
|
||||||
|
|
@ -36,6 +36,10 @@ python () {
|
||||||
import hashlib
|
import hashlib
|
||||||
import os
|
import os
|
||||||
|
|
||||||
|
if ("ccimx8x" in d.getVar("MACHINE", True)):
|
||||||
|
bb.fatal("Trustfence is not currently supported on the ccimx8x SOM")
|
||||||
|
return
|
||||||
|
|
||||||
# Secure console configuration
|
# Secure console configuration
|
||||||
if (d.getVar("TRUSTFENCE_CONSOLE_DISABLE", True) == "1"):
|
if (d.getVar("TRUSTFENCE_CONSOLE_DISABLE", True) == "1"):
|
||||||
d.appendVar("UBOOT_EXTRA_CONF", "CONFIG_CONSOLE_DISABLE=y ")
|
d.appendVar("UBOOT_EXTRA_CONF", "CONFIG_CONSOLE_DISABLE=y ")
|
||||||
|
|
|
||||||
|
|
@ -22,12 +22,13 @@ POKY_DEFAULT_EXTRA_RRECOMMENDS = ""
|
||||||
DISTRO_FEATURES ?= "${DISTRO_FEATURES_DEFAULT} ${DISTRO_FEATURES_LIBC} ${POKY_DEFAULT_DISTRO_FEATURES}"
|
DISTRO_FEATURES ?= "${DISTRO_FEATURES_DEFAULT} ${DISTRO_FEATURES_LIBC} ${POKY_DEFAULT_DISTRO_FEATURES}"
|
||||||
|
|
||||||
# Removed DISTRO_FEATURES
|
# Removed DISTRO_FEATURES
|
||||||
# 'wayland' -> not supported at the moment
|
# 'wayland' -> only supported on the i.MX8 QXP
|
||||||
# 'ptest' -> fails to build QT5 toolchain
|
# 'ptest' -> fails to build QT5 toolchain
|
||||||
DISTRO_FEATURES_DEFAULT_remove = "3g nfc nfs zeroconf"
|
DISTRO_FEATURES_DEFAULT_remove = "3g nfc nfs zeroconf"
|
||||||
POKY_DEFAULT_DISTRO_FEATURES_remove = "ptest wayland"
|
POKY_DEFAULT_DISTRO_FEATURES_remove = "ptest wayland"
|
||||||
|
|
||||||
GRAPHICAL_BACKEND = "${@bb.utils.contains('DISTRO_FEATURES', 'x11', 'x11', 'fb', d)}"
|
GRAPHICAL_BACKEND = "${@bb.utils.contains('DISTRO_FEATURES', 'x11 wayland', 'xwayland', \
|
||||||
|
bb.utils.contains('DISTRO_FEATURES', 'x11', 'x11', 'fb', d), d)}"
|
||||||
|
|
||||||
# Recovery initramfs image name.
|
# Recovery initramfs image name.
|
||||||
RECOVERY_INITRAMFS_IMAGE ?= "dey-image-recovery-initramfs"
|
RECOVERY_INITRAMFS_IMAGE ?= "dey-image-recovery-initramfs"
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,93 @@
|
||||||
|
#!/bin/sh
|
||||||
|
#===============================================================================
|
||||||
|
#
|
||||||
|
# Copyright (C) 2018 by Digi International Inc.
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or modify it
|
||||||
|
# under the terms of the GNU General Public License version 2 as published by
|
||||||
|
# the Free Software Foundation.
|
||||||
|
#
|
||||||
|
#
|
||||||
|
# !Description: Initialize bluetooth hardware
|
||||||
|
#
|
||||||
|
#===============================================================================
|
||||||
|
|
||||||
|
# Bluetooth power GPIO
|
||||||
|
BT_EN_QCA_GPIO_NR="394"
|
||||||
|
|
||||||
|
# set_gpio_value <gpio_nr> <value>
|
||||||
|
set_gpio_value() {
|
||||||
|
local SG_GPIONR="${1}"
|
||||||
|
local SG_GPIOVAL="${2}"
|
||||||
|
local SG_GPIOPATH="/sys/class/gpio/gpio${SG_GPIONR}"
|
||||||
|
|
||||||
|
[ -d "${SG_GPIOPATH}" ] || printf "%s" "${SG_GPIONR}" > /sys/class/gpio/export
|
||||||
|
printf out > "${SG_GPIOPATH}/direction" && sleep .2
|
||||||
|
printf "${SG_GPIOVAL}" > "${SG_GPIOPATH}/value" && sleep .2
|
||||||
|
[ -d "${SG_GPIOPATH}" ] && printf "%s" "${SG_GPIONR}" > /sys/class/gpio/unexport
|
||||||
|
}
|
||||||
|
|
||||||
|
# powercycle_gpio <gpio_nr>
|
||||||
|
powercycle_gpio() {
|
||||||
|
set_gpio_value "${1}" 0
|
||||||
|
set_gpio_value "${1}" 1
|
||||||
|
}
|
||||||
|
|
||||||
|
error() {
|
||||||
|
echo ${1}
|
||||||
|
exit 1
|
||||||
|
}
|
||||||
|
|
||||||
|
bluetooth_init() {
|
||||||
|
# Get MAC address from the device tree. Use a default value if it has not been set.
|
||||||
|
BT_MACADDR="$(hexdump -ve '1/1 "%02X" ":"' /proc/device-tree/bluetooth/mac-address 2>/dev/null | sed 's/:$//g')"
|
||||||
|
if [ -z "${BT_MACADDR}" ] || [ "${BT_MACADDR}" = "00:00:00:00:00:00" ]; then
|
||||||
|
BT_MACADDR="00:04:F3:FF:FF:BB"
|
||||||
|
fi
|
||||||
|
|
||||||
|
# Start the Bluetooth driver and bring up the interface
|
||||||
|
HCIATTACH_LOG="/var/log/hciattach.log"
|
||||||
|
|
||||||
|
for RETRY in $(seq 1 5)
|
||||||
|
do
|
||||||
|
killproc hciattach
|
||||||
|
powercycle_gpio "${BT_EN_QCA_GPIO_NR}"
|
||||||
|
if hciattach ttyBt qca ${BT_RATE:-3000000} -t30 ${BT_FLOW:-flow} unused ${BT_MACADDR} >${HCIATTACH_LOG} 2>&1; then
|
||||||
|
return
|
||||||
|
fi
|
||||||
|
sleep 1
|
||||||
|
done
|
||||||
|
BT_ERROR="FAIL (hciattach)"
|
||||||
|
}
|
||||||
|
|
||||||
|
# Source function library
|
||||||
|
. /etc/init.d/functions
|
||||||
|
|
||||||
|
case "$1" in
|
||||||
|
start)
|
||||||
|
if [ -d "/proc/device-tree/bluetooth" ]; then
|
||||||
|
echo -n "Starting bluetooth hardware: "
|
||||||
|
bluetooth_init
|
||||||
|
echo "${BT_ERROR:-done.}"
|
||||||
|
fi
|
||||||
|
;;
|
||||||
|
stop)
|
||||||
|
if [ -d "/sys/class/bluetooth/hci0" ]; then
|
||||||
|
echo -n "Stopping bluetooth hardware: "
|
||||||
|
killproc hciattach
|
||||||
|
# Power down bluetooth
|
||||||
|
set_gpio_value "${BT_EN_QCA_GPIO_NR}" 0
|
||||||
|
echo "done."
|
||||||
|
fi
|
||||||
|
;;
|
||||||
|
restart)
|
||||||
|
$0 stop
|
||||||
|
sleep 1
|
||||||
|
$0 start
|
||||||
|
;;
|
||||||
|
*)
|
||||||
|
echo "Usage: $0 {start|stop|restart}"
|
||||||
|
exit 1
|
||||||
|
;;
|
||||||
|
esac
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
[General]
|
||||||
|
|
||||||
|
# Default adapter name
|
||||||
|
# Defaults to 'BlueZ X.YZ'
|
||||||
|
Name = cc8x
|
||||||
|
|
||||||
|
[Policy]
|
||||||
|
|
||||||
|
# AutoEnable defines option to enable all controllers when they are found.
|
||||||
|
# This includes adapters present on start as well as adapters that are plugged
|
||||||
|
# in later on. Defaults to 'false'.
|
||||||
|
AutoEnable=true
|
||||||
|
|
@ -18,15 +18,15 @@ SRC_URI += " \
|
||||||
file://0011-core-Fix-BR-EDR-pairing-for-dual-mode-devices.patch \
|
file://0011-core-Fix-BR-EDR-pairing-for-dual-mode-devices.patch \
|
||||||
"
|
"
|
||||||
|
|
||||||
QCA6564_COMMON_PATCHES = " \
|
QCA65XX_COMMON_PATCHES = " \
|
||||||
file://0012-QCA_bluetooth_chip_support.patch \
|
file://0012-QCA_bluetooth_chip_support.patch \
|
||||||
file://0013-hciattach_rome-Respect-the-user-indication-for-noflo.patch \
|
file://0013-hciattach_rome-Respect-the-user-indication-for-noflo.patch \
|
||||||
file://0014-hciattach-If-the-user-supplies-a-bdaddr-use-it.patch \
|
file://0014-hciattach-If-the-user-supplies-a-bdaddr-use-it.patch \
|
||||||
file://0015-hciattach-Add-verbosity-option.patch \
|
file://0015-hciattach-Add-verbosity-option.patch \
|
||||||
"
|
"
|
||||||
|
|
||||||
SRC_URI_append_ccimx6ul = " ${QCA6564_COMMON_PATCHES}"
|
SRC_URI_append_ccimx6ul = " ${QCA65XX_COMMON_PATCHES}"
|
||||||
SRC_URI_append_ccimx6qpsbc = " ${QCA6564_COMMON_PATCHES}"
|
SRC_URI_append_ccimx6qpsbc = " ${QCA65XX_COMMON_PATCHES}"
|
||||||
|
|
||||||
inherit update-rc.d
|
inherit update-rc.d
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -10,15 +10,16 @@ SRC_URI += " \
|
||||||
file://0003-port-test-discovery-to-python3.patch \
|
file://0003-port-test-discovery-to-python3.patch \
|
||||||
"
|
"
|
||||||
|
|
||||||
QCA6564_COMMON_PATCHES = " \
|
QCA65XX_COMMON_PATCHES = " \
|
||||||
file://0004-QCA_bluetooth_chip_support.patch \
|
file://0004-QCA_bluetooth_chip_support.patch \
|
||||||
file://0005-hciattach_rome-Respect-the-user-indication-for-noflo.patch \
|
file://0005-hciattach_rome-Respect-the-user-indication-for-noflo.patch \
|
||||||
file://0006-hciattach-If-the-user-supplies-a-bdaddr-use-it.patch \
|
file://0006-hciattach-If-the-user-supplies-a-bdaddr-use-it.patch \
|
||||||
file://0007-hciattach-Add-verbosity-option.patch \
|
file://0007-hciattach-Add-verbosity-option.patch \
|
||||||
"
|
"
|
||||||
|
|
||||||
SRC_URI_append_ccimx6ul = " ${QCA6564_COMMON_PATCHES}"
|
SRC_URI_append_ccimx6ul = " ${QCA65XX_COMMON_PATCHES}"
|
||||||
SRC_URI_append_ccimx6qpsbc = " ${QCA6564_COMMON_PATCHES}"
|
SRC_URI_append_ccimx6qpsbc = " ${QCA65XX_COMMON_PATCHES}"
|
||||||
|
SRC_URI_append_ccimx8x = " ${QCA65XX_COMMON_PATCHES}"
|
||||||
|
|
||||||
inherit update-rc.d
|
inherit update-rc.d
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,11 @@
|
||||||
# Copyright (C) 2016,2017 Digi International.
|
# Copyright (C) 2016-2018 Digi International.
|
||||||
|
|
||||||
FILESEXTRAPATHS_prepend := "${THISDIR}/${BPN}:"
|
FILESEXTRAPATHS_prepend := "${THISDIR}/${BPN}:"
|
||||||
|
|
||||||
SRC_URI_append = " file://hostapd_wlan0.conf"
|
SRC_URI_append = " file://hostapd_wlan0.conf"
|
||||||
SRC_URI_append_ccimx6ul = " file://hostapd_wlan1.conf"
|
SRC_URI_append_ccimx6ul = " file://hostapd_wlan1.conf"
|
||||||
SRC_URI_append_ccimx6qpsbc = " file://hostapd_wlan1.conf"
|
SRC_URI_append_ccimx6qpsbc = " file://hostapd_wlan1.conf"
|
||||||
|
SRC_URI_append_ccimx8x = " file://hostapd_wlan1.conf"
|
||||||
|
|
||||||
do_install_append() {
|
do_install_append() {
|
||||||
# Remove the default hostapd.conf
|
# Remove the default hostapd.conf
|
||||||
|
|
@ -23,6 +24,11 @@ do_install_append_ccimx6qpsbc() {
|
||||||
install -m 0644 ${WORKDIR}/hostapd_wlan1.conf ${D}${sysconfdir}
|
install -m 0644 ${WORKDIR}/hostapd_wlan1.conf ${D}${sysconfdir}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
do_install_append_ccimx8x() {
|
||||||
|
# Install custom hostapd_IFACE.conf file
|
||||||
|
install -m 0644 ${WORKDIR}/hostapd_wlan1.conf ${D}${sysconfdir}
|
||||||
|
}
|
||||||
|
|
||||||
pkg_postinst_${PN}() {
|
pkg_postinst_${PN}() {
|
||||||
# Append the last two bytes of the wlan0 MAC address to the SSID of the
|
# Append the last two bytes of the wlan0 MAC address to the SSID of the
|
||||||
# hostAP configuration files
|
# hostAP configuration files
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,10 @@
|
||||||
|
ACTION!="add|change|move", GOTO="mm_digi_xbee_cellular_modem_end"
|
||||||
|
|
||||||
|
# By default, ModemManager expects a default baudrate of 57600bps. Different
|
||||||
|
# baudrates may be used by setting the ID_MM_TTY_BAUDRATE udev tag.
|
||||||
|
|
||||||
|
# ModemManager documentation states that the best practice is to use the DEVPATH
|
||||||
|
# this way rather than other rules such as KERNEL, so be careful when modifying
|
||||||
|
DEVPATH=="/devices/platform/5a060000.serial/tty/ttyLP0", ENV{ID_MM_PLATFORM_DRIVER_PROBE}="1", ENV{ID_MM_PHYSDEV_UID}="Digi XBee Cellular"
|
||||||
|
|
||||||
|
LABEL="mm_digi_xbee_cellular_modem_end"
|
||||||
|
|
@ -0,0 +1,40 @@
|
||||||
|
From: Gabriel Valcazar <gabriel.valcazar@digi.com>
|
||||||
|
Date: Wed, 2 May 2018 18:49:28 +0200
|
||||||
|
Subject: [PATCH] Modify openssl.cnf to automatically load the cryptochip
|
||||||
|
engine
|
||||||
|
|
||||||
|
https://jira.digi.com/browse/DEL-5592
|
||||||
|
|
||||||
|
Signed-off-by: Gabriel Valcazar <gabriel.valcazar@digi.com>
|
||||||
|
---
|
||||||
|
apps/openssl.cnf | 13 +++++++++++++
|
||||||
|
1 file changed, 13 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/apps/openssl.cnf b/apps/openssl.cnf
|
||||||
|
index 1eb86c4..49d9d83 100644
|
||||||
|
--- a/apps/openssl.cnf
|
||||||
|
+++ b/apps/openssl.cnf
|
||||||
|
@@ -3,6 +3,8 @@
|
||||||
|
# This is mostly being used for generation of certificate requests.
|
||||||
|
#
|
||||||
|
|
||||||
|
+openssl_conf = openssl_init
|
||||||
|
+
|
||||||
|
# This definition stops the following lines choking if HOME isn't
|
||||||
|
# defined.
|
||||||
|
HOME = .
|
||||||
|
@@ -348,3 +350,14 @@ tsa_name = yes # Must the TSA name be included in the reply?
|
||||||
|
# (optional, default: no)
|
||||||
|
ess_cert_id_chain = no # Must the ESS cert id chain be included?
|
||||||
|
# (optional, default: no)
|
||||||
|
+
|
||||||
|
+[ openssl_init ]
|
||||||
|
+engines = engine_section
|
||||||
|
+
|
||||||
|
+[ engine_section ]
|
||||||
|
+ateccx08 = ateccx08_config
|
||||||
|
+
|
||||||
|
+[ ateccx08_config ]
|
||||||
|
+engine_id = ateccx08
|
||||||
|
+dynamic_path = /usr/lib/ssl/engines/libateccssl.so
|
||||||
|
+init = 0
|
||||||
|
|
@ -1,8 +1,13 @@
|
||||||
# Copyright (C) 2016 Digi International.
|
# Copyright (C) 2016-2018 Digi International.
|
||||||
|
|
||||||
FILESEXTRAPATHS_prepend := "${THISDIR}/${BPN}:"
|
FILESEXTRAPATHS_prepend := "${THISDIR}/${BPN}:"
|
||||||
|
|
||||||
|
CRYPTOCHIP_COMMON_PATCHES = " \
|
||||||
|
file://0003-Modify-openssl.cnf-to-automatically-load-the-cryptoc.patch \
|
||||||
|
"
|
||||||
|
|
||||||
SRC_URI += " \
|
SRC_URI += " \
|
||||||
file://0001-cryptodev-Fix-issue-with-signature-generation.patch \
|
file://0001-cryptodev-Fix-issue-with-signature-generation.patch \
|
||||||
file://0002-cryptodev-allow-copying-EVP-contexts.patch \
|
file://0002-cryptodev-allow-copying-EVP-contexts.patch \
|
||||||
|
${@bb.utils.contains("MACHINE_FEATURES", "cryptochip", "${CRYPTOCHIP_COMMON_PATCHES}", "", d)} \
|
||||||
"
|
"
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
#
|
#
|
||||||
# Copyright (C) 2012-2017 Digi International.
|
# Copyright (C) 2012-2018 Digi International.
|
||||||
#
|
#
|
||||||
SUMMARY = "Wireless packagegroup for DEY image"
|
SUMMARY = "Wireless packagegroup for DEY image"
|
||||||
|
|
||||||
|
|
@ -17,3 +17,4 @@ RDEPENDS_${PN} = "\
|
||||||
|
|
||||||
RDEPENDS_${PN}_append_ccimx6ul = " hostapd"
|
RDEPENDS_${PN}_append_ccimx6ul = " hostapd"
|
||||||
RDEPENDS_${PN}_append_ccimx6qpsbc = " hostapd"
|
RDEPENDS_${PN}_append_ccimx6qpsbc = " hostapd"
|
||||||
|
RDEPENDS_${PN}_append_ccimx8x = " hostapd"
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,18 @@
|
||||||
|
ctrl_interface=/var/run/wpa_supplicant
|
||||||
|
ctrl_interface_group=0
|
||||||
|
fast_reauth=1
|
||||||
|
update_config=1
|
||||||
|
|
||||||
|
ap_scan=1
|
||||||
|
|
||||||
|
# Static scheduled scan interval time in seconds
|
||||||
|
#
|
||||||
|
# The wpa-supplicant dynamically adjusts the scheduled scan time interval. On
|
||||||
|
# occassions, fixing the interval time is helpful, for example on DFS channels.
|
||||||
|
#sched_scan_interval=2
|
||||||
|
|
||||||
|
network={
|
||||||
|
scan_ssid=1
|
||||||
|
ssid=""
|
||||||
|
key_mgmt=NONE
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,8 @@
|
||||||
|
ctrl_interface=/var/run/wpa_supplicant
|
||||||
|
update_config=1
|
||||||
|
device_name=ccimx8x-p2p
|
||||||
|
manufacturer=QCA
|
||||||
|
model_name=McK
|
||||||
|
device_type=1-0050F204-1
|
||||||
|
config_methods=display keypad push_button
|
||||||
|
persistent_reconnect=1
|
||||||
|
|
@ -0,0 +1,116 @@
|
||||||
|
#!/bin/sh
|
||||||
|
#===============================================================================
|
||||||
|
#
|
||||||
|
# standby
|
||||||
|
#
|
||||||
|
# Copyright (C) 2018 by Digi International Inc.
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or modify it
|
||||||
|
# under the terms of the GNU General Public License version 2 as published by
|
||||||
|
# the Free Software Foundation.
|
||||||
|
#
|
||||||
|
#
|
||||||
|
# !Description: suspend system to RAM
|
||||||
|
#
|
||||||
|
#===============================================================================
|
||||||
|
|
||||||
|
scriptname="$(basename $(readlink -f ${0}))"
|
||||||
|
syspower="/sys/power/state"
|
||||||
|
lockfile="/var/lock/${scriptname}.lock"
|
||||||
|
lockfd="9"
|
||||||
|
|
||||||
|
BT_INIT="/etc/init.d/bluetooth-init"
|
||||||
|
BT_DAEMON="/etc/init.d/bluetooth"
|
||||||
|
NM_DAEMON="/etc/init.d/networkmanager"
|
||||||
|
|
||||||
|
usage() {
|
||||||
|
printf "\nSuspend system to RAM memory\n"
|
||||||
|
printf "\nUsage: ${scriptname} [OPTIONS]\n
|
||||||
|
-h Show this help
|
||||||
|
\n"
|
||||||
|
}
|
||||||
|
|
||||||
|
suspend_interfaces() {
|
||||||
|
# Stop NetworkManager before suspend
|
||||||
|
${NM_DAEMON} stop
|
||||||
|
|
||||||
|
# Suspend wireless interfaces
|
||||||
|
if [ -d "/proc/device-tree/wireless" ]; then
|
||||||
|
for i in $(sed -ne 's,^\(wlan[0-9]\)=.*,\1,g;T;p' /var/run/ifstate | sort -r); do
|
||||||
|
ifdown "${i}" && RESUME_IFACES="${RESUME_IFACES:+${RESUME_IFACES} }${i}"
|
||||||
|
done
|
||||||
|
grep -qs '^wlan' /proc/modules && rmmod wlan
|
||||||
|
fi
|
||||||
|
|
||||||
|
# Suspend bluetooth interface
|
||||||
|
if [ -d "/proc/device-tree/bluetooth" ]; then
|
||||||
|
hciconfig hci0 2>&1 | grep -qs UP && up_bt_on_resume="1"
|
||||||
|
${BT_DAEMON} stop >/dev/null
|
||||||
|
${BT_INIT} stop >/dev/null
|
||||||
|
fi
|
||||||
|
}
|
||||||
|
|
||||||
|
resume_interfaces() {
|
||||||
|
# Resume wireless interfaces
|
||||||
|
if [ -d "/proc/device-tree/wireless" ]; then
|
||||||
|
# Trigger wireless module loading event, and wait until the interface exists
|
||||||
|
udevadm trigger --action=add --attr-match="modalias=pci:v0000168Cd0000003Esv*sd*bc*sc*i*"
|
||||||
|
timeout -t 5 sh -c "while [ ! -d /sys/class/net/wlan0 ]; do sleep .2; done" 2>/dev/null
|
||||||
|
|
||||||
|
# Bring up the interfaces that were bring down on suspend
|
||||||
|
for i in $(echo ${RESUME_IFACES} | tr ' ' '\n' | sort); do
|
||||||
|
grep -qs "^${i}" /var/run/ifstate || ifup "${i}"
|
||||||
|
done
|
||||||
|
fi
|
||||||
|
|
||||||
|
# Resume NetworkManager after suspend
|
||||||
|
${NM_DAEMON} start
|
||||||
|
|
||||||
|
# Resume bluetooth interface
|
||||||
|
if [ -d "/proc/device-tree/bluetooth" ]; then
|
||||||
|
if [ -n "${up_bt_on_resume}" ]; then
|
||||||
|
${BT_INIT} start >/dev/null
|
||||||
|
${BT_DAEMON} start >/dev/null
|
||||||
|
fi
|
||||||
|
fi
|
||||||
|
}
|
||||||
|
|
||||||
|
enter_critical_section() {
|
||||||
|
# Create lock file
|
||||||
|
eval "exec ${lockfd}>${lockfile}"
|
||||||
|
|
||||||
|
# Acquire the lock in non blocking mode. Otherwise, additional calls
|
||||||
|
# to the script will be queued and the system will endlessly go in
|
||||||
|
# and out of suspend to ram
|
||||||
|
flock -n "${lockfd}" || exit 0
|
||||||
|
}
|
||||||
|
|
||||||
|
exit_critical_section() {
|
||||||
|
# Release the lock
|
||||||
|
flock -u "${lockfd}"
|
||||||
|
}
|
||||||
|
|
||||||
|
while getopts "h" c; do
|
||||||
|
case "${c}" in
|
||||||
|
h) usage; exit;;
|
||||||
|
esac
|
||||||
|
done
|
||||||
|
|
||||||
|
if [ -f "${syspower}" ]; then
|
||||||
|
# Avoid running multiple instances of this script in parallel
|
||||||
|
enter_critical_section
|
||||||
|
|
||||||
|
# Pre-suspend actions
|
||||||
|
suspend_interfaces
|
||||||
|
|
||||||
|
# Suspend the device
|
||||||
|
printf "freeze" > ${syspower}
|
||||||
|
|
||||||
|
# Post-resume actions
|
||||||
|
resume_interfaces
|
||||||
|
|
||||||
|
exit_critical_section
|
||||||
|
else
|
||||||
|
printf "\n[ERROR] File ${syspower} not found\n\n"
|
||||||
|
fi
|
||||||
|
|
@ -5,7 +5,7 @@ DESCRIPTION = "DEY image with QT graphical libraries"
|
||||||
LICENSE = "MIT"
|
LICENSE = "MIT"
|
||||||
|
|
||||||
SOC_PACKAGES = ""
|
SOC_PACKAGES = ""
|
||||||
SOC_PACKAGES_ccimx6 = "imx-gpu-viv-demos imx-gpu-viv-tools"
|
SOC_PACKAGES_imxgpu2d = "imx-gpu-viv-demos imx-gpu-viv-tools"
|
||||||
|
|
||||||
IMAGE_INSTALL = " \
|
IMAGE_INSTALL = " \
|
||||||
packagegroup-dey-core \
|
packagegroup-dey-core \
|
||||||
|
|
@ -19,7 +19,9 @@ IMAGE_FEATURES += " \
|
||||||
eclipse-debug \
|
eclipse-debug \
|
||||||
package-management \
|
package-management \
|
||||||
ssh-server-dropbear \
|
ssh-server-dropbear \
|
||||||
${@bb.utils.contains('DISTRO_FEATURES', 'x11', 'x11-base x11-sato', '', d)} \
|
${@bb.utils.contains('DISTRO_FEATURES', 'wayland', '', \
|
||||||
|
bb.utils.contains('DISTRO_FEATURES', 'x11', 'x11-base x11-sato', \
|
||||||
|
'', d), d)} \
|
||||||
${@bb.utils.contains('MACHINE_FEATURES', 'accel-video', 'dey-gstreamer', '', d)} \
|
${@bb.utils.contains('MACHINE_FEATURES', 'accel-video', 'dey-gstreamer', '', d)} \
|
||||||
${@bb.utils.contains('MACHINE_FEATURES', 'alsa', 'dey-audio', '', d)} \
|
${@bb.utils.contains('MACHINE_FEATURES', 'alsa', 'dey-audio', '', d)} \
|
||||||
${@bb.utils.contains('MACHINE_FEATURES', 'bluetooth', 'dey-bluetooth', '', d)} \
|
${@bb.utils.contains('MACHINE_FEATURES', 'bluetooth', 'dey-bluetooth', '', d)} \
|
||||||
|
|
@ -43,7 +45,7 @@ inherit core-image
|
||||||
inherit dey-image
|
inherit dey-image
|
||||||
inherit distro_features_check
|
inherit distro_features_check
|
||||||
|
|
||||||
CONFLICT_DISTRO_FEATURES = "directfb wayland"
|
CONFLICT_DISTRO_FEATURES = "directfb"
|
||||||
|
|
||||||
IMAGE_ROOTFS_SIZE = "8192"
|
IMAGE_ROOTFS_SIZE = "8192"
|
||||||
|
|
||||||
|
|
@ -52,3 +54,8 @@ BAD_RECOMMENDATIONS += "udev-cache"
|
||||||
BAD_RECOMMENDATIONS += "eudev-hwdb"
|
BAD_RECOMMENDATIONS += "eudev-hwdb"
|
||||||
|
|
||||||
export IMAGE_BASENAME = "dey-image-qt-${GRAPHICAL_BACKEND}"
|
export IMAGE_BASENAME = "dey-image-qt-${GRAPHICAL_BACKEND}"
|
||||||
|
|
||||||
|
CORE_IMAGE_EXTRA_INSTALL += " \
|
||||||
|
${@bb.utils.contains('DISTRO_FEATURES', 'wayland', 'weston-init weston-examples gtk+3-demo clutter-1.0-examples', '', d)} \
|
||||||
|
${@bb.utils.contains('DISTRO_FEATURES', 'x11 wayland', 'weston-xwayland xterm', '', d)} \
|
||||||
|
"
|
||||||
|
|
|
||||||
|
|
@ -15,6 +15,7 @@ PACKAGE_INSTALL = " \
|
||||||
|
|
||||||
PACKAGE_INSTALL_append_ccimx6 = " e2fsprogs-mke2fs"
|
PACKAGE_INSTALL_append_ccimx6 = " e2fsprogs-mke2fs"
|
||||||
PACKAGE_INSTALL_append_ccimx6ul = " mtd-utils-ubifs"
|
PACKAGE_INSTALL_append_ccimx6ul = " mtd-utils-ubifs"
|
||||||
|
PACKAGE_INSTALL_append_ccimx8x = " e2fsprogs-mke2fs"
|
||||||
|
|
||||||
# Do not pollute the initrd image with rootfs features
|
# Do not pollute the initrd image with rootfs features
|
||||||
IMAGE_FEATURES = ""
|
IMAGE_FEATURES = ""
|
||||||
|
|
|
||||||
|
|
@ -1,7 +0,0 @@
|
||||||
|
|
||||||
## Example bridge between eth0 and wlan1
|
|
||||||
#auto br0
|
|
||||||
#iface br0 inet static
|
|
||||||
# bridge_ports eth0 wlan1
|
|
||||||
# address 192.168.42.50
|
|
||||||
# netmask 255.255.255.0
|
|
||||||
|
|
@ -1,6 +0,0 @@
|
||||||
|
|
||||||
auto wlan1
|
|
||||||
iface wlan1 inet dhcp
|
|
||||||
udhcpc_opts -S -b >/dev/null &
|
|
||||||
post-up /etc/init.d/hostapd start
|
|
||||||
pre-down /etc/init.d/hostapd stop
|
|
||||||
|
|
@ -1,9 +0,0 @@
|
||||||
|
|
||||||
auto wlan1
|
|
||||||
iface wlan1 inet static
|
|
||||||
address ##WLAN1_STATIC_IP##
|
|
||||||
netmask ##WLAN1_STATIC_NETMASK##
|
|
||||||
gateway ##WLAN1_STATIC_GATEWAY##
|
|
||||||
dns-nameservers ##WLAN1_STATIC_DNS##
|
|
||||||
post-up /etc/init.d/hostapd start
|
|
||||||
pre-down /etc/init.d/hostapd stop
|
|
||||||
|
|
@ -1,30 +0,0 @@
|
||||||
#!/bin/sh
|
|
||||||
#
|
|
||||||
# Copyright (c) 2017, Digi International Inc.
|
|
||||||
#
|
|
||||||
# This Source Code Form is subject to the terms of the Mozilla Public
|
|
||||||
# License, v. 2.0. If a copy of the MPL was not distributed with this
|
|
||||||
# file, you can obtain one at http://mozilla.org/MPL/2.0/.
|
|
||||||
#
|
|
||||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
|
||||||
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
|
||||||
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
|
||||||
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
|
||||||
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
|
||||||
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
|
||||||
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
|
||||||
#
|
|
||||||
|
|
||||||
# This will create a second wireless network device
|
|
||||||
if [ -s "/proc/device-tree/wireless/mac-address1" ] &&
|
|
||||||
[ -s "/proc/device-tree/wireless/mac-address2" ] &&
|
|
||||||
[ -s "/proc/device-tree/wireless/mac-address3" ]; then
|
|
||||||
:
|
|
||||||
else
|
|
||||||
echo "[WARN] Using default MAC addresses for virtual interfaces, please program them referring to the Digi U-Boot Documentation"
|
|
||||||
fi
|
|
||||||
|
|
||||||
if [ ! -d "/sys/class/net/wlan1" ]; then
|
|
||||||
# This will create a second wireless network device
|
|
||||||
iw dev wlan0 interface add wlan1 type __ap
|
|
||||||
fi
|
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
# Copyright (C) 2013-2017 Digi International Inc.
|
# Copyright (C) 2013-2018 Digi International Inc.
|
||||||
|
|
||||||
FILESEXTRAPATHS_prepend := "${THISDIR}/${BP}:"
|
FILESEXTRAPATHS_prepend := "${THISDIR}/${BP}:"
|
||||||
|
|
||||||
|
|
@ -23,6 +23,12 @@ SRC_URI_append_ccimx6ul = "\
|
||||||
file://virtwlans.sh \
|
file://virtwlans.sh \
|
||||||
"
|
"
|
||||||
|
|
||||||
|
SRC_URI_append_ccimx8x = "\
|
||||||
|
file://interfaces.wlan1.static \
|
||||||
|
file://interfaces.wlan1.dhcp \
|
||||||
|
file://virtwlans.sh \
|
||||||
|
"
|
||||||
|
|
||||||
WPA_DRIVER ?= "nl80211"
|
WPA_DRIVER ?= "nl80211"
|
||||||
|
|
||||||
do_install_append() {
|
do_install_append() {
|
||||||
|
|
@ -49,54 +55,46 @@ do_install_append() {
|
||||||
sed -i -e "s,##P2P0_STATIC_GATEWAY##,${P2P0_STATIC_GATEWAY},g" ${D}${sysconfdir}/network/interfaces
|
sed -i -e "s,##P2P0_STATIC_GATEWAY##,${P2P0_STATIC_GATEWAY},g" ${D}${sysconfdir}/network/interfaces
|
||||||
sed -i -e "s,##P2P0_STATIC_DNS##,${P2P0_STATIC_DNS},g" ${D}${sysconfdir}/network/interfaces
|
sed -i -e "s,##P2P0_STATIC_DNS##,${P2P0_STATIC_DNS},g" ${D}${sysconfdir}/network/interfaces
|
||||||
sed -i -e "s,##WPA_DRIVER##,${WPA_DRIVER},g" ${D}${sysconfdir}/network/interfaces
|
sed -i -e "s,##WPA_DRIVER##,${WPA_DRIVER},g" ${D}${sysconfdir}/network/interfaces
|
||||||
|
|
||||||
|
cat ${WORKDIR}/interfaces.br0.example >> ${D}${sysconfdir}/network/interfaces
|
||||||
}
|
}
|
||||||
|
|
||||||
do_install_append_ccimx6sbc() {
|
install_virtwlans() {
|
||||||
cat ${WORKDIR}/interfaces.br0.example >> ${D}${sysconfdir}/network/interfaces
|
install -d ${D}${base_bindir}
|
||||||
|
install -m 0755 ${WORKDIR}/virtwlans.sh ${D}${base_bindir}
|
||||||
|
}
|
||||||
|
|
||||||
|
install_wlan1() {
|
||||||
|
if [ -n "${HAVE_WIFI}" ]; then
|
||||||
|
cat ${WORKDIR}/interfaces.wlan1.${WLAN1_MODE} >> ${D}${sysconfdir}/network/interfaces
|
||||||
|
fi
|
||||||
|
|
||||||
|
# Remove config entries if corresponding variable is not defined
|
||||||
|
[ -z "${WLAN1_STATIC_DNS}" ] && sed -i -e "/##WLAN1_STATIC_DNS##/d" ${D}${sysconfdir}/network/interfaces
|
||||||
|
[ -z "${WLAN1_STATIC_GATEWAY}" ] && sed -i -e "/##WLAN1_STATIC_GATEWAY##/d" ${D}${sysconfdir}/network/interfaces
|
||||||
|
[ -z "${WLAN1_STATIC_IP}" ] && sed -i -e "/##WLAN1_STATIC_IP##/d" ${D}${sysconfdir}/network/interfaces
|
||||||
|
[ -z "${WLAN1_STATIC_NETMASK}" ] && sed -i -e "/##WLAN1_STATIC_NETMASK##/d" ${D}${sysconfdir}/network/interfaces
|
||||||
|
|
||||||
|
# Replace interface parameters
|
||||||
|
sed -i -e "s,##WLAN1_STATIC_IP##,${WLAN1_STATIC_IP},g" ${D}${sysconfdir}/network/interfaces
|
||||||
|
sed -i -e "s,##WLAN1_STATIC_NETMASK##,${WLAN1_STATIC_NETMASK},g" ${D}${sysconfdir}/network/interfaces
|
||||||
|
sed -i -e "s,##WLAN1_STATIC_GATEWAY##,${WLAN1_STATIC_GATEWAY},g" ${D}${sysconfdir}/network/interfaces
|
||||||
|
sed -i -e "s,##WLAN1_STATIC_DNS##,${WLAN1_STATIC_DNS},g" ${D}${sysconfdir}/network/interfaces
|
||||||
}
|
}
|
||||||
|
|
||||||
do_install_append_ccimx6qpsbc() {
|
do_install_append_ccimx6qpsbc() {
|
||||||
install -d ${D}${base_bindir}
|
install_virtwlans
|
||||||
install -m 0755 ${WORKDIR}/virtwlans.sh ${D}${base_bindir}
|
install_wlan1
|
||||||
if [ -n "${HAVE_WIFI}" ]; then
|
|
||||||
cat ${WORKDIR}/interfaces.wlan1.${WLAN1_MODE} >> ${D}${sysconfdir}/network/interfaces
|
|
||||||
fi
|
|
||||||
|
|
||||||
# Remove config entries if corresponding variable is not defined
|
|
||||||
[ -z "${WLAN1_STATIC_DNS}" ] && sed -i -e "/##WLAN1_STATIC_DNS##/d" ${D}${sysconfdir}/network/interfaces
|
|
||||||
[ -z "${WLAN1_STATIC_GATEWAY}" ] && sed -i -e "/##WLAN1_STATIC_GATEWAY##/d" ${D}${sysconfdir}/network/interfaces
|
|
||||||
[ -z "${WLAN1_STATIC_IP}" ] && sed -i -e "/##WLAN1_STATIC_IP##/d" ${D}${sysconfdir}/network/interfaces
|
|
||||||
[ -z "${WLAN1_STATIC_NETMASK}" ] && sed -i -e "/##WLAN1_STATIC_NETMASK##/d" ${D}${sysconfdir}/network/interfaces
|
|
||||||
|
|
||||||
# Replace interface parameters
|
|
||||||
sed -i -e "s,##WLAN1_STATIC_IP##,${WLAN1_STATIC_IP},g" ${D}${sysconfdir}/network/interfaces
|
|
||||||
sed -i -e "s,##WLAN1_STATIC_NETMASK##,${WLAN1_STATIC_NETMASK},g" ${D}${sysconfdir}/network/interfaces
|
|
||||||
sed -i -e "s,##WLAN1_STATIC_GATEWAY##,${WLAN1_STATIC_GATEWAY},g" ${D}${sysconfdir}/network/interfaces
|
|
||||||
sed -i -e "s,##WLAN1_STATIC_DNS##,${WLAN1_STATIC_DNS},g" ${D}${sysconfdir}/network/interfaces
|
|
||||||
|
|
||||||
cat ${WORKDIR}/interfaces.br0.example >> ${D}${sysconfdir}/network/interfaces
|
|
||||||
}
|
}
|
||||||
|
|
||||||
do_install_append_ccimx6ul() {
|
do_install_append_ccimx6ul() {
|
||||||
install -d ${D}${base_bindir}
|
install_virtwlans
|
||||||
install -m 0755 ${WORKDIR}/virtwlans.sh ${D}${base_bindir}
|
install_wlan1
|
||||||
if [ -n "${HAVE_WIFI}" ]; then
|
}
|
||||||
cat ${WORKDIR}/interfaces.wlan1.${WLAN1_MODE} >> ${D}${sysconfdir}/network/interfaces
|
|
||||||
fi
|
|
||||||
|
|
||||||
# Remove config entries if corresponding variable is not defined
|
do_install_append_ccimx8x() {
|
||||||
[ -z "${WLAN1_STATIC_DNS}" ] && sed -i -e "/##WLAN1_STATIC_DNS##/d" ${D}${sysconfdir}/network/interfaces
|
install_virtwlans
|
||||||
[ -z "${WLAN1_STATIC_GATEWAY}" ] && sed -i -e "/##WLAN1_STATIC_GATEWAY##/d" ${D}${sysconfdir}/network/interfaces
|
install_wlan1
|
||||||
[ -z "${WLAN1_STATIC_IP}" ] && sed -i -e "/##WLAN1_STATIC_IP##/d" ${D}${sysconfdir}/network/interfaces
|
|
||||||
[ -z "${WLAN1_STATIC_NETMASK}" ] && sed -i -e "/##WLAN1_STATIC_NETMASK##/d" ${D}${sysconfdir}/network/interfaces
|
|
||||||
|
|
||||||
# Replace interface parameters
|
|
||||||
sed -i -e "s,##WLAN1_STATIC_IP##,${WLAN1_STATIC_IP},g" ${D}${sysconfdir}/network/interfaces
|
|
||||||
sed -i -e "s,##WLAN1_STATIC_NETMASK##,${WLAN1_STATIC_NETMASK},g" ${D}${sysconfdir}/network/interfaces
|
|
||||||
sed -i -e "s,##WLAN1_STATIC_GATEWAY##,${WLAN1_STATIC_GATEWAY},g" ${D}${sysconfdir}/network/interfaces
|
|
||||||
sed -i -e "s,##WLAN1_STATIC_DNS##,${WLAN1_STATIC_DNS},g" ${D}${sysconfdir}/network/interfaces
|
|
||||||
|
|
||||||
cat ${WORKDIR}/interfaces.br0.example >> ${D}${sysconfdir}/network/interfaces
|
|
||||||
}
|
}
|
||||||
|
|
||||||
# Disable wireless interfaces on first boot for non-wireless variants
|
# Disable wireless interfaces on first boot for non-wireless variants
|
||||||
|
|
|
||||||
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Reference in New Issue