Digi
/
meta-digi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

imx-system-manager: add patches to expose regulators to Linux 

This series of patches expose a number of regulators of
the PMIC to the non-secure world, so that they can be
referenced and used by Linux drivers.

Signed-off-by: Hector Palacios <hector.palacios@digi.com>
This commit is contained in:
Hector Palacios 2025-10-13 16:27:52 +02:00
parent b3a84b1d4e
commit bf87d0df25
4 changed files with 361 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

274
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0009-ccimx95-change-names-of-voltage-regulators.patch Normal file
View File

@ -0,0 +1,274 @@
From: Hector Palacios <hector.palacios@digi.com>
Date: Mon, 29 Sep 2025 13:02:02 +0200
Subject: [PATCH 09/11] ccimx95: change names of voltage regulators
Change the names of voltage regulators for easier identification.
Use the PMIC regulator (SW1, SW2, LDO1...) and then the name of the power
rail used in the SOM.
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
boards/ccimx95dvk/sm/brd_sm_voltage.c | 85 ++++++++++++++-------------
boards/ccimx95dvk/sm/brd_sm_voltage.h | 15 ++---
2 files changed, 51 insertions(+), 49 deletions(-)
diff --git a/boards/ccimx95dvk/sm/brd_sm_voltage.c b/boards/ccimx95dvk/sm/brd_sm_voltage.c
index b81ffd970294..d7e7c9b3ea27 100755
--- a/boards/ccimx95dvk/sm/brd_sm_voltage.c
+++ b/boards/ccimx95dvk/sm/brd_sm_voltage.c
@@ -2,6 +2,7 @@
** ###################################################################
**
** Copyright 2023-2025 NXP
+** Copyright 2025 Digi International Inc.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
@@ -63,13 +64,13 @@ int32_t BRD_SM_VoltageNameGet(uint32_t domainId, string *voltNameAddr,
static string const s_name[BRD_SM_NUM_VOLT] =
{
- "vdd_gpio_3p3",
- "vdd_ana_0p8",
- "vdd_gpio_1p8",
- "vddq_ddr",
- "vdd2_ddr",
- "sd_card",
- "nvcc_sd2"
+ "vdd_3v3",
+ "vdd_ana_0v8",
+ "vdd_1v8",
+ "lpd5_vddq",
+ "lpd5_vdd2",
+ "vdd_ldo1",
+ "vdd_sdio2"
};
/* Get max string width */
@@ -117,25 +118,25 @@ int32_t BRD_SM_VoltageDescribe(uint32_t domainId,
case DEV_SM_VOLT_ARM:
status = DEV_SM_VoltageDescribe(domainId, range);
break;
- case BRD_SM_VOLT_VDD_GPIO_3P3:
+ case BRD_SM_VOLT_SW1_VDD_3V3:
rc = PF09_RegulatorInfoGet(PF09_REG_SW1, &info);
break;
- case BRD_SM_VOLT_VDD_ANA_0P8:
+ case BRD_SM_VOLT_SW2_VDD_ANA_0V8:
rc = PF09_RegulatorInfoGet(PF09_REG_SW2, &info);
break;
- case BRD_SM_VOLT_VDD_GPIO_1P8:
+ case BRD_SM_VOLT_SW3_VDD_1V8:
rc = PF09_RegulatorInfoGet(PF09_REG_SW3, &info);
break;
- case BRD_SM_VOLT_VDDQ_DDR:
+ case BRD_SM_VOLT_SW4_LPD5_VDDQ:
rc = PF09_RegulatorInfoGet(PF09_REG_SW4, &info);
break;
- case BRD_SM_VOLT_VDD2_DDR:
+ case BRD_SM_VOLT_SW5_LPD5_VDD2:
rc = PF09_RegulatorInfoGet(PF09_REG_SW5, &info);
break;
- case BRD_SM_VOLT_SD_CARD:
+ case BRD_SM_VOLT_LDO1_VDD_LDO1:
rc = PF09_RegulatorInfoGet(PF09_REG_LDO1, &info);
break;
- case BRD_SM_VOLT_NVCC_SD2:
+ case BRD_SM_VOLT_LDO2_VDD_SDIO2:
rc = PF09_RegulatorInfoGet(PF09_REG_LDO2, &info);
break;
default:
@@ -206,31 +207,31 @@ int32_t BRD_SM_VoltageModeSet(uint32_t domainId, uint8_t voltMode)
s_modeArm = voltMode;
}
break;
- case BRD_SM_VOLT_VDD_GPIO_3P3:
+ case BRD_SM_VOLT_SW1_VDD_3V3:
rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
mode);
break;
- case BRD_SM_VOLT_VDD_ANA_0P8:
+ case BRD_SM_VOLT_SW2_VDD_ANA_0V8:
rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
mode);
break;
- case BRD_SM_VOLT_VDD_GPIO_1P8:
+ case BRD_SM_VOLT_SW3_VDD_1V8:
rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
mode);
break;
- case BRD_SM_VOLT_VDDQ_DDR:
+ case BRD_SM_VOLT_SW4_LPD5_VDDQ:
rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
mode);
break;
- case BRD_SM_VOLT_VDD2_DDR:
+ case BRD_SM_VOLT_SW5_LPD5_VDD2:
rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
mode);
break;
- case BRD_SM_VOLT_SD_CARD:
+ case BRD_SM_VOLT_LDO1_VDD_LDO1:
rc = PF09_LdoEnable(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
enable);
break;
- case BRD_SM_VOLT_NVCC_SD2:
+ case BRD_SM_VOLT_LDO2_VDD_SDIO2:
rc = PF09_LdoEnable(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
enable);
break;
@@ -271,36 +272,36 @@ int32_t BRD_SM_VoltageModeGet(uint32_t domainId, uint8_t *voltMode)
rc = PF09_GpioCtrlGet(&g_pf09Dev, PF09_GPIO4, PF53_STATE_VRUN,
&enable);
break;
- case BRD_SM_VOLT_VDD_GPIO_3P3:
+ case BRD_SM_VOLT_SW1_VDD_3V3:
rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
&mode);
enable = (mode != PF09_SW_MODE_OFF);
break;
- case BRD_SM_VOLT_VDD_ANA_0P8:
+ case BRD_SM_VOLT_SW2_VDD_ANA_0V8:
rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
&mode);
enable = (mode != PF09_SW_MODE_OFF);
break;
- case BRD_SM_VOLT_VDD_GPIO_1P8:
+ case BRD_SM_VOLT_SW3_VDD_1V8:
rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
&mode);
enable = (mode != PF09_SW_MODE_OFF);
break;
- case BRD_SM_VOLT_VDDQ_DDR:
+ case BRD_SM_VOLT_SW4_LPD5_VDDQ:
rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
&mode);
enable = (mode != PF09_SW_MODE_OFF);
break;
- case BRD_SM_VOLT_VDD2_DDR:
+ case BRD_SM_VOLT_SW5_LPD5_VDD2:
rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
&mode);
enable = (mode != PF09_SW_MODE_OFF);
break;
- case BRD_SM_VOLT_SD_CARD:
+ case BRD_SM_VOLT_LDO1_VDD_LDO1:
rc = PF09_LdoIsEnabled(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
&enable);
break;
- case BRD_SM_VOLT_NVCC_SD2:
+ case BRD_SM_VOLT_LDO2_VDD_SDIO2:
rc = PF09_LdoIsEnabled(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
&enable);
break;
@@ -359,31 +360,31 @@ int32_t BRD_SM_VoltageLevelSet(uint32_t domainId, int32_t voltageLevel)
s_levelArm = (int32_t) level;
rc = true;
break;
- case BRD_SM_VOLT_VDD_GPIO_3P3:
+ case BRD_SM_VOLT_SW1_VDD_3V3:
rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
level);
break;
- case BRD_SM_VOLT_VDD_ANA_0P8:
+ case BRD_SM_VOLT_SW2_VDD_ANA_0V8:
rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
level);
break;
- case BRD_SM_VOLT_VDD_GPIO_1P8:
+ case BRD_SM_VOLT_SW3_VDD_1V8:
rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
level);
break;
- case BRD_SM_VOLT_VDDQ_DDR:
+ case BRD_SM_VOLT_SW4_LPD5_VDDQ:
rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
level);
break;
- case BRD_SM_VOLT_VDD2_DDR:
+ case BRD_SM_VOLT_SW5_LPD5_VDD2:
rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
level);
break;
- case BRD_SM_VOLT_SD_CARD:
+ case BRD_SM_VOLT_LDO1_VDD_LDO1:
rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
level);
break;
- case BRD_SM_VOLT_NVCC_SD2:
+ case BRD_SM_VOLT_LDO2_VDD_SDIO2:
rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
level);
break;
@@ -458,31 +459,31 @@ int32_t BRD_SM_VoltageLevelGet(uint32_t domainId, int32_t *voltageLevel)
}
}
break;
- case BRD_SM_VOLT_VDD_GPIO_3P3:
+ case BRD_SM_VOLT_SW1_VDD_3V3:
rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
&level);
break;
- case BRD_SM_VOLT_VDD_ANA_0P8:
+ case BRD_SM_VOLT_SW2_VDD_ANA_0V8:
rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
&level);
break;
- case BRD_SM_VOLT_VDD_GPIO_1P8:
+ case BRD_SM_VOLT_SW3_VDD_1V8:
rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
&level);
break;
- case BRD_SM_VOLT_VDDQ_DDR:
+ case BRD_SM_VOLT_SW4_LPD5_VDDQ:
rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
&level);
break;
- case BRD_SM_VOLT_VDD2_DDR:
+ case BRD_SM_VOLT_SW5_LPD5_VDD2:
rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
&level);
break;
- case BRD_SM_VOLT_SD_CARD:
+ case BRD_SM_VOLT_LDO1_VDD_LDO1:
rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
&level);
break;
- case BRD_SM_VOLT_NVCC_SD2:
+ case BRD_SM_VOLT_LDO2_VDD_SDIO2:
rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
&level);
break;
diff --git a/boards/ccimx95dvk/sm/brd_sm_voltage.h b/boards/ccimx95dvk/sm/brd_sm_voltage.h
index 6c9e01286e7e..46ddc9d89096 100755
--- a/boards/ccimx95dvk/sm/brd_sm_voltage.h
+++ b/boards/ccimx95dvk/sm/brd_sm_voltage.h
@@ -2,6 +2,7 @@
** ###################################################################
**
** Copyright 2023-2024 NXP
+** Copyright 2025 Digi International Inc.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
@@ -76,13 +77,13 @@
* @name BRD_SM voltage domains
*/
/** @{ */
-#define BRD_SM_VOLT_VDD_GPIO_3P3 (DEV_SM_NUM_VOLT + 0U) /*!< VDD GPIO 3.3v */
-#define BRD_SM_VOLT_VDD_ANA_0P8 (DEV_SM_NUM_VOLT + 1U) /*!< VDD ANA 0.8v */
-#define BRD_SM_VOLT_VDD_GPIO_1P8 (DEV_SM_NUM_VOLT + 2U) /*!< VDD GPIO 1.8v */
-#define BRD_SM_VOLT_VDDQ_DDR (DEV_SM_NUM_VOLT + 3U) /*!< DDR VDDQ */
-#define BRD_SM_VOLT_VDD2_DDR (DEV_SM_NUM_VOLT + 4U) /*!< DDR VDD2 */
-#define BRD_SM_VOLT_SD_CARD (DEV_SM_NUM_VOLT + 5U) /*!< SD1 */
-#define BRD_SM_VOLT_NVCC_SD2 (DEV_SM_NUM_VOLT + 6U) /*!< SD2 */
+#define BRD_SM_VOLT_SW1_VDD_3V3 (DEV_SM_NUM_VOLT + 0U) /*!< VDD 3V3 */
+#define BRD_SM_VOLT_SW2_VDD_ANA_0V8 (DEV_SM_NUM_VOLT + 1U) /*!< VDD ANA 0V8 */
+#define BRD_SM_VOLT_SW3_VDD_1V8 (DEV_SM_NUM_VOLT + 2U) /*!< VDD 1V8 */
+#define BRD_SM_VOLT_SW4_LPD5_VDDQ (DEV_SM_NUM_VOLT + 3U) /*!< DDR VDDQ */
+#define BRD_SM_VOLT_SW5_LPD5_VDD2 (DEV_SM_NUM_VOLT + 4U) /*!< DDR VDD2 */
+#define BRD_SM_VOLT_LDO1_VDD_LDO1 (DEV_SM_NUM_VOLT + 5U) /*!< LDO1 */
+#define BRD_SM_VOLT_LDO2_VDD_SDIO2 (DEV_SM_NUM_VOLT + 6U) /*!< LDO2 (VDD_SDIO2) */
/** @} */
/* Types */

47
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0010-ccimx95dvk-enable-full-access-to-certain-regulators-.patch Normal file
View File

@ -0,0 +1,47 @@
From: Hector Palacios <hector.palacios@digi.com>
Date: Thu, 9 Oct 2025 13:16:00 +0200
Subject: [PATCH 10/11] ccimx95dvk: enable full access to certain regulators
from non-secure LVM
The following PMIC regulators are used by the DVK:
- VDD_3V3 (SW1)
- VDD_1V8 (SW3)
- VDD_LDO1 (LDO1)
- VDD_SDIO2 (LDO2)
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
configs/ccimx95dvk.cfg | 4 ++++
configs/ccimx95dvk/config_scmi.h | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
index b324e0fb0e45..b7c33f8d7e9a 100755
--- a/configs/ccimx95dvk.cfg
+++ b/configs/ccimx95dvk.cfg
@@ -532,6 +532,10 @@ AUDIO_PLL2 ALL
BRD_SM_SENSOR_TEMP_PF09 ALL
BRD_SM_SENSOR_TEMP_PF5301 SET
BRD_SM_SENSOR_TEMP_PF5302 SET
+BRD_SM_VOLT_SW1_VDD_3V3 ALL
+BRD_SM_VOLT_SW3_VDD_1V8 ALL
+BRD_SM_VOLT_LDO1_VDD_LDO1 ALL
+BRD_SM_VOLT_LDO2_VDD_SDIO2 ALL
BUTTON ALL, test
CLOCK_DISP1PIX ALL
CLOCK_DISP2PIX ALL
diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
index b23958f33138..18a4e5ef6360 100644
--- a/configs/ccimx95dvk/config_scmi.h
+++ b/configs/ccimx95dvk/config_scmi.h
@@ -610,6 +610,10 @@
.sensorPerms[DEV_SM_SENSOR_TEMP_A55] = SM_SCMI_PERM_ALL, \
.sensorPerms[DEV_SM_SENSOR_TEMP_ANA] = SM_SCMI_PERM_SET, \
.sysPerms = SM_SCMI_PERM_NOTIFY, \
+ .voltPerms[BRD_SM_VOLT_LDO1_VDD_LDO1] = SM_SCMI_PERM_ALL, \
+ .voltPerms[BRD_SM_VOLT_LDO2_VDD_SDIO2] = SM_SCMI_PERM_ALL, \
+ .voltPerms[BRD_SM_VOLT_SW1_VDD_3V3] = SM_SCMI_PERM_ALL, \
+ .voltPerms[BRD_SM_VOLT_SW3_VDD_1V8] = SM_SCMI_PERM_ALL, \
}
/*! Config for SCMI channel 5 */

37
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0011-components-pf09-reduce-LDOs-step-to-50mV.patch Normal file
View File

@ -0,0 +1,37 @@
From: Hector Palacios <hector.palacios@digi.com>
Date: Mon, 13 Oct 2025 08:49:57 +0200
Subject: [PATCH 11/11] components: pf09: reduce LDOs step to 50mV
The voltage values that can be programmed to the LDOs are not linear.
For low voltages, the step is 50mV, but for higher voltages it is 100mV.
Setting the step as 100mV fools the Linux kernel regulator framework
which does not properly calculate the selector it must call when using
the SCMI regulator framework, resulting in -EINVAL errors.
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
components/pf09/fsl_pf09.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/components/pf09/fsl_pf09.c b/components/pf09/fsl_pf09.c
index 21a0b5557244..3e1887158d7d 100755
--- a/components/pf09/fsl_pf09.c
+++ b/components/pf09/fsl_pf09.c
@@ -528,7 +528,7 @@ bool PF09_RegulatorInfoGet(uint8_t regulator, PF09_RegInfo *regInfo)
/* set min/max/step in microvolts */
regInfo->minV = 750000U;
regInfo->maxV = 3300000U;
- regInfo->stepV = 100000U;
+ regInfo->stepV = 50000U;
}
break;
case PF09_REG_LDO2:
@@ -537,7 +537,7 @@ bool PF09_RegulatorInfoGet(uint8_t regulator, PF09_RegInfo *regInfo)
/* set min/max/step in microvolts */
regInfo->minV = 650000U;
regInfo->maxV = 3300000U;
- regInfo->stepV = 100000U;
+ regInfo->stepV = 50000U;
}
break;
default:

3
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager_1.0.0.bbappend
View File

@ -11,6 +11,9 @@ SRC_URI:append:dey = " \
file://0006-ccimx95dvk-move-CAN1-to-be-used-by-A55.patch \
file://0007-ccimx95dvk-remove-PCAL6408A-IO-expander-from-EVK.patch \
file://0008-ccimx95dvk-remove-PCA2123-RTC-from-EVK.patch \
file://0009-ccimx95-change-names-of-voltage-regulators.patch \
file://0010-ccimx95dvk-enable-full-access-to-certain-regulators-.patch \
file://0011-components-pf09-reduce-LDOs-step-to-50mV.patch \
"
# Disable debug monitor by default