imx-system-manager: add patch with SM fix for 2GiB DDR

The system manager was not reporting (via SCMI) the size for the 2GiB
ram. This patch is a backport of a newer version of the SM.

https://onedigi.atlassian.net/browse/DUB-1117

Signed-off-by: Javier Viguera <javier.viguera@digi.com>

meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0013-ccimx95dvk-change-SM-console-from-LPUART7-to-LPUART2.patch

@@ -1,6 +1,6 @@
 From: Hector Palacios <hector.palacios@digi.com>
 Date: Wed, 14 Jan 2026 16:03:29 +0100
-Subject: [PATCH 13/14] ccimx95dvk: change SM console from LPUART7 to LPUART2
+Subject: [PATCH] ccimx95dvk: change SM console from LPUART7 to LPUART2
 
 On version 2 of the SOM, the SM console has changed to LPUART2.
 

meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0014-ccimx95dvk-PF09-PMIC-interrupt-moved-to-PDM_BIT_STRE.patch

@@ -1,7 +1,6 @@
 From: Hector Palacios <hector.palacios@digi.com>
 Date: Wed, 14 Jan 2026 14:05:57 +0100
-Subject: [PATCH 14/14] ccimx95dvk: PF09 PMIC interrupt moved to
+Subject: [PATCH] ccimx95dvk: PF09 PMIC interrupt moved to PDM_BIT_STREAM1
- PDM_BIT_STREAM1
 
 Upstream-Status: Inappropriate [DEY specific]
 

meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0015-SM-319-Fix-issue-with-one-chip-select-DRAMs.patch

@@ -0,0 +1,57 @@
+From: Chuck Cannon <chuck.cannon@nxp.com>
+Date: Thu, 30 Oct 2025 10:06:57 -0500
+Subject: [PATCH] SM-319: Fix issue with one chip select DRAMs.
+
+Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>
+(cherry picked from commit d6f582baa73046f4167549567781a4ea0df4a9ba)
+Signed-off-by: Javier Viguera <javier.viguera@digi.com>
+
+Upstream-Status: Inappropriate [DEY specific]
+---
+ drivers/ddr/fsl_ddr.c | 15 ++++++++-------
+ 1 file changed, 8 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/ddr/fsl_ddr.c b/drivers/ddr/fsl_ddr.c
+index 1042f6a0ba7c..275af15c0ce7 100644
+--- a/drivers/ddr/fsl_ddr.c
++++ b/drivers/ddr/fsl_ddr.c
+@@ -533,10 +533,10 @@ bool DDR_GetDRAMInfo(const struct ddr_info *ddrp, struct dram_info *info)
+             info->eccEnb = false;
+         }
+ 
+-        /* extract MTS from DDR info */
++        /* Extract MTS from DDR info */
+         info->mts = ddrp->pstate_freq[0];
+ 
+-        /* start address from CS0 bounds (top 12 of 36 bits addr)
++        /* Start address from CS0 bounds (top 12 of 36 bits addr)
+            + DDR AXI start */
+         addr = ((DDRC->CS_BNDS[0].CS_BNDS & DDRC_CS_BNDS_CS_BNDS_SA_MASK)
+             >> DDRC_CS_BNDS_CS_BNDS_SA_SHIFT);
+@@ -544,12 +544,13 @@ bool DDR_GetDRAMInfo(const struct ddr_info *ddrp, struct dram_info *info)
+         info->startAddr <<= 24U;
+         info->startAddr += 0x80000000ULL;
+ 
+-        /* end address from CS0 bounds if Rank interleaving set
++        /* End address from CS0 bounds if Rank interleaving set
+            + DDR AXI start */
+-        if ((DDRC->DDR_SDRAM_CFG & DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_MASK)
+-            != 0U)
++        if (((DDRC->DDR_SDRAM_CFG & DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_MASK)
++            != 0U) || ((DDRC->CS_CONFIG[1] & DDRC_CS_CONFIG_CS_EN_MASK)
++            == 0U))
+         {
+-            /* end address from CS0 bounds if Rank interleaving set
++            /* End address from CS0 bounds if Rank interleaving set
+                + DDR AXI start */
+             addr = ((DDRC->CS_BNDS[0].CS_BNDS
+                 & DDRC_CS_BNDS_CS_BNDS_EA_MASK)
+@@ -557,7 +558,7 @@ bool DDR_GetDRAMInfo(const struct ddr_info *ddrp, struct dram_info *info)
+         }
+         else
+         {
+-            /* end address from CS1 bounds + DDR AXI start */
++            /* End address from CS1 bounds + DDR AXI start */
+             addr = ((DDRC->CS_BNDS[1].CS_BNDS
+                 & DDRC_CS_BNDS_CS_BNDS_EA_MASK)
+                 >> DDRC_CS_BNDS_CS_BNDS_EA_SHIFT);

meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager_2025q3.bbappend

@@ -17,6 +17,7 @@ SRC_URI:append:dey = " \
     file://0012-ccimx95dvk-remove-access-to-VDD_3V3-and-VDD_1V8-from.patch \
     file://0013-ccimx95dvk-change-SM-console-from-LPUART7-to-LPUART2.patch \
     file://0014-ccimx95dvk-PF09-PMIC-interrupt-moved-to-PDM_BIT_STRE.patch \
+    file://0015-SM-319-Fix-issue-with-one-chip-select-DRAMs.patch \
 "
 
 # Disable debug monitor by default