diff --git a/meta-digi-arm/recipes-bsp/imx-mkimage/files/0002-cc8x-add-second-DCD-for-the-2GB-variant-of-the-cc8x.patch b/meta-digi-arm/recipes-bsp/imx-mkimage/files/0002-cc8x-add-second-DCD-for-the-2GB-variant-of-the-cc8x.patch new file mode 100644 index 000000000..00a01d53e --- /dev/null +++ b/meta-digi-arm/recipes-bsp/imx-mkimage/files/0002-cc8x-add-second-DCD-for-the-2GB-variant-of-the-cc8x.patch @@ -0,0 +1,892 @@ +From: Gabriel Valcazar +Date: Fri, 27 Jul 2018 12:50:37 +0200 +Subject: [PATCH 2/2] cc8x: add second DCD for the 2GB variant of the cc8x + +This DCD is the same as the one used for the 1GB variant, but with minor timing +and indexing changes. + +Also, suffix each DCD with their corresponding UBOOT_CONFIG values so the +imx-boot recipe is able to handle them. + +https://jira.digi.com/browse/DEL-6085 + +Signed-off-by: Gabriel Valcazar +--- + iMX8QX/imx8qx_dcd_1.2GHz.cfg | 284 --------------------- + .../imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express1GB | 284 +++++++++++++++++++++ + .../imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express2GB | 284 +++++++++++++++++++++ + 3 files changed, 568 insertions(+), 284 deletions(-) + delete mode 100644 iMX8QX/imx8qx_dcd_1.2GHz.cfg + create mode 100644 iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express1GB + create mode 100644 iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express2GB + +diff --git a/iMX8QX/imx8qx_dcd_1.2GHz.cfg b/iMX8QX/imx8qx_dcd_1.2GHz.cfg +deleted file mode 100644 +index abf0ad8..0000000 +--- a/iMX8QX/imx8qx_dcd_1.2GHz.cfg ++++ /dev/null +@@ -1,284 +0,0 @@ +-#define __ASSEMBLY__ +- +-#include +-#include +- +-/* +- * Device Configuration Data (DCD) +- * +- * Each entry must have the format: +- * Addr-type Address Value +- * +- * where: +- * Addr-type register length (1,2 or 4 bytes) +- * Address absolute address of the register +- * value value to be stored in the register +- */ +- +-#ifndef SCFW_DCD +-/* For 1200MHz DDR, DRC 600MHz operation */ +-DATA 4 0xff190000 0x00000CC8 /* DRC0 bringup */ +-#else +-/* Set the DRC rate to 600MHz, the PHY PLL will double this for the DRAM rate. */ +-uint32_t rate2 = SC_600MHZ; +-pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); +-#endif +- +-DATA 4 0x41C80208 0x1 +-DATA 4 0x41C80040 0xb +-DATA 4 0x41C80204 0x1 +- +-/* DRAM 0 controller configuration begin */ +-DATA 4 DDRC_MSTR_0 0xC1080020 // Set LPDDR4, BL = 16 and active ranks +-DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data +-DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read +-DATA 4 DDRC_RFSHTMG_0 0x0049006C // tREFI, tRFC +-DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us +-DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us +-DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2 +-DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13 +-DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +-DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin +-DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC +-DATA 4 DDRC_DRAMTMG2_0 0x060E1714 // WL, RL, rd2wr, wr2rd +-DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod +-DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp +-DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke +-DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx +-DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx +-DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD +-DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +-DATA 4 DDRC_DRAMTMG14_0 0x00000071 // txsr +-DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT +-DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval +-DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +-DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +-DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +-DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +-DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +-DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +-DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +-DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 +-DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +-DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +-DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +-DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +-DATA 4 DDRC_ADDRMAP6_0 0x0F070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +-DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +-DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +-DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 +- +-DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 +- +-DATA 4 DDRC_PWRCTL_0 0x0000010D +- +-DATA 4 0x41c80208 0x1 +-DATA 4 0x41c80040 0xf +-DATA 4 0x41c80204 0x1 +- +-//------------------------------------------- +-// Configure registers for PHY initialization +-// Timings are computed for 1200MHz DRAM operation +-//-------------------------------------------- +-// Set-up DRAM Configuration Register +-DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +-// Set-up byte and bit swapping registers +-DATA 4 DDR_PHY_PGCR8_0 0x0001000A +-DATA 4 DDR_PHY_DX0DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping +-DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping +-DATA 4 DDR_PHY_DX1DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping +-DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping +-DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping +-DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping +-DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping +-DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping +-DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +-DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +-// Set-up PHY General Configuration Register +-// PGCR1,4,5,6,7 are untouched +-SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1 +-DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) +-DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD +-DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +-// Set-up PHY Timing Register +-// PTR2 is untouched +-DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST +-DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST +-// Set-up PLL Control Register +-DATA 4 DDR_PHY_PLLCR0_0 0x001C0000 +-DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000 +-// Set-up Impedance Control Register +-DATA 4 DDR_PHY_ZQCR_0 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +-// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +-DATA 4 DDR_PHY_ZQ0PR0_0 0x1BBBB // Optimal setting based on factory testing +-DATA 4 DDR_PHY_ZQ1PR0_0 0x1B9BB // Optimal setting based on factory testing +-// Set-up PHY Initialization Register +-DATA 4 DDR_PHY_PIR_0 0x32 +-// Launch initialization (set bit 0) +-DATA 4 DDR_PHY_PIR_0 0x33 +- +- +-//------------------------------------------- +-// Configure registers for DRAM initialization +-//------------------------------------------- +-// Set-up Mode Register +-// MR0, MR3, MR4, MR5 MR6 are untouched +-DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST +-DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL +-DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength +- +-DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT +-DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +-/* LPDDR4 mode register writes for CA and DQ VREF settings */ +-DATA 4 DDR_PHY_MR12_0 0x48 +-DATA 4 DDR_PHY_MR14_0 0x48 +-// Set-up DRAM Timing Parameters Register +-// DTPR6 is untouched +-DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP +-DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD +-DATA 4 DDR_PHY_DTPR2_0 0x006960E2 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +-DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK) +-DATA 4 DDR_PHY_DTPR4_0 0x00D82B0C // tRFC, tWLO, tXP +-DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR +-// Set-up PHY Timing Register +-DATA 4 DDR_PHY_PTR3_0 0x00249F00 // tDINIT0 +-DATA 4 DDR_PHY_PTR4_0 0x00000960 // tDINIT1 +-DATA 4 DDR_PHY_PTR5_0 0x0003A980 // tDINIT2 +-DATA 4 DDR_PHY_PTR6_0 0x027004B0 // tDINIT4, tDINIT3 +- +- +-// Set-up ODT Configuration Register +-// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +-DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +-DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +-DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +-DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +- +- +-// Set-up AC I/O Configuration Register +-// ACIOCR1-4 are untouched +-DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +-DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +-// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +-DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +-// Set-up VREF Training Control Registers +-DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +-DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0 +-// Set-up DATX8 General Configuration Registers +-// DXnGCR0-4 are untouched +-SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +-DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +-// Set-up DATX8 General Configuration Registers +-DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +-DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +-DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +-DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +-DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +-DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +-DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +-DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +-// Set-up DATX8 DX Control Register 2 +-// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +-DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400 +-// Set-up DATX8 IO Control Register +-DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 +- +-#if DDR_TRAIN_IN_DCD +-// Wait PHY initialization end then launch DRAM initialization +-// Wait for bit 0 of PGSR0 to be '1' +-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured +- +-// Launch DRAM 0 initialization (set bit 0) +-DATA 4 DDR_PHY_PIR_0 0x180 +-DATA 4 DDR_PHY_PIR_0 0x181 +- +-// DRAM 0 initialization end +-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 +- +-// Launch a second time DRAM initialization due to following Synopsys PHY bug: +-// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +-// Workaround: "Run DRAM Initialization twice" +-DATA 4 DDR_PHY_PIR_0 0x100 +-DATA 4 DDR_PHY_PIR_0 0x101 +- +-// Wait (second time) DRAM 0 initialization end +-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 +- +-//---------------------------------------------------------------// +-// DATA training +-//---------------------------------------------------------------// +-// configure PHY for data training +-// The following register writes are recommended by SNPS prior to running training +-CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +-SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +-CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +-SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +-// Per SNPS initialize BIST registers for VREF training +-DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +-DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +-DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) +- +-// Set-up Data Training Configuration Register +-// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys +-// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +-// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED). +-DATA 4 DDR_PHY_DTCR0_0 0x000071C7 // Set DTRPTN to 0x7. RFSHDT=0 +-DATA 4 DDR_PHY_DTCR1_0 0x00010236 // Set RANKEN +- +-CLR_BIT 4 DDR_PHY_DX4GCR1_0 0xFF // disable byte 4 +- +-// Launch Write leveling +-DATA 4 DDR_PHY_PIR_0 0x200 +-DATA 4 DDR_PHY_PIR_0 0x201 +-// Wait Write leveling to complete +-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 +- +-// Set DQS/DQSn glitch suppression resistor for training PHY0 +-DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7 +-// Launch Read DQS training +-DATA 4 DDR_PHY_PIR_0 0x400 +-DATA 4 DDR_PHY_PIR_0 0x401 +-// Wait Read DQS training to complete PHY0 +-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +-// Remove DQS/DQSn glitch suppression resistor PHY0 +-DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000 +- +-// DQS2DQ training, Write leveling, Deskew and eye trainings +-DATA 4 DDR_PHY_PIR_0 0x0010F800 +-DATA 4 DDR_PHY_PIR_0 0x0010F801 +-// Wait for training to complete +-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 +- +-// Launch VREF training +-DATA 4 DDR_PHY_PIR_0 0x00020000 +-DATA 4 DDR_PHY_PIR_0 0x00020001 +-// Wait for training to complete +-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00080000 +- +-//Re-allow uMCTL2 to send commands to DDR +-CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 +- +-//DQS Drift Registers PHY0 +-CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +-CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +-CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +-CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +-// Enable DQS drift detection PHY0 +-DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +-DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +-DATA 4 DDR_PHY_DQSDR2_0 0x00070200 +- +-// Enable VT compensation +-CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 +- +-//Check that controller is ready to operate +-CHECK_BITS_SET 4 DDRC_STAT_0 0x1 +- +-#endif +diff --git a/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express1GB b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express1GB +new file mode 100644 +index 0000000..abf0ad8 +--- /dev/null ++++ b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express1GB +@@ -0,0 +1,284 @@ ++#define __ASSEMBLY__ ++ ++#include ++#include ++ ++/* ++ * Device Configuration Data (DCD) ++ * ++ * Each entry must have the format: ++ * Addr-type Address Value ++ * ++ * where: ++ * Addr-type register length (1,2 or 4 bytes) ++ * Address absolute address of the register ++ * value value to be stored in the register ++ */ ++ ++#ifndef SCFW_DCD ++/* For 1200MHz DDR, DRC 600MHz operation */ ++DATA 4 0xff190000 0x00000CC8 /* DRC0 bringup */ ++#else ++/* Set the DRC rate to 600MHz, the PHY PLL will double this for the DRAM rate. */ ++uint32_t rate2 = SC_600MHZ; ++pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); ++#endif ++ ++DATA 4 0x41C80208 0x1 ++DATA 4 0x41C80040 0xb ++DATA 4 0x41C80204 0x1 ++ ++/* DRAM 0 controller configuration begin */ ++DATA 4 DDRC_MSTR_0 0xC1080020 // Set LPDDR4, BL = 16 and active ranks ++DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data ++DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read ++DATA 4 DDRC_RFSHTMG_0 0x0049006C // tREFI, tRFC ++DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us ++DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us ++DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2 ++DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13 ++DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd ++DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin ++DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC ++DATA 4 DDRC_DRAMTMG2_0 0x060E1714 // WL, RL, rd2wr, wr2rd ++DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod ++DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp ++DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke ++DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx ++DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx ++DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD ++DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD ++DATA 4 DDRC_DRAMTMG14_0 0x00000071 // txsr ++DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT ++DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval ++DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat ++DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable ++DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat ++DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity ++DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation ++DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) ++DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en ++DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 ++DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 ++DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated ++DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 ++DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 ++DATA 4 DDRC_ADDRMAP6_0 0x0F070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 ++DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 ++DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt ++DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 ++ ++DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 ++ ++DATA 4 DDRC_PWRCTL_0 0x0000010D ++ ++DATA 4 0x41c80208 0x1 ++DATA 4 0x41c80040 0xf ++DATA 4 0x41c80204 0x1 ++ ++//------------------------------------------- ++// Configure registers for PHY initialization ++// Timings are computed for 1200MHz DRAM operation ++//-------------------------------------------- ++// Set-up DRAM Configuration Register ++DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank ++// Set-up byte and bit swapping registers ++DATA 4 DDR_PHY_PGCR8_0 0x0001000A ++DATA 4 DDR_PHY_DX0DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping ++DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping ++DATA 4 DDR_PHY_DX1DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping ++DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping ++DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping ++DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping ++DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping ++DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping ++DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY ++DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY ++// Set-up PHY General Configuration Register ++// PGCR1,4,5,6,7 are untouched ++SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1 ++DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) ++DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD ++DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity ++// Set-up PHY Timing Register ++// PTR2 is untouched ++DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST ++DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST ++// Set-up PLL Control Register ++DATA 4 DDR_PHY_PLLCR0_0 0x001C0000 ++DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000 ++// Set-up Impedance Control Register ++DATA 4 DDR_PHY_ZQCR_0 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) ++// ZPROG_DRAM_ODT and ZPROG_HOST_ODT ++DATA 4 DDR_PHY_ZQ0PR0_0 0x1BBBB // Optimal setting based on factory testing ++DATA 4 DDR_PHY_ZQ1PR0_0 0x1B9BB // Optimal setting based on factory testing ++// Set-up PHY Initialization Register ++DATA 4 DDR_PHY_PIR_0 0x32 ++// Launch initialization (set bit 0) ++DATA 4 DDR_PHY_PIR_0 0x33 ++ ++ ++//------------------------------------------- ++// Configure registers for DRAM initialization ++//------------------------------------------- ++// Set-up Mode Register ++// MR0, MR3, MR4, MR5 MR6 are untouched ++DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST ++DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL ++DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength ++ ++DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT ++DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) ++/* LPDDR4 mode register writes for CA and DQ VREF settings */ ++DATA 4 DDR_PHY_MR12_0 0x48 ++DATA 4 DDR_PHY_MR14_0 0x48 ++// Set-up DRAM Timing Parameters Register ++// DTPR6 is untouched ++DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP ++DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD ++DATA 4 DDR_PHY_DTPR2_0 0x006960E2 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS ++DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK) ++DATA 4 DDR_PHY_DTPR4_0 0x00D82B0C // tRFC, tWLO, tXP ++DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR ++// Set-up PHY Timing Register ++DATA 4 DDR_PHY_PTR3_0 0x00249F00 // tDINIT0 ++DATA 4 DDR_PHY_PTR4_0 0x00000960 // tDINIT1 ++DATA 4 DDR_PHY_PTR5_0 0x0003A980 // tDINIT2 ++DATA 4 DDR_PHY_PTR6_0 0x027004B0 // tDINIT4, tDINIT3 ++ ++ ++// Set-up ODT Configuration Register ++// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. ++DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write ++DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled ++DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write ++DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled ++ ++ ++// Set-up AC I/O Configuration Register ++// ACIOCR1-4 are untouched ++DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 ++DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 ++// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. ++DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 ++// Set-up VREF Training Control Registers ++DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 ++DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0 ++// Set-up DATX8 General Configuration Registers ++// DXnGCR0-4 are untouched ++SET_BIT 4 DDR_PHY_PGCR5_0 0x4 ++DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit ++// Set-up DATX8 General Configuration Registers ++DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults ++DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults ++DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults ++DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults ++DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults ++DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults ++DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults ++DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults ++// Set-up DATX8 DX Control Register 2 ++// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA ++DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400 ++// Set-up DATX8 IO Control Register ++DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 ++ ++#if DDR_TRAIN_IN_DCD ++// Wait PHY initialization end then launch DRAM initialization ++// Wait for bit 0 of PGSR0 to be '1' ++CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 ++CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured ++ ++// Launch DRAM 0 initialization (set bit 0) ++DATA 4 DDR_PHY_PIR_0 0x180 ++DATA 4 DDR_PHY_PIR_0 0x181 ++ ++// DRAM 0 initialization end ++CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 ++CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 ++ ++// Launch a second time DRAM initialization due to following Synopsys PHY bug: ++// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" ++// Workaround: "Run DRAM Initialization twice" ++DATA 4 DDR_PHY_PIR_0 0x100 ++DATA 4 DDR_PHY_PIR_0 0x101 ++ ++// Wait (second time) DRAM 0 initialization end ++CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 ++CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 ++ ++//---------------------------------------------------------------// ++// DATA training ++//---------------------------------------------------------------// ++// configure PHY for data training ++// The following register writes are recommended by SNPS prior to running training ++CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift ++SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation ++CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation ++SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 ++// Per SNPS initialize BIST registers for VREF training ++DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) ++DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) ++DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) ++ ++// Set-up Data Training Configuration Register ++// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys ++// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). ++// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED). ++DATA 4 DDR_PHY_DTCR0_0 0x000071C7 // Set DTRPTN to 0x7. RFSHDT=0 ++DATA 4 DDR_PHY_DTCR1_0 0x00010236 // Set RANKEN ++ ++CLR_BIT 4 DDR_PHY_DX4GCR1_0 0xFF // disable byte 4 ++ ++// Launch Write leveling ++DATA 4 DDR_PHY_PIR_0 0x200 ++DATA 4 DDR_PHY_PIR_0 0x201 ++// Wait Write leveling to complete ++CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 ++CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 ++ ++// Set DQS/DQSn glitch suppression resistor for training PHY0 ++DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7 ++// Launch Read DQS training ++DATA 4 DDR_PHY_PIR_0 0x400 ++DATA 4 DDR_PHY_PIR_0 0x401 ++// Wait Read DQS training to complete PHY0 ++CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 ++CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 ++// Remove DQS/DQSn glitch suppression resistor PHY0 ++DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000 ++ ++// DQS2DQ training, Write leveling, Deskew and eye trainings ++DATA 4 DDR_PHY_PIR_0 0x0010F800 ++DATA 4 DDR_PHY_PIR_0 0x0010F801 ++// Wait for training to complete ++CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 ++CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 ++ ++// Launch VREF training ++DATA 4 DDR_PHY_PIR_0 0x00020000 ++DATA 4 DDR_PHY_PIR_0 0x00020001 ++// Wait for training to complete ++CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 ++CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00080000 ++ ++//Re-allow uMCTL2 to send commands to DDR ++CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 ++ ++//DQS Drift Registers PHY0 ++CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 ++CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 ++CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 ++CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 ++// Enable DQS drift detection PHY0 ++DATA 4 DDR_PHY_DQSDR0_0 0x20188005 ++DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 ++DATA 4 DDR_PHY_DQSDR2_0 0x00070200 ++ ++// Enable VT compensation ++CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 ++ ++//Check that controller is ready to operate ++CHECK_BITS_SET 4 DDRC_STAT_0 0x1 ++ ++#endif +diff --git a/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express2GB b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express2GB +new file mode 100644 +index 0000000..bb37fd5 +--- /dev/null ++++ b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express2GB +@@ -0,0 +1,284 @@ ++#define __ASSEMBLY__ ++ ++#include ++#include ++ ++/* ++ * Device Configuration Data (DCD) ++ * ++ * Each entry must have the format: ++ * Addr-type Address Value ++ * ++ * where: ++ * Addr-type register length (1,2 or 4 bytes) ++ * Address absolute address of the register ++ * value value to be stored in the register ++ */ ++ ++#ifndef SCFW_DCD ++/* For 1200MHz DDR, DRC 600MHz operation */ ++DATA 4 0xff190000 0x00000CC8 /* DRC0 bringup */ ++#else ++/* Set the DRC rate to 600MHz, the PHY PLL will double this for the DRAM rate. */ ++uint32_t rate2 = SC_600MHZ; ++pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); ++#endif ++ ++DATA 4 0x41C80208 0x1 ++DATA 4 0x41C80040 0xb ++DATA 4 0x41C80204 0x1 ++ ++/* DRAM 0 controller configuration begin */ ++DATA 4 DDRC_MSTR_0 0xC1080020 // Set LPDDR4, BL = 16 and active ranks ++DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data ++DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read ++DATA 4 DDRC_RFSHTMG_0 0x004900A8 // tREFI, tRFC ++DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us ++DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us ++DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2 ++DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13 ++DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd ++DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin ++DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC ++DATA 4 DDRC_DRAMTMG2_0 0x060E1714 // WL, RL, rd2wr, wr2rd ++DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod ++DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp ++DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke ++DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx ++DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx ++DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD ++DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD ++DATA 4 DDRC_DRAMTMG14_0 0x000000AD // txsr ++DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT ++DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval ++DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat ++DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable ++DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat ++DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity ++DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation ++DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) ++DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en ++DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 ++DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 ++DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated ++DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 ++DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 ++DATA 4 DDRC_ADDRMAP6_0 0x07070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 ++DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 ++DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt ++DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 ++ ++DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 ++ ++DATA 4 DDRC_PWRCTL_0 0x0000010D ++ ++DATA 4 0x41c80208 0x1 ++DATA 4 0x41c80040 0xf ++DATA 4 0x41c80204 0x1 ++ ++//------------------------------------------- ++// Configure registers for PHY initialization ++// Timings are computed for 1200MHz DRAM operation ++//-------------------------------------------- ++// Set-up DRAM Configuration Register ++DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank ++// Set-up byte and bit swapping registers ++DATA 4 DDR_PHY_PGCR8_0 0x0001000A ++DATA 4 DDR_PHY_DX0DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping ++DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping ++DATA 4 DDR_PHY_DX1DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping ++DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping ++DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping ++DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping ++DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping ++DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping ++DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY ++DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY ++// Set-up PHY General Configuration Register ++// PGCR1,4,5,6,7 are untouched ++SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1 ++DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) ++DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD ++DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity ++// Set-up PHY Timing Register ++// PTR2 is untouched ++DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST ++DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST ++// Set-up PLL Control Register ++DATA 4 DDR_PHY_PLLCR0_0 0x001C0000 ++DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000 ++// Set-up Impedance Control Register ++DATA 4 DDR_PHY_ZQCR_0 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) ++// ZPROG_DRAM_ODT and ZPROG_HOST_ODT ++DATA 4 DDR_PHY_ZQ0PR0_0 0x1BBBB // Optimal setting based on factory testing ++DATA 4 DDR_PHY_ZQ1PR0_0 0x1B9BB // Optimal setting based on factory testing ++// Set-up PHY Initialization Register ++DATA 4 DDR_PHY_PIR_0 0x32 ++// Launch initialization (set bit 0) ++DATA 4 DDR_PHY_PIR_0 0x33 ++ ++ ++//------------------------------------------- ++// Configure registers for DRAM initialization ++//------------------------------------------- ++// Set-up Mode Register ++// MR0, MR3, MR4, MR5 MR6 are untouched ++DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST ++DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL ++DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength ++ ++DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT ++DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) ++/* LPDDR4 mode register writes for CA and DQ VREF settings */ ++DATA 4 DDR_PHY_MR12_0 0x48 ++DATA 4 DDR_PHY_MR14_0 0x48 ++// Set-up DRAM Timing Parameters Register ++// DTPR6 is untouched ++DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP ++DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD ++DATA 4 DDR_PHY_DTPR2_0 0x0069615A // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS ++DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK) ++DATA 4 DDR_PHY_DTPR4_0 0x01502B0C // tRFC, tWLO, tXP ++DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR ++// Set-up PHY Timing Register ++DATA 4 DDR_PHY_PTR3_0 0x00249F00 // tDINIT0 ++DATA 4 DDR_PHY_PTR4_0 0x00000960 // tDINIT1 ++DATA 4 DDR_PHY_PTR5_0 0x0003A980 // tDINIT2 ++DATA 4 DDR_PHY_PTR6_0 0x027004B0 // tDINIT4, tDINIT3 ++ ++ ++// Set-up ODT Configuration Register ++// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. ++DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write ++DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled ++DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write ++DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled ++ ++ ++// Set-up AC I/O Configuration Register ++// ACIOCR1-4 are untouched ++DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 ++DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 ++// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. ++DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 ++// Set-up VREF Training Control Registers ++DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 ++DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0 ++// Set-up DATX8 General Configuration Registers ++// DXnGCR0-4 are untouched ++SET_BIT 4 DDR_PHY_PGCR5_0 0x4 ++DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit ++// Set-up DATX8 General Configuration Registers ++DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults ++DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults ++DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults ++DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults ++DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults ++DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults ++DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults ++DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults ++// Set-up DATX8 DX Control Register 2 ++// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA ++DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400 ++// Set-up DATX8 IO Control Register ++DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 ++ ++#if DDR_TRAIN_IN_DCD ++// Wait PHY initialization end then launch DRAM initialization ++// Wait for bit 0 of PGSR0 to be '1' ++CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 ++CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured ++ ++// Launch DRAM 0 initialization (set bit 0) ++DATA 4 DDR_PHY_PIR_0 0x180 ++DATA 4 DDR_PHY_PIR_0 0x181 ++ ++// DRAM 0 initialization end ++CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 ++CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 ++ ++// Launch a second time DRAM initialization due to following Synopsys PHY bug: ++// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" ++// Workaround: "Run DRAM Initialization twice" ++DATA 4 DDR_PHY_PIR_0 0x100 ++DATA 4 DDR_PHY_PIR_0 0x101 ++ ++// Wait (second time) DRAM 0 initialization end ++CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 ++CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 ++ ++//---------------------------------------------------------------// ++// DATA training ++//---------------------------------------------------------------// ++// configure PHY for data training ++// The following register writes are recommended by SNPS prior to running training ++CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift ++SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation ++CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation ++SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 ++// Per SNPS initialize BIST registers for VREF training ++DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) ++DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) ++DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) ++ ++// Set-up Data Training Configuration Register ++// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys ++// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). ++// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED). ++DATA 4 DDR_PHY_DTCR0_0 0x000071C7 // Set DTRPTN to 0x7. RFSHDT=0 ++DATA 4 DDR_PHY_DTCR1_0 0x00010236 // Set RANKEN ++ ++CLR_BIT 4 DDR_PHY_DX4GCR1_0 0xFF // disable byte 4 ++ ++// Launch Write leveling ++DATA 4 DDR_PHY_PIR_0 0x200 ++DATA 4 DDR_PHY_PIR_0 0x201 ++// Wait Write leveling to complete ++CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 ++CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 ++ ++// Set DQS/DQSn glitch suppression resistor for training PHY0 ++DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7 ++// Launch Read DQS training ++DATA 4 DDR_PHY_PIR_0 0x400 ++DATA 4 DDR_PHY_PIR_0 0x401 ++// Wait Read DQS training to complete PHY0 ++CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 ++CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 ++// Remove DQS/DQSn glitch suppression resistor PHY0 ++DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000 ++ ++// DQS2DQ training, Write leveling, Deskew and eye trainings ++DATA 4 DDR_PHY_PIR_0 0x0010F800 ++DATA 4 DDR_PHY_PIR_0 0x0010F801 ++// Wait for training to complete ++CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 ++CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 ++ ++// Launch VREF training ++DATA 4 DDR_PHY_PIR_0 0x00020000 ++DATA 4 DDR_PHY_PIR_0 0x00020001 ++// Wait for training to complete ++CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 ++CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00080000 ++ ++//Re-allow uMCTL2 to send commands to DDR ++CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 ++ ++//DQS Drift Registers PHY0 ++CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 ++CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 ++CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 ++CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 ++// Enable DQS drift detection PHY0 ++DATA 4 DDR_PHY_DQSDR0_0 0x20188005 ++DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 ++DATA 4 DDR_PHY_DQSDR2_0 0x00070200 ++ ++// Enable VT compensation ++CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 ++ ++//Check that controller is ready to operate ++CHECK_BITS_SET 4 DDRC_STAT_0 0x1 ++ ++#endif diff --git a/meta-digi-arm/recipes-bsp/imx-mkimage/imx-boot_%.bbappend b/meta-digi-arm/recipes-bsp/imx-mkimage/imx-boot_%.bbappend deleted file mode 100644 index c8ba2530d..000000000 --- a/meta-digi-arm/recipes-bsp/imx-mkimage/imx-boot_%.bbappend +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (C) 2018 Digi International, Inc. - -SRC_URI_append = " \ - file://0001-cc8x-configure-DDRC-for-Micron-MT53B256M32D1.patch \ -" diff --git a/meta-digi-arm/recipes-bsp/imx-mkimage/imx-boot_0.2.bb b/meta-digi-arm/recipes-bsp/imx-mkimage/imx-boot_0.2.bb index a1d8dfce2..c4856b387 100644 --- a/meta-digi-arm/recipes-bsp/imx-mkimage/imx-boot_0.2.bb +++ b/meta-digi-arm/recipes-bsp/imx-mkimage/imx-boot_0.2.bb @@ -9,6 +9,11 @@ require imx-mkimage_git.inc inherit deploy +SRC_URI_append = " \ + file://0001-cc8x-configure-DDRC-for-Micron-MT53B256M32D1.patch \ + file://0002-cc8x-add-second-DCD-for-the-2GB-variant-of-the-cc8x.patch \ +" + # Add CFLAGS with native INCDIR & LIBDIR for imx-mkimage build CFLAGS = "-O2 -Wall -std=c99 -static -I ${STAGING_INCDIR_NATIVE} -L ${STAGING_LIBDIR_NATIVE}" @@ -56,6 +61,8 @@ DCD_NAME ?= "imx8qm_dcd.cfg.tmp" DCD_NAME_mx8qm = "imx8qm_dcd.cfg.tmp" DCD_NAME_mx8qxp = "imx8qx_dcd.cfg.tmp" +DCD_SRC_NAME = "imx8qx_dcd_1.2GHz.cfg" + UBOOT_NAME = "u-boot-${MACHINE}.bin" BOOT_CONFIG_MACHINE = "${BOOT_NAME}" @@ -126,9 +133,10 @@ do_compile () { # mkimage for i.MX8 for type in ${UBOOT_CONFIG}; do - cd ${S}/${SOC_TARGET} - ln -sf u-boot.bin-${type} u-boot.bin - cd - + cd ${S}/${SOC_TARGET} + ln -sf u-boot.bin-${type} u-boot.bin + ln -sf ${DCD_SRC_NAME}-${type} ${DCD_SRC_NAME} + cd - for target in ${IMXBOOT_TARGETS}; do echo "building ${SOC_TARGET} - ${type} - ${target}" make SOC=${SOC_TARGET} ${target} @@ -136,7 +144,9 @@ do_compile () { cp ${S}/${SOC_TARGET}/flash.bin ${S}/${BOOT_CONFIG_MACHINE}-${type}.bin-${target} fi done - rm ${S}/${SOC_TARGET}/u-boot.bin + cp ${S}/${SOC_TARGET}/${DCD_NAME} ${S}/${SOC_TARGET}/${DCD_NAME}-${type} + rm ${S}/${SOC_TARGET}/${DCD_SRC_NAME} + rm ${S}/${SOC_TARGET}/u-boot.bin done } @@ -175,7 +185,9 @@ do_deploy () { install -m 0755 ${S}/${TOOLS_NAME} ${DEPLOYDIR}/${BOOT_TOOLS} else # the DCD only needs to get copied when using an A0 CPU - install -m 0644 ${S}/${SOC_TARGET}/${DCD_NAME} ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT} + for type in ${UBOOT_CONFIG}; do + install -m 0644 ${S}/${SOC_TARGET}/${DCD_NAME}-${type} ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT} + done install -m 0644 ${S}/${SOC_TARGET}/ahab-container.img ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT} install -m 0644 ${S}/${SOC_TARGET}/m40_tcm.bin ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT} install -m 0644 ${S}/${SOC_TARGET}/CM4.bin ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT} @@ -193,7 +205,7 @@ do_deploy () { # copy the generated boot image to deploy path for type in ${UBOOT_CONFIG}; do - IMAGE_IMXBOOT_TARGET="" + IMAGE_IMXBOOT_TARGET="" for target in ${IMXBOOT_TARGETS}; do # Use first "target" as IMAGE_IMXBOOT_TARGET if [ "$IMAGE_IMXBOOT_TARGET" = "" ]; then