54 lines
1.9 KiB
Diff
54 lines
1.9 KiB
Diff
From: Javier Viguera <javier.viguera@digi.com>
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Date: Tue, 31 Oct 2023 11:25:46 +0100
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Subject: [PATCH] imx93: bring back ELE clock workaround for soc revision A0
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Revert commit 7411561db535a20f61ff6621fec5b374130d34f9 to allow building
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for soc revision A0 using a compilation flag.
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Signed-off-by: Javier Viguera <javier.viguera@digi.com>
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---
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plat/imx/imx93/imx93_psci.c | 10 ++++++++++
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plat/imx/imx93/platform.mk | 4 ++++
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2 files changed, 14 insertions(+)
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diff --git a/plat/imx/imx93/imx93_psci.c b/plat/imx/imx93/imx93_psci.c
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index 0fd2bb7802df..461801afb126 100644
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--- a/plat/imx/imx93/imx93_psci.c
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+++ b/plat/imx/imx93/imx93_psci.c
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@@ -783,6 +783,11 @@ void imx_pwr_domain_suspend(const psci_power_state_t *target_state)
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} else {
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write_clusterpwrdn(DSU_CLUSTER_PWR_OFF);
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}
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+
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+#ifdef SOC_REV_A0
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+ /* FIXME: slow down S401 clock: 24M OSC */
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+ mmio_clrbits_32(0x44450200, GENMASK_32(9, 8));
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+#endif
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}
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if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
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@@ -902,6 +907,11 @@ void imx_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
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mmio_write_32(IMX_GPC_BASE + A55C0_CMC_OFFSET + 0x800 * 2 + CM_MODE_CTRL, CM_MODE_RUN);
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/* clear L3 retention */
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mmio_clrbits_32(IMX_SRC_BASE + A55C0_MEM + 0x400 * 3 + 0x4, MEM_LP_RETENTION);
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+
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+#ifdef SOC_REV_A0
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+ /* FIXME: set S401 clock back */
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+ mmio_setbits_32(0x44450200, BIT(9));
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+#endif
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}
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/* do core level */
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if (is_local_state_off(CORE_PWR_STATE(target_state))) {
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diff --git a/plat/imx/imx93/platform.mk b/plat/imx/imx93/platform.mk
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index be09b9f0be7a..440c13c1dbe1 100644
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--- a/plat/imx/imx93/platform.mk
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+++ b/plat/imx/imx93/platform.mk
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@@ -57,3 +57,7 @@ BL32_BASE ?= 0x96000000
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BL32_SIZE ?= 0x02000000
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$(eval $(call add_define,BL32_BASE))
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$(eval $(call add_define,BL32_SIZE))
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+
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+ifeq (${SOC_REV_A0},1)
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+$(eval $(call add_define,SOC_REV_A0))
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+endif
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