27 lines
922 B
Diff
27 lines
922 B
Diff
From: Jacky Bai <ping.bai@nxp.com>
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Date: Wed, 23 Oct 2019 13:44:28 +0800
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Subject: [PATCH] plat: imx8m: update the lpddr4 retention flow for imx8mn
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for i.MX8MN, it can only support 16bit DDR, so
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it is not necessary to config the DDR_SS_GPR register.
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Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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---
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plat/imx/common/imx8m/lpddr4_retention.c | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/plat/imx/common/imx8m/lpddr4_retention.c b/plat/imx/common/imx8m/lpddr4_retention.c
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index 8cc44c8..dbec3d5 100644
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--- a/plat/imx/common/imx8m/lpddr4_retention.c
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+++ b/plat/imx/common/imx8m/lpddr4_retention.c
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@@ -184,7 +184,9 @@ void lpddr4_exit_retention(void)
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/* before write Dynamic reg, sw_done should be 0 */
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mmio_write_32(DDRC_SWCTL(0), 0x00000000);
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+#if !defined(PLAT_imx8mn)
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mmio_write_32(DDRC_DDR_SS_GPR0, 0x01); /*LPDDR4 mode */
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+#endif
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mmio_write_32(DDRC_DFIMISC(0), 0x00000000);
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/* dram phy re-init */
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