31 lines
1.1 KiB
Diff
31 lines
1.1 KiB
Diff
From: Hector Palacios <hector.palacios@digi.com>
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Date: Fri, 21 Nov 2025 11:30:35 +0100
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Subject: [PATCH] ccimx95: enable non-secure, non-privilege access to GPIO1
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GPIO1 port is reserved on NXP EVK but we want to enable
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full access to the port from the non-secure world.
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Signed-off-by: Hector Palacios <hector.palacios@digi.com>
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https://onedigi.atlassian.net/browse/DEL-9839
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---
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plat/imx/imx95/imx95_bl31_setup.c | 5 +++++
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1 file changed, 5 insertions(+)
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diff --git a/plat/imx/imx95/imx95_bl31_setup.c b/plat/imx/imx95/imx95_bl31_setup.c
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index 175a78a20021..fcf41a0ffa5b 100644
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--- a/plat/imx/imx95/imx95_bl31_setup.c
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+++ b/plat/imx/imx95/imx95_bl31_setup.c
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@@ -108,6 +108,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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void bl31_plat_arch_setup(void)
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{
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/* Assign all the GPIO pins to non-secure world by default */
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+ mmio_write_32(GPIO1_BASE + 0x10, 0xffffffff);
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+ mmio_write_32(GPIO1_BASE + 0x14, 0x3);
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+ mmio_write_32(GPIO1_BASE + 0x18, 0xffffffff);
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+ mmio_write_32(GPIO1_BASE + 0x1c, 0x3);
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+
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mmio_write_32(GPIO2_BASE + 0x10, 0xffffffff);
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mmio_write_32(GPIO2_BASE + 0x14, 0x3);
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mmio_write_32(GPIO2_BASE + 0x18, 0xffffffff);
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