imx-boot: remove DCD patches
These patches were originally introduced in the recipe because the DCD files were needed by mkimage to create the final imx-boot binaries. Now they are in the SCFW source code instead. https://jira.digi.com/browse/DEL-6158 Signed-off-by: Gabriel Valcazar <gabriel.valcazar@digi.com>
This commit is contained in:
Gabriel Valcazar
parent
17b054059d
commit
577302650d
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@ -1,315 +0,0 @@
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From: Gabriel Valcazar <gabriel.valcazar@digi.com>
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Date: Fri, 27 Jul 2018 12:50:37 +0200
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Subject: [PATCH 2/2] cc8x: add second DCD for the 2GB variant of the cc8x
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This DCD is the same as the one used for the 1GB variant, but with minor timing
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and indexing changes.
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Also, suffix each DCD with their corresponding UBOOT_CONFIG values so the
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imx-boot recipe is able to handle them.
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https://jira.digi.com/browse/DEL-6085
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Signed-off-by: Gabriel Valcazar <gabriel.valcazar@digi.com>
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Signed-off-by: Arturo Buzarra <arturo.buzarra@digi.com>
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---
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...d_1.2GHz.cfg => imx8qx_dcd_1.2GHz.cfg-1GB} | 0
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iMX8QX/imx8qx_dcd_1.2GHz.cfg-2GB | 284 ++++++++++++++++++
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2 files changed, 284 insertions(+)
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rename iMX8QX/{imx8qx_dcd_1.2GHz.cfg => imx8qx_dcd_1.2GHz.cfg-1GB} (100%)
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create mode 100644 iMX8QX/imx8qx_dcd_1.2GHz.cfg-2GB
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diff --git a/iMX8QX/imx8qx_dcd_1.2GHz.cfg b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-1GB
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similarity index 100%
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rename from iMX8QX/imx8qx_dcd_1.2GHz.cfg
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rename to iMX8QX/imx8qx_dcd_1.2GHz.cfg-1GB
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diff --git a/iMX8QX/imx8qx_dcd_1.2GHz.cfg-2GB b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-2GB
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new file mode 100644
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index 0000000..bb37fd5
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--- /dev/null
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+++ b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-2GB
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@@ -0,0 +1,284 @@
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+#define __ASSEMBLY__
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+
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+#include <ddrc_mem_map.h>
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+#include <ddr_phy_mem_map.h>
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+
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+/*
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+ * Device Configuration Data (DCD)
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+ *
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+ * Each entry must have the format:
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+ * Addr-type Address Value
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+ *
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+ * where:
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+ * Addr-type register length (1,2 or 4 bytes)
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+ * Address absolute address of the register
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+ * value value to be stored in the register
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+ */
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+
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+#ifndef SCFW_DCD
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+/* For 1200MHz DDR, DRC 600MHz operation */
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+DATA 4 0xff190000 0x00000CC8 /* DRC0 bringup */
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+#else
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+/* Set the DRC rate to 600MHz, the PHY PLL will double this for the DRAM rate. */
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+uint32_t rate2 = SC_600MHZ;
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+pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2);
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+#endif
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+
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+DATA 4 0x41C80208 0x1
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+DATA 4 0x41C80040 0xb
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+DATA 4 0x41C80204 0x1
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+
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+/* DRAM 0 controller configuration begin */
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+DATA 4 DDRC_MSTR_0 0xC1080020 // Set LPDDR4, BL = 16 and active ranks
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+DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data
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+DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read
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+DATA 4 DDRC_RFSHTMG_0 0x004900A8 // tREFI, tRFC
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+DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us
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+DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us
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+DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2
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+DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13
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+DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
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+DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin
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+DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC
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+DATA 4 DDRC_DRAMTMG2_0 0x060E1714 // WL, RL, rd2wr, wr2rd
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+DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod
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+DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp
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+DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke
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+DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx
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+DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx
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+DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD
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+DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD
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+DATA 4 DDRC_DRAMTMG14_0 0x000000AD // txsr
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+DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT
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+DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval
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+DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat
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+DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
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+DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat
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+DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity
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+DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation
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+DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max)
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+DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en
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+DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0
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+DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6
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+DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated
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+DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
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+DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
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+DATA 4 DDRC_ADDRMAP6_0 0x07070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12
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+DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1
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+DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt
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+DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0
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+
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+DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000
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+
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+DATA 4 DDRC_PWRCTL_0 0x0000010D
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+
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+DATA 4 0x41c80208 0x1
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+DATA 4 0x41c80040 0xf
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+DATA 4 0x41c80204 0x1
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+
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+//-------------------------------------------
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+// Configure registers for PHY initialization
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+// Timings are computed for 1200MHz DRAM operation
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+//--------------------------------------------
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+// Set-up DRAM Configuration Register
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+DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank
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+// Set-up byte and bit swapping registers
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+DATA 4 DDR_PHY_PGCR8_0 0x0001000A
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+DATA 4 DDR_PHY_DX0DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
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+DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
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+DATA 4 DDR_PHY_DX1DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
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+DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
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+DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
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+DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
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+DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
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+DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
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+DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
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+DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
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+// Set-up PHY General Configuration Register
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+// PGCR1,4,5,6,7 are untouched
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+SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1
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+DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy)
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+DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD
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+DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity
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+// Set-up PHY Timing Register
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+// PTR2 is untouched
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+DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST
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+DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST
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+// Set-up PLL Control Register
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+DATA 4 DDR_PHY_PLLCR0_0 0x001C0000
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+DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000
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+// Set-up Impedance Control Register
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+DATA 4 DDR_PHY_ZQCR_0 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup)
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+// ZPROG_DRAM_ODT and ZPROG_HOST_ODT
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+DATA 4 DDR_PHY_ZQ0PR0_0 0x1BBBB // Optimal setting based on factory testing
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+DATA 4 DDR_PHY_ZQ1PR0_0 0x1B9BB // Optimal setting based on factory testing
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+// Set-up PHY Initialization Register
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+DATA 4 DDR_PHY_PIR_0 0x32
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+// Launch initialization (set bit 0)
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+DATA 4 DDR_PHY_PIR_0 0x33
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+
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+
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+//-------------------------------------------
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+// Configure registers for DRAM initialization
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+//-------------------------------------------
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+// Set-up Mode Register
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+// MR0, MR3, MR4, MR5 MR6 are untouched
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+DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST
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+DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL
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+DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength
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+
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+DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT
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+DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks)
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+/* LPDDR4 mode register writes for CA and DQ VREF settings */
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+DATA 4 DDR_PHY_MR12_0 0x48
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+DATA 4 DDR_PHY_MR14_0 0x48
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+// Set-up DRAM Timing Parameters Register
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+// DTPR6 is untouched
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+DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP
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+DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD
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+DATA 4 DDR_PHY_DTPR2_0 0x0069615A // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
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+DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
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+DATA 4 DDR_PHY_DTPR4_0 0x01502B0C // tRFC, tWLO, tXP
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+DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR
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+// Set-up PHY Timing Register
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+DATA 4 DDR_PHY_PTR3_0 0x00249F00 // tDINIT0
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+DATA 4 DDR_PHY_PTR4_0 0x00000960 // tDINIT1
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+DATA 4 DDR_PHY_PTR5_0 0x0003A980 // tDINIT2
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+DATA 4 DDR_PHY_PTR6_0 0x027004B0 // tDINIT4, tDINIT3
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+
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+
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+// Set-up ODT Configuration Register
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+// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
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+DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write
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+DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled
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+DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write
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+DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled
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+
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+
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+// Set-up AC I/O Configuration Register
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+// ACIOCR1-4 are untouched
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+DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2
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+DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4
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+// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON.
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+DATA 4 DDR_PHY_ACIOCR1_0 0x44000000
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+// Set-up VREF Training Control Registers
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+DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12
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+DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0
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+// Set-up DATX8 General Configuration Registers
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+// DXnGCR0-4 are untouched
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+SET_BIT 4 DDR_PHY_PGCR5_0 0x4
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+DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit
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+// Set-up DATX8 General Configuration Registers
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+DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
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+DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
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+DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
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+DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
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+DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
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+DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
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+DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
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+DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
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+// Set-up DATX8 DX Control Register 2
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+// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA
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+DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400
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+// Set-up DATX8 IO Control Register
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+DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4
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+
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+#if DDR_TRAIN_IN_DCD
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+// Wait PHY initialization end then launch DRAM initialization
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+// Wait for bit 0 of PGSR0 to be '1'
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+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
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+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured
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+
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+// Launch DRAM 0 initialization (set bit 0)
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+DATA 4 DDR_PHY_PIR_0 0x180
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+DATA 4 DDR_PHY_PIR_0 0x181
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+
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+// DRAM 0 initialization end
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+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
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+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
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+
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+// Launch a second time DRAM initialization due to following Synopsys PHY bug:
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+// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration"
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+// Workaround: "Run DRAM Initialization twice"
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+DATA 4 DDR_PHY_PIR_0 0x100
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+DATA 4 DDR_PHY_PIR_0 0x101
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+
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+// Wait (second time) DRAM 0 initialization end
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+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
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+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
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+
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+//---------------------------------------------------------------//
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+// DATA training
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+//---------------------------------------------------------------//
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+// configure PHY for data training
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+// The following register writes are recommended by SNPS prior to running training
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+CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift
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+SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation
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+CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation
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+SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1
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+// Per SNPS initialize BIST registers for VREF training
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+DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16)
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+DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC)
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+DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC)
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+
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+// Set-up Data Training Configuration Register
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+// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys
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+// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training).
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+// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED).
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+DATA 4 DDR_PHY_DTCR0_0 0x000071C7 // Set DTRPTN to 0x7. RFSHDT=0
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+DATA 4 DDR_PHY_DTCR1_0 0x00010236 // Set RANKEN
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+
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+CLR_BIT 4 DDR_PHY_DX4GCR1_0 0xFF // disable byte 4
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+
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+// Launch Write leveling
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+DATA 4 DDR_PHY_PIR_0 0x200
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+DATA 4 DDR_PHY_PIR_0 0x201
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+// Wait Write leveling to complete
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+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
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+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000
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+
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+// Set DQS/DQSn glitch suppression resistor for training PHY0
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+DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7
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+// Launch Read DQS training
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+DATA 4 DDR_PHY_PIR_0 0x400
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+DATA 4 DDR_PHY_PIR_0 0x401
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+// Wait Read DQS training to complete PHY0
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+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
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+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000
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+// Remove DQS/DQSn glitch suppression resistor PHY0
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+DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000
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+
|
||||
+// DQS2DQ training, Write leveling, Deskew and eye trainings
|
||||
+DATA 4 DDR_PHY_PIR_0 0x0010F800
|
||||
+DATA 4 DDR_PHY_PIR_0 0x0010F801
|
||||
+// Wait for training to complete
|
||||
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
|
||||
+
|
||||
+// Launch VREF training
|
||||
+DATA 4 DDR_PHY_PIR_0 0x00020000
|
||||
+DATA 4 DDR_PHY_PIR_0 0x00020001
|
||||
+// Wait for training to complete
|
||||
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
|
||||
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00080000
|
||||
+
|
||||
+//Re-allow uMCTL2 to send commands to DDR
|
||||
+CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0
|
||||
+
|
||||
+//DQS Drift Registers PHY0
|
||||
+CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000
|
||||
+CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000
|
||||
+CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000
|
||||
+CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000
|
||||
+// Enable DQS drift detection PHY0
|
||||
+DATA 4 DDR_PHY_DQSDR0_0 0x20188005
|
||||
+DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000
|
||||
+DATA 4 DDR_PHY_DQSDR2_0 0x00070200
|
||||
+
|
||||
+// Enable VT compensation
|
||||
+CLR_BIT 4 DDR_PHY_PGCR6_0 0x1
|
||||
+
|
||||
+//Check that controller is ready to operate
|
||||
+CHECK_BITS_SET 4 DDRC_STAT_0 0x1
|
||||
+
|
||||
+#endif
|
||||
|
|
@ -9,11 +9,6 @@ require imx-mkimage_git.inc
|
|||
|
||||
inherit deploy
|
||||
|
||||
SRC_URI_append = " \
|
||||
file://0001-cc8x-configure-DDRC-for-Micron-MT53B256M32D1.patch \
|
||||
file://0002-cc8x-add-second-DCD-for-the-2GB-variant-of-the-cc8x.patch \
|
||||
"
|
||||
|
||||
# Add CFLAGS with native INCDIR & LIBDIR for imx-mkimage build
|
||||
CFLAGS = "-O2 -Wall -std=c99 -static -I ${STAGING_INCDIR_NATIVE} -L ${STAGING_LIBDIR_NATIVE}"
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue