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Merge branch 'dey-2.4/master' into dey-2.4/maint 

Signed-off-by: Hector Palacios <hector.palacios@digi.com>
This commit is contained in:
Hector Palacios 2018-11-12 16:11:02 +01:00
parent d74e5d3cc2 d4c3751bbd
commit 9daca40854
41 changed files with 6916 additions and 948 deletions
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4
README.md
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@ -1,5 +1,5 @@
# Digi Embedded Yocto (DEY) 2.4
## Release 2.4-r2-beta
## Release 2.4-r2.4-beta
This document provides information about Digi Embedded Yocto,
Digi International's professional embedded Yocto development environment.
@ -98,7 +98,7 @@ Documentation is available online on the Digi documentation site:
# Release Changelog
## 2.4-r2-beta
## 2.4-r2.4-beta
* Added support for ConnectCore 8X platform. Supported features:
* Bluetooth and Wireless interfaces (STA, SoftAP, P2P, Concurrence)

4
meta-digi-arm/conf/machine/ccimx6ulsbc.conf
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@ -26,6 +26,10 @@ KERNEL_DEVICETREE ?= " \
imx6ul-ccimx6ulsbc-id135.dtb \
imx6ul-ccimx6ulsbc-id136.dtb \
"
KERNEL_DEVICETREE_use-mainline-bsp ?= "imx6ul-ccimx6ulsbcpro.dtb"
KERNEL_DEFCONFIG ?= "arch/arm/configs/ccimx6ul_defconfig"
KERNEL_DEFCONFIG_use-mainline-bsp ?= "arch/arm/configs/imx_v6_v7_defconfig"
SERIAL_CONSOLES ?= "115200;ttymxc4"

4
meta-digi-arm/conf/machine/ccimx6ulstarter.conf
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@ -25,6 +25,10 @@ KERNEL_DEVICETREE ?= " \
imx6ul-ccimx6ulstarter-wb.dtb \
imx6ul-ccimx6ulstarter-id129.dtb \
"
KERNEL_DEVICETREE_use-mainline-bsp ?= "imx6ul-ccimx6ulsbcexpress.dtb"
KERNEL_DEFCONFIG ?= "arch/arm/configs/ccimx6ul_defconfig"
KERNEL_DEFCONFIG_use-mainline-bsp ?= "arch/arm/configs/imx_v6_v7_defconfig"
SERIAL_CONSOLES ?= "115200;ttymxc4"

44
meta-digi-arm/conf/machine/ccimx8x-sbc-pro.conf Normal file
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@ -0,0 +1,44 @@
#@TYPE: Machine
#@NAME: ConnectCore 8X Single Board Computer Pro.
#@DESCRIPTION: Machine configuration for Digi's ConnectCore 8X SBC Pro.
# Include the machine configuration for Digi's ConnectCore 8X module.
include conf/machine/include/ccimx8x.inc
# Wireless external module
WIRELESS_MODULE_append = " ${@base_conditional('HAVE_WIFI', '1', 'kernel-module-qualcomm', '', d)}"
# Wireless p2p interface
WLAN_P2P_INTERFACE ?= "p2p0"
MACHINE_EXTRA_RRECOMMENDS += " \
cryptoauthlib \
cryptoauth-openssl-engine \
"
# Firmware
MACHINE_FIRMWARE_append = " ${@base_conditional('HAVE_BT', '1', 'firmware-qualcomm-qca6574-bt', '', d)}"
MACHINE_FIRMWARE_append = " ${@base_conditional('HAVE_WIFI', '1', 'firmware-qualcomm-qca6574-wifi', '', d)}"
# U-Boot configurations
# Last one is the default (the one the symlinks point at)
UBOOT_CONFIG ??= "ccimx8x_sbc_pro1GB ccimx8x_sbc_pro2GB"
UBOOT_CONFIG[ccimx8x_sbc_pro2GB] = "ccimx8x_sbc_pro2GB_defconfig,,u-boot-dtb.${UBOOT_SUFFIX}"
UBOOT_CONFIG[ccimx8x_sbc_pro1GB] = "ccimx8x_sbc_pro1GB_defconfig,,u-boot-dtb.${UBOOT_SUFFIX}"
KERNEL_DEVICETREE ?= " \
digi/ccimx8x-sbc-pro-id135.dtb \
digi/ccimx8x-sbc-pro-wb.dtb \
digi/ccimx8x-sbc-pro.dtb \
"
SERIAL_CONSOLES ?= "115200;ttyLP2"
# Bluetooth tty
BT_TTY ?= "ttyLP1"
# U-Boot script to be copied to the boot image
BOOT_SCRIPTS = "boot.scr:boot.scr"
# Flash image types
IMAGE_FSTYPES ?= "boot.vfat ext4 sdcard tar.bz2 recovery.vfat"

4
meta-digi-arm/conf/machine/include/ccimx6ul.inc
View File

@ -12,9 +12,6 @@ include conf/machine/include/tune-cortexa7.inc
UBOOT_SUFFIX = "imx"
UBOOT_SYMLINK = "u-boot-${MACHINE}.${UBOOT_SUFFIX}"
# Linux kernel configuration
KERNEL_DEFCONFIG ?= "arch/arm/configs/ccimx6ul_defconfig"
# Wireless external module
WIRELESS_MODULE ?= ""
WIRELESS_MODULE_append = " ${@base_conditional('HAVE_WIFI', '1', 'kernel-module-qualcomm', '', d)}"
@ -40,6 +37,7 @@ MACHINE_EXTRA_RRECOMMENDS += " \
cryptodev-module \
cryptoauth-openssl-engine \
"
MACHINE_EXTRA_RRECOMMENDS_remove_use-mainline-bsp = "${@bb.utils.contains('COMBINED_FEATURES', 'alsa', 'imx-alsa-plugins', '', d)}"
MACHINE_FEATURES += "wifi bluetooth cryptochip"

1
meta-digi-arm/conf/machine/include/digi-defaults.inc
View File

@ -3,6 +3,7 @@ PREFERRED_PROVIDER_jpeg-native ?= "jpeg-native"
PREFERRED_PROVIDER_u-boot ??= "u-boot-dey"
PREFERRED_PROVIDER_virtual/bootloader ??= "u-boot-dey"
PREFERRED_PROVIDER_virtual/kernel ??= "linux-dey"
PREFERRED_PROVIDER_virtual/kernel_use-mainline-bsp ??= "linux-4.18.y"
PREFERRED_PROVIDER_virtual/xserver = "xserver-xorg"
#

1
meta-digi-arm/conf/machine/include/imx-digi-base.inc
View File

@ -63,6 +63,7 @@ MACHINE_EXTRA_RRECOMMENDS += "udev-extraconf udev-rules-imx"
# GStreamer 1.0 plugins
MACHINE_GSTREAMER_1_0_PLUGIN ?= ""
MACHINE_GSTREAMER_1_0_PLUGIN_use-mainline-bsp ?= "gstreamer1.0-plugins-imx-meta"
MACHINE_GSTREAMER_1_0_PLUGIN_mx6q ?= "imx-gst1.0-plugin imx-gst1.0-plugin-gplay imx-gst1.0-plugin-grecorder"
MACHINE_GSTREAMER_1_0_PLUGIN_mx6dl ?= "imx-gst1.0-plugin imx-gst1.0-plugin-gplay imx-gst1.0-plugin-grecorder"
MACHINE_GSTREAMER_1_0_PLUGIN_mx6ul ?= "imx-gst1.0-plugin imx-gst1.0-plugin-gplay imx-gst1.0-plugin-grecorder"

2
meta-digi-arm/recipes-bsp/alsa-state/alsa-state.bbappend
View File

@ -12,6 +12,8 @@ SRC_URI_append_ccimx6 = " \
SRC_URI_append_ccimx6ul = " file://asound.state"
SRC_URI_append_ccimx8x = " file://asound.state"
do_install_append_ccimx6() {
ln -sf asound.micro_play.state ${D}${localstatedir}/lib/alsa/asound.state
}

268
meta-digi-arm/recipes-bsp/alsa-state/alsa-state/ccimx8x/asound.conf
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@ -1,271 +1,9 @@
defaults.pcm.rate_converter "linear"
pcm.dmix_48000{
type dmix
ipc_key 5678293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 48000
}
}
pcm.dmix_44100{
type dmix
ipc_key 5678293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 44100
}
}
pcm.dmix_32000{
type dmix
ipc_key 5678293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 32000
}
}
pcm.dmix_24000{
type dmix
ipc_key 5678293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 24000
}
}
pcm.dmix_22050{
type dmix
ipc_key 5678293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 22050
}
}
pcm.dmix_16000{
type dmix
ipc_key 5678293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 16000
}
}
pcm.dmix_12000{
type dmix
ipc_key 5678293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 12000
}
}
pcm.dmix_11025{
type dmix
ipc_key 5678293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 11025
}
}
pcm.dmix_8000{
type dmix
ipc_key 5678293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 8000
}
}
pcm.!dsnoop_48000{
type dsnoop
ipc_key 5778293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 48000
}
}
pcm.!dsnoop_44100{
type dsnoop
ipc_key 5778293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 44100
}
}
pcm.!dsnoop_32000{
type dsnoop
ipc_key 5778293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 32000
}
}
pcm.!dsnoop_24000{
type dsnoop
ipc_key 5778293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 24000
}
}
pcm.!dsnoop_22050{
type dsnoop
ipc_key 5778293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 22050
}
}
pcm.!dsnoop_16000{
type dsnoop
ipc_key 5778293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 16000
}
}
pcm.!dsnoop_12000{
type dsnoop
ipc_key 5778293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 12000
}
}
pcm.!dsnoop_11025{
type dsnoop
ipc_key 5778293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 11025
}
}
pcm.!dsnoop_8000{
type dsnoop
ipc_key 5778293
ipc_key_add_uid yes
slave{
pcm "hw:0,0"
period_time 40000
format S16_LE
rate 8000
}
}
pcm.asymed{
type asym
playback.pcm "dmix_44100"
capture.pcm "dsnoop_44100"
}
pcm.dsp0{
type plug
slave.pcm "asymed"
}
pcm.!default{
type plug
route_policy "average"
slave.pcm "asymed"
}
ctl.!default{
pcm.imxmax98088 {
type hw
card 0
}
ctl.mixer0{
ctl.imxmax98088 {
type hw
card 0
}
pcm_slave.esai{
pcm "hw:0,0"
channels 8
rate 48000
period_time 40000
}
pcm.esaich1to6{
type dshare
ipc_key 5778293
slave esai
bindings.0 0
bindings.1 4
bindings.2 1
bindings.3 5
bindings.4 2
bindings.5 6
}
pcm.esaich78{
type dshare
ipc_key 5778293
slave esai
bindings.0 3
bindings.1 7
}
ctl.!default imxmax98088

1148
meta-digi-arm/recipes-bsp/alsa-state/alsa-state/ccimx8x/asound.state Normal file
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File diff suppressed because it is too large Load Diff

BIN
meta-digi-arm/recipes-bsp/firmware-qualcomm/firmware-qualcomm/qca/nvm_tlv_3.2.bin
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Binary file not shown.

601
meta-digi-arm/recipes-bsp/imx-mkimage/files/0002-cc8x-add-second-DCD-for-the-2GB-variant-of-the-cc8x.patch
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@ -11,600 +11,23 @@ imx-boot recipe is able to handle them.
https://jira.digi.com/browse/DEL-6085
Signed-off-by: Gabriel Valcazar <gabriel.valcazar@digi.com>
Signed-off-by: Arturo Buzarra <arturo.buzarra@digi.com>
---
iMX8QX/imx8qx_dcd_1.2GHz.cfg | 284 ---------------------
.../imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express1GB | 284 +++++++++++++++++++++
.../imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express2GB | 284 +++++++++++++++++++++
3 files changed, 568 insertions(+), 284 deletions(-)
delete mode 100644 iMX8QX/imx8qx_dcd_1.2GHz.cfg
create mode 100644 iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express1GB
create mode 100644 iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express2GB
...d_1.2GHz.cfg => imx8qx_dcd_1.2GHz.cfg-1GB} | 0
iMX8QX/imx8qx_dcd_1.2GHz.cfg-2GB | 284 ++++++++++++++++++
2 files changed, 284 insertions(+)
rename iMX8QX/{imx8qx_dcd_1.2GHz.cfg => imx8qx_dcd_1.2GHz.cfg-1GB} (100%)
create mode 100644 iMX8QX/imx8qx_dcd_1.2GHz.cfg-2GB
diff --git a/iMX8QX/imx8qx_dcd_1.2GHz.cfg b/iMX8QX/imx8qx_dcd_1.2GHz.cfg
deleted file mode 100644
index abf0ad8..0000000
--- a/iMX8QX/imx8qx_dcd_1.2GHz.cfg
+++ /dev/null
@@ -1,284 +0,0 @@
-#define __ASSEMBLY__
-
-#include <ddrc_mem_map.h>
-#include <ddr_phy_mem_map.h>
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-#ifndef SCFW_DCD
-/* For 1200MHz DDR, DRC 600MHz operation */
-DATA 4 0xff190000 0x00000CC8 /* DRC0 bringup */
-#else
-/* Set the DRC rate to 600MHz, the PHY PLL will double this for the DRAM rate. */
-uint32_t rate2 = SC_600MHZ;
-pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2);
-#endif
-
-DATA 4 0x41C80208 0x1
-DATA 4 0x41C80040 0xb
-DATA 4 0x41C80204 0x1
-
-/* DRAM 0 controller configuration begin */
-DATA 4 DDRC_MSTR_0 0xC1080020 // Set LPDDR4, BL = 16 and active ranks
-DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data
-DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read
-DATA 4 DDRC_RFSHTMG_0 0x0049006C // tREFI, tRFC
-DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us
-DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us
-DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2
-DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13
-DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
-DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin
-DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC
-DATA 4 DDRC_DRAMTMG2_0 0x060E1714 // WL, RL, rd2wr, wr2rd
-DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod
-DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp
-DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke
-DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx
-DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx
-DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD
-DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD
-DATA 4 DDRC_DRAMTMG14_0 0x00000071 // txsr
-DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT
-DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval
-DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat
-DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
-DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat
-DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity
-DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation
-DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max)
-DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en
-DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0
-DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6
-DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated
-DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
-DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
-DATA 4 DDRC_ADDRMAP6_0 0x0F070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12
-DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1
-DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt
-DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0
-
-DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000
-
-DATA 4 DDRC_PWRCTL_0 0x0000010D
-
-DATA 4 0x41c80208 0x1
-DATA 4 0x41c80040 0xf
-DATA 4 0x41c80204 0x1
-
-//-------------------------------------------
-// Configure registers for PHY initialization
-// Timings are computed for 1200MHz DRAM operation
-//--------------------------------------------
-// Set-up DRAM Configuration Register
-DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank
-// Set-up byte and bit swapping registers
-DATA 4 DDR_PHY_PGCR8_0 0x0001000A
-DATA 4 DDR_PHY_DX0DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
-DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
-DATA 4 DDR_PHY_DX1DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
-DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
-DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
-DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
-DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
-DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
-DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
-DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
-// Set-up PHY General Configuration Register
-// PGCR1,4,5,6,7 are untouched
-SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1
-DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy)
-DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD
-DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity
-// Set-up PHY Timing Register
-// PTR2 is untouched
-DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST
-DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST
-// Set-up PLL Control Register
-DATA 4 DDR_PHY_PLLCR0_0 0x001C0000
-DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000
-// Set-up Impedance Control Register
-DATA 4 DDR_PHY_ZQCR_0 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup)
-// ZPROG_DRAM_ODT and ZPROG_HOST_ODT
-DATA 4 DDR_PHY_ZQ0PR0_0 0x1BBBB // Optimal setting based on factory testing
-DATA 4 DDR_PHY_ZQ1PR0_0 0x1B9BB // Optimal setting based on factory testing
-// Set-up PHY Initialization Register
-DATA 4 DDR_PHY_PIR_0 0x32
-// Launch initialization (set bit 0)
-DATA 4 DDR_PHY_PIR_0 0x33
-
-
-//-------------------------------------------
-// Configure registers for DRAM initialization
-//-------------------------------------------
-// Set-up Mode Register
-// MR0, MR3, MR4, MR5 MR6 are untouched
-DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST
-DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL
-DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength
-
-DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT
-DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks)
-/* LPDDR4 mode register writes for CA and DQ VREF settings */
-DATA 4 DDR_PHY_MR12_0 0x48
-DATA 4 DDR_PHY_MR14_0 0x48
-// Set-up DRAM Timing Parameters Register
-// DTPR6 is untouched
-DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP
-DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD
-DATA 4 DDR_PHY_DTPR2_0 0x006960E2 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
-DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
-DATA 4 DDR_PHY_DTPR4_0 0x00D82B0C // tRFC, tWLO, tXP
-DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR
-// Set-up PHY Timing Register
-DATA 4 DDR_PHY_PTR3_0 0x00249F00 // tDINIT0
-DATA 4 DDR_PHY_PTR4_0 0x00000960 // tDINIT1
-DATA 4 DDR_PHY_PTR5_0 0x0003A980 // tDINIT2
-DATA 4 DDR_PHY_PTR6_0 0x027004B0 // tDINIT4, tDINIT3
-
-
-// Set-up ODT Configuration Register
-// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
-DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write
-DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled
-DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write
-DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled
-
-
-// Set-up AC I/O Configuration Register
-// ACIOCR1-4 are untouched
-DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2
-DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4
-// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON.
-DATA 4 DDR_PHY_ACIOCR1_0 0x44000000
-// Set-up VREF Training Control Registers
-DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12
-DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0
-// Set-up DATX8 General Configuration Registers
-// DXnGCR0-4 are untouched
-SET_BIT 4 DDR_PHY_PGCR5_0 0x4
-DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit
-// Set-up DATX8 General Configuration Registers
-DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
-DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
-DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
-DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
-DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
-DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
-DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
-DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
-// Set-up DATX8 DX Control Register 2
-// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA
-DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400
-// Set-up DATX8 IO Control Register
-DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4
-
-#if DDR_TRAIN_IN_DCD
-// Wait PHY initialization end then launch DRAM initialization
-// Wait for bit 0 of PGSR0 to be '1'
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured
-
-// Launch DRAM 0 initialization (set bit 0)
-DATA 4 DDR_PHY_PIR_0 0x180
-DATA 4 DDR_PHY_PIR_0 0x181
-
-// DRAM 0 initialization end
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
-
-// Launch a second time DRAM initialization due to following Synopsys PHY bug:
-// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration"
-// Workaround: "Run DRAM Initialization twice"
-DATA 4 DDR_PHY_PIR_0 0x100
-DATA 4 DDR_PHY_PIR_0 0x101
-
-// Wait (second time) DRAM 0 initialization end
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
-
-//---------------------------------------------------------------//
-// DATA training
-//---------------------------------------------------------------//
-// configure PHY for data training
-// The following register writes are recommended by SNPS prior to running training
-CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift
-SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation
-CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation
-SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1
-// Per SNPS initialize BIST registers for VREF training
-DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16)
-DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC)
-DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC)
-
-// Set-up Data Training Configuration Register
-// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys
-// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training).
-// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED).
-DATA 4 DDR_PHY_DTCR0_0 0x000071C7 // Set DTRPTN to 0x7. RFSHDT=0
-DATA 4 DDR_PHY_DTCR1_0 0x00010236 // Set RANKEN
-
-CLR_BIT 4 DDR_PHY_DX4GCR1_0 0xFF // disable byte 4
-
-// Launch Write leveling
-DATA 4 DDR_PHY_PIR_0 0x200
-DATA 4 DDR_PHY_PIR_0 0x201
-// Wait Write leveling to complete
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000
-
-// Set DQS/DQSn glitch suppression resistor for training PHY0
-DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7
-// Launch Read DQS training
-DATA 4 DDR_PHY_PIR_0 0x400
-DATA 4 DDR_PHY_PIR_0 0x401
-// Wait Read DQS training to complete PHY0
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000
-// Remove DQS/DQSn glitch suppression resistor PHY0
-DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000
-
-// DQS2DQ training, Write leveling, Deskew and eye trainings
-DATA 4 DDR_PHY_PIR_0 0x0010F800
-DATA 4 DDR_PHY_PIR_0 0x0010F801
-// Wait for training to complete
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
-
-// Launch VREF training
-DATA 4 DDR_PHY_PIR_0 0x00020000
-DATA 4 DDR_PHY_PIR_0 0x00020001
-// Wait for training to complete
-CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
-CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00080000
-
-//Re-allow uMCTL2 to send commands to DDR
-CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0
-
-//DQS Drift Registers PHY0
-CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000
-CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000
-CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000
-CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000
-// Enable DQS drift detection PHY0
-DATA 4 DDR_PHY_DQSDR0_0 0x20188005
-DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000
-DATA 4 DDR_PHY_DQSDR2_0 0x00070200
-
-// Enable VT compensation
-CLR_BIT 4 DDR_PHY_PGCR6_0 0x1
-
-//Check that controller is ready to operate
-CHECK_BITS_SET 4 DDRC_STAT_0 0x1
-
-#endif
diff --git a/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express1GB b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express1GB
new file mode 100644
index 0000000..abf0ad8
--- /dev/null
+++ b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express1GB
@@ -0,0 +1,284 @@
+#define __ASSEMBLY__
+
+#include <ddrc_mem_map.h>
+#include <ddr_phy_mem_map.h>
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+#ifndef SCFW_DCD
+/* For 1200MHz DDR, DRC 600MHz operation */
+DATA 4 0xff190000 0x00000CC8 /* DRC0 bringup */
+#else
+/* Set the DRC rate to 600MHz, the PHY PLL will double this for the DRAM rate. */
+uint32_t rate2 = SC_600MHZ;
+pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2);
+#endif
+
+DATA 4 0x41C80208 0x1
+DATA 4 0x41C80040 0xb
+DATA 4 0x41C80204 0x1
+
+/* DRAM 0 controller configuration begin */
+DATA 4 DDRC_MSTR_0 0xC1080020 // Set LPDDR4, BL = 16 and active ranks
+DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data
+DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read
+DATA 4 DDRC_RFSHTMG_0 0x0049006C // tREFI, tRFC
+DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us
+DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us
+DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2
+DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13
+DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
+DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin
+DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC
+DATA 4 DDRC_DRAMTMG2_0 0x060E1714 // WL, RL, rd2wr, wr2rd
+DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod
+DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp
+DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke
+DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx
+DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx
+DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD
+DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD
+DATA 4 DDRC_DRAMTMG14_0 0x00000071 // txsr
+DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT
+DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval
+DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat
+DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
+DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat
+DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity
+DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation
+DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max)
+DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en
+DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0
+DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6
+DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated
+DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
+DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
+DATA 4 DDRC_ADDRMAP6_0 0x0F070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12
+DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1
+DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt
+DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0
+
+DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000
+
+DATA 4 DDRC_PWRCTL_0 0x0000010D
+
+DATA 4 0x41c80208 0x1
+DATA 4 0x41c80040 0xf
+DATA 4 0x41c80204 0x1
+
+//-------------------------------------------
+// Configure registers for PHY initialization
+// Timings are computed for 1200MHz DRAM operation
+//--------------------------------------------
+// Set-up DRAM Configuration Register
+DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank
+// Set-up byte and bit swapping registers
+DATA 4 DDR_PHY_PGCR8_0 0x0001000A
+DATA 4 DDR_PHY_DX0DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
+DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
+DATA 4 DDR_PHY_DX1DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
+DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
+DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
+DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
+DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping
+DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping
+DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
+DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
+// Set-up PHY General Configuration Register
+// PGCR1,4,5,6,7 are untouched
+SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1
+DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy)
+DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD
+DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity
+// Set-up PHY Timing Register
+// PTR2 is untouched
+DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST
+DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST
+// Set-up PLL Control Register
+DATA 4 DDR_PHY_PLLCR0_0 0x001C0000
+DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000
+// Set-up Impedance Control Register
+DATA 4 DDR_PHY_ZQCR_0 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup)
+// ZPROG_DRAM_ODT and ZPROG_HOST_ODT
+DATA 4 DDR_PHY_ZQ0PR0_0 0x1BBBB // Optimal setting based on factory testing
+DATA 4 DDR_PHY_ZQ1PR0_0 0x1B9BB // Optimal setting based on factory testing
+// Set-up PHY Initialization Register
+DATA 4 DDR_PHY_PIR_0 0x32
+// Launch initialization (set bit 0)
+DATA 4 DDR_PHY_PIR_0 0x33
+
+
+//-------------------------------------------
+// Configure registers for DRAM initialization
+//-------------------------------------------
+// Set-up Mode Register
+// MR0, MR3, MR4, MR5 MR6 are untouched
+DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST
+DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL
+DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength
+
+DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT
+DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks)
+/* LPDDR4 mode register writes for CA and DQ VREF settings */
+DATA 4 DDR_PHY_MR12_0 0x48
+DATA 4 DDR_PHY_MR14_0 0x48
+// Set-up DRAM Timing Parameters Register
+// DTPR6 is untouched
+DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP
+DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD
+DATA 4 DDR_PHY_DTPR2_0 0x006960E2 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
+DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
+DATA 4 DDR_PHY_DTPR4_0 0x00D82B0C // tRFC, tWLO, tXP
+DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR
+// Set-up PHY Timing Register
+DATA 4 DDR_PHY_PTR3_0 0x00249F00 // tDINIT0
+DATA 4 DDR_PHY_PTR4_0 0x00000960 // tDINIT1
+DATA 4 DDR_PHY_PTR5_0 0x0003A980 // tDINIT2
+DATA 4 DDR_PHY_PTR6_0 0x027004B0 // tDINIT4, tDINIT3
+
+
+// Set-up ODT Configuration Register
+// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
+DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write
+DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled
+DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write
+DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled
+
+
+// Set-up AC I/O Configuration Register
+// ACIOCR1-4 are untouched
+DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2
+DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4
+// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON.
+DATA 4 DDR_PHY_ACIOCR1_0 0x44000000
+// Set-up VREF Training Control Registers
+DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12
+DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0
+// Set-up DATX8 General Configuration Registers
+// DXnGCR0-4 are untouched
+SET_BIT 4 DDR_PHY_PGCR5_0 0x4
+DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit
+// Set-up DATX8 General Configuration Registers
+DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+// Set-up DATX8 DX Control Register 2
+// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA
+DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400
+// Set-up DATX8 IO Control Register
+DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4
+
+#if DDR_TRAIN_IN_DCD
+// Wait PHY initialization end then launch DRAM initialization
+// Wait for bit 0 of PGSR0 to be '1'
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured
+
+// Launch DRAM 0 initialization (set bit 0)
+DATA 4 DDR_PHY_PIR_0 0x180
+DATA 4 DDR_PHY_PIR_0 0x181
+
+// DRAM 0 initialization end
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
+
+// Launch a second time DRAM initialization due to following Synopsys PHY bug:
+// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration"
+// Workaround: "Run DRAM Initialization twice"
+DATA 4 DDR_PHY_PIR_0 0x100
+DATA 4 DDR_PHY_PIR_0 0x101
+
+// Wait (second time) DRAM 0 initialization end
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
+
+//---------------------------------------------------------------//
+// DATA training
+//---------------------------------------------------------------//
+// configure PHY for data training
+// The following register writes are recommended by SNPS prior to running training
+CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift
+SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation
+CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation
+SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1
+// Per SNPS initialize BIST registers for VREF training
+DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16)
+DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC)
+DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC)
+
+// Set-up Data Training Configuration Register
+// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys
+// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training).
+// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED).
+DATA 4 DDR_PHY_DTCR0_0 0x000071C7 // Set DTRPTN to 0x7. RFSHDT=0
+DATA 4 DDR_PHY_DTCR1_0 0x00010236 // Set RANKEN
+
+CLR_BIT 4 DDR_PHY_DX4GCR1_0 0xFF // disable byte 4
+
+// Launch Write leveling
+DATA 4 DDR_PHY_PIR_0 0x200
+DATA 4 DDR_PHY_PIR_0 0x201
+// Wait Write leveling to complete
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000
+
+// Set DQS/DQSn glitch suppression resistor for training PHY0
+DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7
+// Launch Read DQS training
+DATA 4 DDR_PHY_PIR_0 0x400
+DATA 4 DDR_PHY_PIR_0 0x401
+// Wait Read DQS training to complete PHY0
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000
+// Remove DQS/DQSn glitch suppression resistor PHY0
+DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000
+
+// DQS2DQ training, Write leveling, Deskew and eye trainings
+DATA 4 DDR_PHY_PIR_0 0x0010F800
+DATA 4 DDR_PHY_PIR_0 0x0010F801
+// Wait for training to complete
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
+
+// Launch VREF training
+DATA 4 DDR_PHY_PIR_0 0x00020000
+DATA 4 DDR_PHY_PIR_0 0x00020001
+// Wait for training to complete
+CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
+CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00080000
+
+//Re-allow uMCTL2 to send commands to DDR
+CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0
+
+//DQS Drift Registers PHY0
+CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000
+CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000
+CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000
+CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000
+// Enable DQS drift detection PHY0
+DATA 4 DDR_PHY_DQSDR0_0 0x20188005
+DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000
+DATA 4 DDR_PHY_DQSDR2_0 0x00070200
+
+// Enable VT compensation
+CLR_BIT 4 DDR_PHY_PGCR6_0 0x1
+
+//Check that controller is ready to operate
+CHECK_BITS_SET 4 DDRC_STAT_0 0x1
+
+#endif
diff --git a/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express2GB b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express2GB
diff --git a/iMX8QX/imx8qx_dcd_1.2GHz.cfg b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-1GB
similarity index 100%
rename from iMX8QX/imx8qx_dcd_1.2GHz.cfg
rename to iMX8QX/imx8qx_dcd_1.2GHz.cfg-1GB
diff --git a/iMX8QX/imx8qx_dcd_1.2GHz.cfg-2GB b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-2GB
new file mode 100644
index 0000000..bb37fd5
--- /dev/null
+++ b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-ccimx8x_sbc_express2GB
+++ b/iMX8QX/imx8qx_dcd_1.2GHz.cfg-2GB
@@ -0,0 +1,284 @@
+#define __ASSEMBLY__
+

26
meta-digi-arm/recipes-bsp/imx-mkimage/imx-boot_0.2.bb
View File

@ -37,8 +37,8 @@ DEPENDS_append_mx8mq = " dtc-native"
# that would otherwise be done in the image build as controlled
# by IMAGE_BOOTFILES_DEPENDS and IMAGE_BOOTFILES in image_types_fsl.bbclass
IMX_M4_DEMOS = ""
IMX_M4_DEMOS_mx8qm = "imx-m4-demos:do_deploy"
IMX_M4_DEMOS_mx8qxp = "imx-m4-demos:do_deploy"
IMX_M4_DEMOS_mx8qm = "imx-m4-demos"
IMX_M4_DEMOS_mx8qxp = "imx-m4-demos"
# This package aggregates output deployed by other packages,
# so set the appropriate dependencies
@ -46,10 +46,20 @@ do_compile[depends] += " \
virtual/bootloader:do_deploy \
${@' '.join('%s:do_deploy' % r for r in '${IMX_FIRMWARE}'.split() )} \
imx-atf:do_deploy \
${IMX_M4_DEMOS} \
${@' '.join('%s:do_deploy' % r for r in '${IMX_M4_DEMOS}'.split() )} \
${@bb.utils.contains('COMBINED_FEATURES', 'optee', 'optee-os-imx:do_deploy', '', d)} \
"
# This package aggregates dependencies with other packages,
# so also define the license dependencies.
do_populate_lic[depends] += " \
virtual/bootloader:do_populate_lic \
${@' '.join('%s:do_populate_lic' % r for r in '${IMX_FIRMWARE}'.split() )} \
imx-atf:do_populate_lic \
${@' '.join('%s:do_populate_lic' % r for r in '${IMX_M4_DEMOS}'.split() )} \
${@bb.utils.contains('COMBINED_FEATURES', 'optee', 'optee-os-imx:do_populate_lic', '', d)} \
"
SC_FIRMWARE_NAME ?= "scfw_tcm.bin"
ATF_MACHINE_NAME ?= "bl31-imx8qm.bin"
@ -122,7 +132,7 @@ do_compile () {
cp ${DEPLOY_DIR_IMAGE}/${BOOT_TOOLS}/${SC_FIRMWARE_NAME} ${S}/${SOC_TARGET}/scfw_tcm.bin
cp ${DEPLOY_DIR_IMAGE}/${BOOT_TOOLS}/${ATF_MACHINE_NAME} ${S}/${SOC_TARGET}/bl31.bin
for type in ${UBOOT_CONFIG}; do
cp ${DEPLOY_DIR_IMAGE}/${UBOOT_NAME}-${type} ${S}/${SOC_TARGET}/u-boot.bin-${type}
cp ${DEPLOY_DIR_IMAGE}/${BOOT_TOOLS}/${UBOOT_NAME}-${type} ${S}/${SOC_TARGET}/u-boot.bin-${type}
done
fi
@ -135,7 +145,8 @@ do_compile () {
for type in ${UBOOT_CONFIG}; do
cd ${S}/${SOC_TARGET}
ln -sf u-boot.bin-${type} u-boot.bin
ln -sf ${DCD_SRC_NAME}-${type} ${DCD_SRC_NAME}
RAM_SIZE="$(echo ${type} | sed -e 's,.*\([0-9]\+GB\),\1,g')"
ln -sf ${DCD_SRC_NAME}-${RAM_SIZE} ${DCD_SRC_NAME}
cd -
for target in ${IMXBOOT_TARGETS}; do
echo "building ${SOC_TARGET} - ${type} - ${target}"
@ -167,10 +178,7 @@ DEPLOYDIR_IMXBOOT = "${BOOT_TOOLS}"
do_deploy () {
install -d ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
# copy the tool mkimage to deploy path and sc fw, dcd and uboot
for type in ${UBOOT_CONFIG}; do
install -m 0644 ${DEPLOY_DIR_IMAGE}/${UBOOT_NAME}-${type} ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
done
# copy the tool mkimage to deploy path along with sc fw and dcd
if [ "${SOC_TARGET}" = "iMX8M" ]; then
install -m 0644 ${DEPLOY_DIR_IMAGE}/u-boot-spl.bin-${MACHINE}-${UBOOT_CONFIG} ${DEPLOYDIR}/${DEPLOYDIR_IMXBOOT}
for ddr_firmware in ${DDR_FIRMWARE_NAME}; do

37
meta-digi-arm/recipes-bsp/u-boot/u-boot-dey/ccimx8x-sbc-pro/boot.txt Normal file
View File

@ -0,0 +1,37 @@
#
# U-Boot bootscript for EMMC/SD images created by Yocto.
#
#
# Set device tree filename depending on the board ID (if defined)
#
if test -n "${board_id}"; then
setenv fdt_file Image.gz-ccimx8x-sbc-pro-id${board_id}.dtb
else
#
# Set device tree filename depending on the hardware variant
#
if test "${module_variant}" = "0x01" || test "${module_variant}" = "0x02" || test "${module_variant}" = "0x04"; then
setenv fdt_file Image.gz-ccimx8x-sbc-pro-wb.dtb
elif test "${module_variant}" = "0x03" || test "${module_variant}" = "0x05"; then
setenv fdt_file Image.gz-ccimx8x-sbc-pro.dtb
else
echo "------ Using default fdt_file: $fdt_file"
fi
fi
# Get the UUID of the configured boot partition.
part uuid mmc ${mmcbootdev}:${mmcpart} bootpart
# Check the boot source.
if test "${bootpart}" = "${part1_uuid}"; then
# We are booting from the eMMC using 'linux'.
true
elif test "${bootpart}" = "${part2_uuid}"; then
# We are booting from the eMMC using 'recovery'.
setenv boot_initrd true
setenv initrd_file uramdisk-recovery.img
else
# We are booting from the SD card.
setenv mmcroot /dev/mmcblk${mmcbootdev}p2
fi
dboot linux mmc ${mmcbootdev}:${mmcpart}

170
meta-digi-arm/recipes-bsp/u-boot/u-boot-dey/ccimx8x-sbc-pro/install_linux_fw_sd.txt Normal file
View File

@ -0,0 +1,170 @@
#
# U-Boot script for installing Linux images created by Yocto from the SD
# card into the eMMC
#
echo "############################################################"
echo "# Linux firmware install from micro SD #"
echo "############################################################"
echo ""
echo " This process will erase your eMMC and will install a new"
echo " U-Boot and Linux firmware images on the eMMC."
echo ""
echo " Press CTRL+C now if you wish to abort or wait 10 seconds"
echo " to continue."
sleep 10
if test $? -eq 1; then
echo "Aborted by user.";
exit;
fi
# Determine U-Boot file to program basing on module variant
if test -n "${module_variant}"; then
if test "${module_variant}" = "0x01" || test "${module_variant}" = "0x04" || test "${module_variant}" = "0x05"; then
setenv INSTALL_UBOOT_FILENAME imx-boot-ccimx8x_sbc_pro1GB.bin;
elif test "${module_variant}" = "0x02" || test "${module_variant}" = "0x03"; then
setenv INSTALL_UBOOT_FILENAME imx-boot-ccimx8x_sbc_pro2GB.bin;
fi
fi
# Use 'test -n ...' because 'test -z ...' does not work well on old versions of
# u-boot when the checked value is empty.
if test -n "${INSTALL_UBOOT_FILENAME}"; then
true;
else
echo "";
echo "[ERROR] Cannot determine U-Boot file for this module!";
echo "";
echo "1. Set variable 'INSTALL_UBOOT_FILENAME' depending on your ConnectCore 8X variant:";
echo " - For a QuadXPlus CPU with 1GB DDR3, run:";
echo " => setenv INSTALL_UBOOT_FILENAME imx-boot-ccimx8x_sbc_pro1GB.bin";
echo " - For a QuadXPlus CPU with 2GB DDR3, run:";
echo " => setenv INSTALL_UBOOT_FILENAME imx-boot-ccimx8x_sbc_pro2GB.bin";
echo "";
echo "2. Run the install script again.";
echo "";
echo "Aborted";
echo "";
exit;
fi;
setenv INSTALL_MMCDEV 1
setenv INSTALL_LINUX_FILENAME dey-image-qt-##GRAPHICAL_BACKEND##-ccimx8x-sbc-pro.boot.vfat
setenv INSTALL_RECOVERY_FILENAME dey-image-qt-##GRAPHICAL_BACKEND##-ccimx8x-sbc-pro.recovery.vfat
setenv INSTALL_ROOTFS_FILENAME dey-image-qt-##GRAPHICAL_BACKEND##-ccimx8x-sbc-pro.ext4
# Check for presence of firmware files on the SD card
for install_f in ${INSTALL_UBOOT_FILENAME} ${INSTALL_LINUX_FILENAME} ${INSTALL_RECOVERY_FILENAME} ${INSTALL_ROOTFS_FILENAME}; do
if test ! -e mmc ${INSTALL_MMCDEV} ${install_f}; then
echo "ERROR: Could not find file ${install_f}";
install_abort=1;
fi;
done
if test -n "${install_abort}"; then
echo "Aborted.";
exit;
fi
# Skip user confirmation for U-Boot update
setenv forced_update 1
# Set bootdelay to zero so that firmware update is run immediately after
# the first reset.
setenv bootdelay 0
# Set target MMC device index to eMMC
setenv mmcdev 0
# Update U-Boot
echo ""
echo ""
echo ">> Installing U-Boot boot loader (target will reset)"
echo ""
echo ""
update uboot mmc ${INSTALL_MMCDEV} fat ${INSTALL_UBOOT_FILENAME}
if test $? -eq 1; then
echo "[ERROR] Failed to update U-Boot boot loader!";
echo "";
echo "Aborted.";
exit;
fi
# Set 'bootcmd' to the second part of the script that will
# - Reset environment to defaults
# - Save the environment
# - Force on-the-fly updates to avoid possible verification errors
# - Partition the eMMC user data area for Linux
# - Update the 'linux' partition
# - Update the 'recovery' partition
# - Update the 'rootfs' partition
# - Configure recovery to wipe 'update' partition
# - Disable on-the-fly updates
# - Run 'recovery' and let the system boot after
setenv bootcmd "
env default -a;
saveenv;
setenv otf-update yes;
echo \"\";
echo \"\";
echo \">> Creating Linux partition table on the eMMC\";
echo \"\";
echo \"\";
run partition_mmc_linux;
if test \$? -eq 1; then
echo \"[ERROR] Failed to create Linux partition table!\";
echo \"\";
echo \"Aborted.\";
exit;
fi;
echo \"\";
echo \"\";
echo \">> Installing Linux kernel and device tree files\";
echo \"\";
echo \"\";
update linux mmc ${INSTALL_MMCDEV} fat ${INSTALL_LINUX_FILENAME};
if test \$? -eq 1; then
echo \"[ERROR] Failed to update linux partition!\";
echo \"\";
echo \"Aborted.\";
exit;
fi;
echo \"\";
echo \"\";
echo \">> Installing recovery\";
echo \"\";
echo \"\";
update recovery mmc ${INSTALL_MMCDEV} fat ${INSTALL_RECOVERY_FILENAME};
if test \$? -eq 1; then
echo \"[ERROR] Failed to update recovery partition!\";
echo \"\";
echo \"Aborted.\";
exit;
fi;
echo \"\";
echo \"\";
echo \">> Installing Linux root file system\";
echo \"\";
echo \"\";
update rootfs mmc ${INSTALL_MMCDEV} fat ${INSTALL_ROOTFS_FILENAME};
if test \$? -eq 1; then
echo \"[ERROR] Failed to update rootfs partition!\";
echo \"\";
echo \"Aborted.\";
exit;
fi;
echo \"\";
setenv boot_recovery yes;
setenv recovery_command wipe_update;
setenv otf-update;
saveenv;
echo \"\";
echo \"\";
echo \">> Firmware installation complete. Rebooting into recovery mode for final deployment.\";
echo \"\";
echo \"\";
sleep 1;
reset;
"
saveenv
reset

16
meta-digi-arm/recipes-bsp/u-boot/u-boot-dey/use-mainline-bsp/boot.txt Normal file
View File

@ -0,0 +1,16 @@
#
# U-Boot bootscript for NAND images created by Yocto.
#
if test "${board}" = "ccimx6ulsbc"; then
setenv fdt_file zImage-imx6ul-ccimx6ulsbcpro.dtb
else
setenv fdt_file zImage-imx6ul-ccimx6ulsbcexpress.dtb
fi
if test "${mtdbootpart}" = "recovery"; then
setenv boot_initrd true
setenv initrd_file uramdisk-recovery.img
else
true
fi
dboot linux nand ${mtdbootpart}

9
meta-digi-arm/recipes-bsp/u-boot/u-boot-dey_2017.03.bb
View File

@ -169,4 +169,13 @@ do_deploy_append() {
rm -f ${TMP_BOOTSCR}
}
BOOT_TOOLS = "imx-boot-tools"
do_deploy_append_ccimx8x() {
# Move all U-Boot artifacts to the imx-boot-tools folder
# U-Boot images are not bootable on the i.MX8X
install -d ${DEPLOYDIR}/${BOOT_TOOLS}
mv ${DEPLOYDIR}/u-boot* ${DEPLOYDIR}/${BOOT_TOOLS}/
}
COMPATIBLE_MACHINE = "(ccimx6$|ccimx6ul|ccimx8x)"

1
meta-digi-arm/recipes-core/udev/udev-extraconf/imx/blacklist.conf Normal file
View File

@ -0,0 +1 @@
blacklist evbug

8
meta-digi-arm/recipes-core/udev/udev-extraconf_1.1.bbappend
View File

@ -1,4 +1,4 @@
# Copyright (C) 2013-2017 Digi International.
# Copyright (C) 2013-2018 Digi International.
FILESEXTRAPATHS_prepend := "${THISDIR}/${BPN}:"
@ -6,6 +6,7 @@ SRC_URI += " \
file://mount_bootparts.sh \
file://mount_partition.sh \
file://81-spi-spidev.rules \
file://blacklist.conf \
"
do_install_append() {
@ -20,7 +21,12 @@ do_install_append() {
"KERNEL==\"${BT_TTY}\", MODE=\"0660\", GROUP=\"dialout\", SYMLINK+=\"ttyBt\"" \
>> ${D}${sysconfdir}/udev/rules.d/localextra.rules
fi
install -d ${D}${sysconfdir}/modprobe.d
install -m 0644 ${WORKDIR}/blacklist.conf ${D}${sysconfdir}/modprobe.d
}
FILES_${PN}_append = " ${sysconfdir}/modprobe.d"
# BT_TTY is machine specific (defined in machine config file)
PACKAGE_ARCH = "${MACHINE_ARCH}"

8
meta-digi-arm/recipes-digi/mca/mca-tool_1.13.bb → meta-digi-arm/recipes-digi/mca/mca-tool_1.14.bb
View File

@ -8,13 +8,13 @@ PKGNAME = "mca_tool"
# ARM tarball
SRC_URI_arm = "${DIGI_PKG_SRC}/${PKGNAME}-${PV}-${TUNE_ARCH}.tar.gz;name=arm"
SRC_URI[arm.md5sum] = "5ed2579b9e3e5bcb2bc10a8082f8be2b"
SRC_URI[arm.sha256sum] = "cfdb464893e02e37f5baaf9f08ac0fb8943a9a70a8fea6737d1b65c659ed9c42"
SRC_URI[arm.md5sum] = "a9c9e4bbafa65b8140def4db60518a61"
SRC_URI[arm.sha256sum] = "70bae34b602573547cd6f9c6a738aaef4f90c03ce7a97b4d54013b20acbf9a45"
# AARCH64 tarball
SRC_URI_aarch64 = "${DIGI_PKG_SRC}/${PKGNAME}-${PV}-${TUNE_ARCH}.tar.gz;name=aarch64"
SRC_URI[aarch64.md5sum] = "9b6c4768205dda0444e04431245881d5"
SRC_URI[aarch64.sha256sum] = "a5e5947d62a6199afeeff74d48eb5b1c08a7f8836c84468b41e9f51773b54122"
SRC_URI[aarch64.md5sum] = "ccde3a7d4981e179b271a3ce258c036c"
SRC_URI[aarch64.sha256sum] = "da6e9710dd4ff07451cbd1e6f7961f42e97a1c6c0f8b25141be48b229aa9b5a8"
S = "${WORKDIR}/${PKGNAME}-${PV}"

11
meta-digi-arm/recipes-kernel/linux/linux-4.18.y.bb Normal file
View File

@ -0,0 +1,11 @@
# Copyright (C) 2018 Digi International
require recipes-kernel/linux/linux-dey.inc
SRCBRANCH = "v4.18.y"
SRCREV = "${AUTOREV}"
DEPENDS += "openssl-native"
HOST_EXTRACFLAGS += "-I${STAGING_INCDIR_NATIVE}"
COMPATIBLE_MACHINE = "(ccimx6ul)"

1
meta-digi-arm/recipes-kernel/linux/linux-dey.inc
View File

@ -3,6 +3,7 @@
SUMMARY = "Linux kernel for Digi boards"
LICENSE = "GPLv2"
LIC_FILES_CHKSUM = "file://COPYING;md5=d7810fab7487fb0aad327b76f1be7cd7"
LIC_FILES_CHKSUM_use-mainline-bsp = "file://COPYING;md5=bbea815ee2795b2f4230826c0c6b8814"
DEPENDS += "lzop-native bc-native"
DEPENDS += "${@base_conditional('TRUSTFENCE_SIGN', '1', 'trustfence-sign-tools-native', '', d)}"

2
meta-digi-dey/conf/distro/dey.conf
View File

@ -1,6 +1,6 @@
DISTRO = "dey"
DISTRO_NAME = "Digi Embedded Yocto"
DISTRO_VERSION = "2.4-r2-beta"
DISTRO_VERSION = "2.4-r2"
DISTRO_CODENAME = "rocko"
SDK_VENDOR = "-deysdk"
SDK_VERSION := "${@'${DISTRO_VERSION}'}"

215
meta-digi-dey/recipes-aws/greengrass/greengrass_1.6.0.bb Normal file
View File

@ -0,0 +1,215 @@
# Copyright (C) 2018, Digi International Inc.
SUMMARY = "AWS IoT Greengrass core"
HOMEPAGE = "https://aws.amazon.com/greengrass/"
#
# The package includes different licenses:
#
# [Apache-2.0]
# ggc/core/LICENSE/attributions/github_aws_aws_sdk_go_License.txt
# ggc/core/LICENSE/attributions/github_coreos_go_systemd_License.txt
# ggc/core/LICENSE/attributions/github_docker_docker_License.txt
# ggc/core/LICENSE/attributions/github_docker_go_units_License.txt
# ggc/core/LICENSE/attributions/github_go_ini_ini_License.txt
# ggc/core/LICENSE/attributions/github_jmespath_go_jmespath_License.txt
# ggc/core/LICENSE/attributions/github_opencontainers_runc_License.txt
# ggc/core/LICENSE/attributions/github_opencontainers_runtime_spec_License.txt
# ggc/core/LICENSE/attributions/github_pquerna_ffjson_License.txt
# ggc/core/LICENSE/attributions/github_vishvananda_netlink_License.txt
# [BSD-2-Clause]
# ggc/core/LICENSE/attributions/github_godbus_dbus_License.txt
# ggc/core/LICENSE/attributions/github_huin_gobinarytest_License.txt
# ggc/core/LICENSE/attributions/github_seccomp_libseccomp_golang_License.txt
# ggc/core/LICENSE/attributions/github_syndtr_gocapability_License.txt
# [BSD-3-Clause]
# ggc/core/LICENSE/attributions/github_fsnotify_fsnotify_License.txt
# ggc/core/LICENSE/attributions/github_golang_protobuf_License.txt
# ggc/core/LICENSE/attributions/github_jeffallen_mqtt_License.txt
# ggc/core/LICENSE/attributions/Golang_License.txt
# [ECLIPSE]
# ggc/core/LICENSE/attributions/github_paho_mqtt_License.txt
# [MIT]
# ggc/core/LICENSE/attributions/github_huin_mqtt_License.txt
# ggc/core/LICENSE/attributions/github_mattn_go_sqlite3_License.txt
# ggc/core/LICENSE/attributions/github_nu7hatch_gouuid_License.txt
# ggc/core/LICENSE/attributions/github_Sirupsen_logrus_License.txt
# ggc/core/LICENSE/attributions/github_urfave_cli_License.txt
# [Proprietary]
# ggc/core/LICENSE/Greengrass AWS SW License (IoT additiona) vr6.txt
# [Copyright-Only Decication]
# ggc/core/LICENSE/attributions/libb64_sourceforge_License.txt
LICENSE = "Apache-2.0 | BSD-2-Clause | BSD-3-Clause | MIT | PD | Proprietary"
LIC_FILES_CHKSUM = " \
file://ggc/core/LICENSE/attributions/curl_haxx_se_License.txt;md5=3b77a99e8530d6c9ccc9aab9a7436f99 \
file://ggc/core/LICENSE/attributions/github_aws_aws_sdk_go_License.txt;md5=d273d63619c9aeaf15cdaf76422c4f87 \
file://ggc/core/LICENSE/attributions/github_coreos_go_systemd_License.txt;md5=715f3348ed8b9bf4fac3b08133384a4d \
file://ggc/core/LICENSE/attributions/github_docker_docker_License.txt;md5=bba4ee48af378e39b452d742d29c710b \
file://ggc/core/LICENSE/attributions/github_docker_go_units_License.txt;md5=bb99db20f1c48c2c4952c27c72855e36 \
file://ggc/core/LICENSE/attributions/github_fsnotify_fsnotify_License.txt;md5=c38914c9a7ab03bb2b96d4baaee10769 \
file://ggc/core/LICENSE/attributions/github_godbus_dbus_License.txt;md5=b03a62440372a9acf9692ad365932c87 \
file://ggc/core/LICENSE/attributions/github_go_ini_ini_License.txt;md5=715f3348ed8b9bf4fac3b08133384a4d \
file://ggc/core/LICENSE/attributions/github_golang_protobuf_License.txt;md5=16fe162f7848190010b6ec7bfaac030a \
file://ggc/core/LICENSE/attributions/github_huin_gobinarytest_License.txt;md5=f2b3138d9d314bccf5297dea7e3e6d14 \
file://ggc/core/LICENSE/attributions/github_huin_mqtt_License.txt;md5=12fd125064676697934b7d8c09bed0e8 \
file://ggc/core/LICENSE/attributions/github_jeffallen_mqtt_License.txt;md5=b7269d52765d477e10f319c19d8a9d33 \
file://ggc/core/LICENSE/attributions/github_jmespath_go_jmespath_License.txt;md5=640d33f0070c9dc3a194d2ed7db02974 \
file://ggc/core/LICENSE/attributions/github_mattn_go_sqlite3_License.txt;md5=948f36a2300ac729e60416063190f664 \
file://ggc/core/LICENSE/attributions/github_nu7hatch_gouuid_License.txt;md5=6b18748dcc29fda05fa5aaef44d517fd \
file://ggc/core/LICENSE/attributions/github_opencontainers_runc_License.txt;md5=587c01b2dcc5dc3b4bed51b918c64731 \
file://ggc/core/LICENSE/attributions/github_opencontainers_runtime_spec_License.txt;md5=ef95ed297310c3d09ba16c06d5e161a5 \
file://ggc/core/LICENSE/attributions/github_paho_mqtt_License.txt;md5=655315b482a5955efb91d34de332ee48 \
file://ggc/core/LICENSE/attributions/github_pquerna_ffjson_License.txt;md5=d273d63619c9aeaf15cdaf76422c4f87 \
file://ggc/core/LICENSE/attributions/github_seccomp_libseccomp_golang_License.txt;md5=9205c4c469bfb9d3a63f346539ee445b \
file://ggc/core/LICENSE/attributions/github_Sirupsen_logrus_License.txt;md5=29baae91637760ae68feb57ca93e5a0a \
file://ggc/core/LICENSE/attributions/github_syndtr_gocapability_License.txt;md5=321f58fa53a0b1bb9a887f14660d436b \
file://ggc/core/LICENSE/attributions/github_urfave_cli_License.txt;md5=f1f14a2449300559aed90bedc36a71ed \
file://ggc/core/LICENSE/attributions/github_vishvananda_netlink_License.txt;md5=c95fd0efd62139c155e956a448df8fd6 \
file://ggc/core/LICENSE/attributions/Golang_License.txt;md5=3d7ed06383c65a3161b36c6a0b0b98f5 \
file://ggc/core/LICENSE/attributions/libb64_sourceforge_License.txt;md5=0f8f14bb84b17652f29aad01072e545f \
file://ggc/core/LICENSE/attributions/sqlite_org_License.txt;md5=380e2694a297aa32879ca2ae9c6c029b\
"
# Bitbake does not support spaces in filenames, but GG License does have spaces,
# so workaround the problem by renaming the file before using it.
GG_LIC_FILENAME = "Greengrass AWS SW License (IoT additional) vr6.txt"
GG_LIC_FILENAME_NOSPACES = "${@d.getVar('GG_LIC_FILENAME', True).replace(' ','_')}"
LIC_FILES_CHKSUM += "file://ggc/core/LICENSE/${GG_LIC_FILENAME_NOSPACES};md5=7df5bf535d02b2f83c260250fe330b6c"
SRC_URI_arm = " \
http:///not/exist/greengrass-linux-armv7l-${PV}.tar.gz;name=arm \
file://greengrass-init \
"
SRC_URI[arm.md5sum] = "93ae820af2bf2527bafdb34598d174ed"
SRC_URI[arm.sha256sum] ="8fe99ba17917df2e192b7065e400e2dc85c4a0fbf7654fa0d141642cde92d88f"
SRC_URI_aarch64 = " \
http:///not/exist/greengrass-linux-aarch64-${PV}.tar.gz;name=aarch64 \
file://greengrass-init \
"
# For ARCH64 we use another tarball.
SRC_URI[aarch64.md5sum] = "e4ec6dba43dcba4d2ec1b04d7c851cd3"
SRC_URI[aarch64.sha256sum] ="f45e502435850fb9a9931a46fd96329f95f53ff2d6d5aaa4bed11094c0237f4c"
GG_TARBALL_LOCAL_PATH ?= ""
# The tarball is only available for downloading after registration, so provide
# a PREMIRROR to a local directory that can be configured in the project's
# local.conf file using GG_TARBALL_LOCAL_PATH variable.
python() {
gg_tarball_local_path = d.getVar('GG_TARBALL_LOCAL_PATH', True)
if gg_tarball_local_path:
premirrors = d.getVar('PREMIRRORS', True)
d.setVar('PREMIRRORS', "http:///not/exist/greengrass.* file://%s \\n %s" % (gg_tarball_local_path, premirrors))
}
S = "${WORKDIR}/${BPN}"
inherit aws-iot update-rc.d useradd
GG_USESYSTEMD = "${@bb.utils.contains('DISTRO_FEATURES', 'systemd', 'yes', 'no', d)}"
# Rename GG license file
do_unpack[postfuncs] += "rename_license"
rename_license() {
cd ${S}/ggc/core/LICENSE/
mv "${GG_LIC_FILENAME}" "${GG_LIC_FILENAME_NOSPACES}"
}
# Disable tasks not needed for the binary package
do_configure[noexec] = "1"
do_compile[noexec] = "1"
do_install() {
install -d ${D}/${BPN}
tar --no-same-owner --exclude='./patches' --exclude='./.pc' -cpf - -C ${S} . \
| tar --no-same-owner -xpf - -C ${D}/${BPN}
# Install wrapper bootscript to launch Greengrass core on boot
install -d ${D}${sysconfdir}/init.d
install -m 0755 ${WORKDIR}/greengrass-init ${D}${sysconfdir}/init.d/greengrass
sed -i -e "s,##GG_INSTALL_DIR##,/${BPN},g" ${D}${sysconfdir}/init.d/greengrass
# If certificates do exist, install them and update the config file
if [ -f "${AWS_IOT_CERTS_DIR}/${AWS_GGCORE_ROOT_CA}" ] && \
[ -f "${AWS_IOT_CERTS_DIR}/${AWS_GGCORE_CERTIFICATE}" ] && \
[ -f "${AWS_IOT_CERTS_DIR}/${AWS_GGCORE_PRIVATE_KEY}" ]; then
install -m 0644 "${AWS_IOT_CERTS_DIR}/${AWS_GGCORE_ROOT_CA}" \
"${AWS_IOT_CERTS_DIR}/${AWS_GGCORE_CERTIFICATE}" \
"${AWS_IOT_CERTS_DIR}/${AWS_GGCORE_PRIVATE_KEY}" \
${D}/${BPN}/certs/
sed -i -e "s,\[ROOT_CA_PEM_HERE],${AWS_GGCORE_ROOT_CA},g" \
-e "s,\[CLOUD_PEM_CRT_HERE],${AWS_GGCORE_CERTIFICATE},g" \
-e "s,\[CLOUD_PEM_KEY_HERE],${AWS_GGCORE_PRIVATE_KEY},g" \
${D}/${BPN}/config/config.json
fi
# Configure the rest of GG Core parameters
[ -n "${AWS_GGCORE_THING_ARN}" ] && sed -i -e "s,\[THING_ARN_HERE],${AWS_GGCORE_THING_ARN},g" ${D}/${BPN}/config/config.json
if [ -n "${AWS_GGCORE_IOT_HOST}" ]; then
AWS_GGCORE_HOST_PREFIX="$(echo ${AWS_GGCORE_IOT_HOST} | sed -e 's,\([^.]\+\)\.iot.*,\1,g')"
AWS_GGCORE_REGION="$(echo ${AWS_GGCORE_IOT_HOST} | sed -e 's,.*.iot\.\([^.]\+\)\..*,\1,g')"
[ -n "${AWS_GGCORE_HOST_PREFIX}" ] && sed -i -e "s,\[HOST_PREFIX_HERE],${AWS_GGCORE_HOST_PREFIX},g" ${D}/${BPN}/config/config.json
[ -n "${AWS_GGCORE_REGION}" ] && sed -i -e "s,\[AWS_REGION_HERE],${AWS_GGCORE_REGION},g" ${D}/${BPN}/config/config.json
fi
# Configure whether to use systemd or not
sed -i -e "/useSystemd/{s,\[yes|no],${GG_USESYSTEMD},g}" ${D}/${BPN}/config/config.json
}
pkg_postinst_${PN}() {
# Enable protection for hardlinks and symlinks
if ! grep -qs 'protected_.*links' $D${sysconfdir}/sysctl.conf; then
cat >> $D${sysconfdir}/sysctl.conf <<-_EOF_
# Greengrass: protect hardlinks/symlinks
fs.protected_hardlinks = 1
fs.protected_symlinks = 1
_EOF_
fi
# Customize '/etc/fstab'
if [ -f "$D${sysconfdir}/fstab" ]; then
# Disable TMPFS /var/volatile
sed -i -e '\#^tmpfs[[:blank:]]\+/var/volatile#s,^,#,g' $D${sysconfdir}/fstab
# Mount a cgroup hierarchy with all available subsystems
if ! grep -qs '^cgroup' $D${sysconfdir}/fstab; then
cat >> $D${sysconfdir}/fstab <<-_EOF_
# Greengrass: mount cgroups
cgroup /sys/fs/cgroup cgroup defaults 0 0
_EOF_
fi
fi
# Disable '/etc/resolv.conf' symlink
if [ -f "$D${sysconfdir}/default/volatiles/00_core" ]; then
sed -i -e '/resolv.conf/d' $D${sysconfdir}/default/volatiles/00_core
cat >> $D${sysconfdir}/default/volatiles/00_core <<-_EOF_
# Greengrass: create a real (no symlink) resolv.conf
f root root 0644 /etc/resolv.conf none
_EOF_
fi
}
FILES_${PN} = "/${BPN} ${sysconfdir}"
CONFFILES_${PN} += "/${BPN}/config/config.json"
INITSCRIPT_NAME = "greengrass"
INITSCRIPT_PARAMS = "defaults 80 20"
USERADD_PACKAGES = "${PN}"
GROUPADD_PARAM_${PN} = "-r ggc_group"
USERADD_PARAM_${PN} = "-r -M -N -g ggc_group -s /bin/false ggc_user"
#
# Disable failing QA checks:
#
# Binary was already stripped
# No GNU_HASH in the elf binary
#
INSANE_SKIP_${PN} += "already-stripped ldflags file-rdeps"
RDEPENDS_${PN} += "ca-certificates python-argparse python-json python-numbers sqlite3"

74
meta-digi-dey/recipes-connectivity/bluez/bluez5-5.41/0012-QCA_bluetooth_chip_support.patch
View File

@ -1,11 +1,4 @@
Add hciattach rome support for Qualcomm chip QCA6564
This is a multiple patch including all the specific qualcomm commits to add
support for its chip in bluez stack (hciattach rome).
Signed-off-by: Isaac Hermida <isaac.hermida@digi.com>
From e6d2fb7efcde66f9ab22a42bd6d7039a4f0c02cd Mon Sep 17 00:00:00 2001
From 64912e658db8883637afd298b0a8eda1f49b056a Mon Sep 17 00:00:00 2001
From: Anantha Krishnan <ananthk@codeaurora.org>
Date: Tue, 19 Aug 2014 20:23:01 +0530
Subject: [PATCH 01/19] bluetooth : Add bluetooth support for QCA6174 chip.
@ -22,10 +15,10 @@ Signed-off-by: Rupesh Tatiya <rtatiya@codeaurora.org>
---
Makefile.tools | 3 +-
tools/hciattach.c | 25 +-
tools/hciattach.h | 8 +-
tools/hciattach.h | 3 +
tools/hciattach_rome.c | 1578 ++++++++++++++++++++++++++++++++++++++++++++++++
tools/hciattach_rome.h | 317 ++++++++++
5 files changed, 1926 insertions(+), 5 deletions(-)
5 files changed, 1924 insertions(+), 2 deletions(-)
create mode 100644 tools/hciattach_rome.c
create mode 100644 tools/hciattach_rome.h
@ -142,24 +135,19 @@ index fad176c9b804..73811d4c4c2a 100644
return 0;
}
diff --git a/tools/hciattach.h b/tools/hciattach.h
index 4279a3361749..0656a845223c 100644
index 4279a3361749..93577e9474de 100644
--- a/tools/hciattach.h
+++ b/tools/hciattach.h
@@ -39,9 +39,10 @@
#define HCI_UART_H4DS 3
#define HCI_UART_LL 4
#define HCI_UART_ATH3K 5
-#define HCI_UART_INTEL 6
-#define HCI_UART_BCM 7
-#define HCI_UART_QCA 8
+#define HCI_UART_IBS 6
+#define HCI_UART_INTEL 7
+#define HCI_UART_BCM 8
+#define HCI_UART_QCA 9
@@ -43,6 +43,8 @@
#define HCI_UART_BCM 7
#define HCI_UART_QCA 8
+#define HCI_UART_IBS 12
+
#define HCI_UART_RAW_DEVICE 0
#define HCI_UART_RESET_ON_INIT 1
@@ -63,6 +64,7 @@ int ath3k_init(int fd, int speed, int init_speed, char *bdaddr,
#define HCI_UART_CREATE_AMP 2
@@ -63,6 +65,7 @@ int ath3k_init(int fd, int speed, int init_speed, char *bdaddr,
struct termios *ti);
int ath3k_post(int fd, int pm);
int qualcomm_init(int fd, int speed, struct termios *ti, const char *bdaddr);
@ -2075,7 +2063,7 @@ index 000000000000..aa59965643ec
+};
+#endif /* HW_ROME_H */
From 333676e63694e137558e7a685d2fa1a50c499436 Mon Sep 17 00:00:00 2001
From f84a56a539fa5f37b1a8262520bf4ab7f503cc17 Mon Sep 17 00:00:00 2001
From: Anantha Krishnan <ananthk@codeaurora.org>
Date: Thu, 11 Sep 2014 19:20:02 +0530
Subject: [PATCH 02/19] bluetooth: Enable bluetooth low power mode
@ -2106,7 +2094,7 @@ index 73811d4c4c2a..e3a915061440 100644
/* QUALCOMM BTS */
From 0518592a10bff2ac0b99e4081bd01154f2eeacb6 Mon Sep 17 00:00:00 2001
From 05c8c51fbdce151bcd050a8b742c3af7ba175ceb Mon Sep 17 00:00:00 2001
From: Anantha Krishnan <ananthk@codeaurora.org>
Date: Thu, 11 Sep 2014 18:57:45 +0530
Subject: [PATCH 03/19] bluetooth: Fix bug in firmware parsing mechanism
@ -2159,7 +2147,7 @@ index aa59965643ec..07127f30a70a 100644
union{
tlv_patch_hdr patch;
From 78f1ab9c20956f4e6f009d7bc2b94fe1d4474a08 Mon Sep 17 00:00:00 2001
From 480096d50d5cad31650380470f9c7f7e783f38e4 Mon Sep 17 00:00:00 2001
From: Anantha Krishnan <ananthk@codeaurora.org>
Date: Mon, 8 Sep 2014 15:11:02 +0530
Subject: [PATCH 04/19] bluetooth: Configure BD Address
@ -2275,7 +2263,7 @@ index 07127f30a70a..a4abe9f73080 100644
typedef enum {
USERIAL_OP_FLOW_ON,
From 7f148243e9d36427734de874f291911e1f3d60d0 Mon Sep 17 00:00:00 2001
From 91decff6ed724123a182f4ca0514b7e55b2b5d0f Mon Sep 17 00:00:00 2001
From: Anantha Krishnan <ananthk@codeaurora.org>
Date: Mon, 8 Sep 2014 14:33:24 +0530
Subject: [PATCH 05/19] bluetooth: Remove unused functions in the firmware
@ -2350,7 +2338,7 @@ index 947e1abb96c4..4fcbdf2ab82a 100644
int rome_set_baudrate_req(int fd)
{
From 175fe3690522afc91f38933f821e4b00bd1a12c8 Mon Sep 17 00:00:00 2001
From ec990e2f5c62417dc32cc3f23af3c5861f815837 Mon Sep 17 00:00:00 2001
From: Anantha Krishnan <ananthk@codeaurora.org>
Date: Mon, 8 Sep 2014 14:31:18 +0530
Subject: [PATCH 06/19] bluetooth: Enable 3Mbps baud rate support
@ -2502,7 +2490,7 @@ index 4fcbdf2ab82a..d0e2935b9997 100644
/* Perform HCI reset here*/
err = rome_hci_reset_req(fd);
From 1911a9d5799d110a7d010e154b44e43c65e838ff Mon Sep 17 00:00:00 2001
From 4acc26e112f003c23f2997f98e0e84e1875c37b1 Mon Sep 17 00:00:00 2001
From: Anantha Krishnan <ananthk@codeaurora.org>
Date: Tue, 30 Sep 2014 12:13:00 +0530
Subject: [PATCH 07/19] bluetooth: Check TTY buffer for data availability
@ -2693,7 +2681,7 @@ index a4abe9f73080..3efb71995c45 100644
#define ROME_1_0_100022_1 0x101000221
#define ROME_1_0_100019 0x101000190
From 9d81b1dd643966ba6f2ffb3f7658a24cfcb37df4 Mon Sep 17 00:00:00 2001
From 1f7fb6f953b1714d574181e6ae6b7b281288c0de Mon Sep 17 00:00:00 2001
From: Anantha Krishnan <ananthk@codeaurora.org>
Date: Wed, 20 Aug 2014 12:13:19 +0530
Subject: [PATCH 08/19] bluetooth : Add support for TUFEELO firmware download
@ -2739,7 +2727,7 @@ index 3efb71995c45..9d18c576fcae 100644
/******************************************************************************
** Local type definitions
From ac12a2a733ad6cc6eed8ccdd3462d1fe1969fc54 Mon Sep 17 00:00:00 2001
From f1594502b2627691bf519fe163e655a3d8755e4f Mon Sep 17 00:00:00 2001
From: Anantha Krishnan <ananthk@codeaurora.org>
Date: Mon, 8 Dec 2014 14:52:16 +0530
Subject: [PATCH 09/19] bluetooth: Add support for ROME 3.2 SOC.
@ -2977,7 +2965,7 @@ index 9d18c576fcae..77e85e7e7b19 100644
};
#endif /* HW_ROME_H */
From f7cc3b22522cfc66a7c4126630c6222f22be17f6 Mon Sep 17 00:00:00 2001
From 4980bd625c8eab2240e7e754f2b7be99ab679fcb Mon Sep 17 00:00:00 2001
From: Anantha Krishnan <ananthk@codeaurora.org>
Date: Thu, 4 Dec 2014 17:23:58 +0530
Subject: [PATCH 10/19] bluetooth: Use correct TTY ioctl calls for flow control
@ -3168,7 +3156,7 @@ index 77e85e7e7b19..ef3647e6a69b 100644
unsigned char vnd_local_bd_addr[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
typedef enum {
From bd7d1fce8de4639445563442a8448468d671fad2 Mon Sep 17 00:00:00 2001
From c42651fe738f2ce0740016fcc885bb79a1909021 Mon Sep 17 00:00:00 2001
From: Anantha Krishnan <ananthk@codeaurora.org>
Date: Tue, 20 Jan 2015 12:43:20 +0530
Subject: [PATCH 11/19] bluetooth: Add support for multi baud rate
@ -3199,10 +3187,10 @@ index c3cf10843303..dda639cabca3 100644
static int qualcomm(int fd, struct uart_t *u, struct termios *ti)
diff --git a/tools/hciattach.h b/tools/hciattach.h
index 0656a845223c..49e59321fcac 100644
index 93577e9474de..5255251448d6 100644
--- a/tools/hciattach.h
+++ b/tools/hciattach.h
@@ -64,7 +64,7 @@ int ath3k_init(int fd, int speed, int init_speed, char *bdaddr,
@@ -65,7 +65,7 @@ int ath3k_init(int fd, int speed, int init_speed, char *bdaddr,
struct termios *ti);
int ath3k_post(int fd, int pm);
int qualcomm_init(int fd, int speed, struct termios *ti, const char *bdaddr);
@ -3426,7 +3414,7 @@ index ef3647e6a69b..1500ddd3a79f 100644
#define FALSE 0
#endif
From 7dc9c5e316aa9a22899259ce296136b2e257735d Mon Sep 17 00:00:00 2001
From c3e7808efa573974bf7d7d5fb08766b140dbe8f3 Mon Sep 17 00:00:00 2001
From: Kamal Negi <kamaln@codeaurora.org>
Date: Tue, 30 Dec 2014 19:15:08 +0530
Subject: [PATCH 12/19] Override PCM Settings by reading configuration file
@ -3572,7 +3560,7 @@ index 1500ddd3a79f..f591c10e4f2b 100644
** Local type definitions
******************************************************************************/
From 9eb8220969598d63be3b918b49b6258387629bf3 Mon Sep 17 00:00:00 2001
From e435ae1aa83440aaee7833c8ebce438065168f76 Mon Sep 17 00:00:00 2001
From: Rupesh Tatiya <rtatiya@codeaurora.org>
Date: Thu, 29 Jan 2015 15:36:27 +0530
Subject: [PATCH 13/19] Add support for Tufello 1.1 SOC
@ -3743,7 +3731,7 @@ index f591c10e4f2b..95d5f1e8a5c2 100644
};
#endif /* HW_ROME_H */
From f55d710cf43d008e42ce06ead49dc0dfbf97d3a1 Mon Sep 17 00:00:00 2001
From f09f6d7675062407b904fb85348249b09425bbed Mon Sep 17 00:00:00 2001
From: Anantha Krishnan <ananthk@codeaurora.org>
Date: Wed, 4 Feb 2015 12:29:07 +0530
Subject: [PATCH 14/19] bluetooth: Vote UART CLK ON prior to firmware download
@ -3819,7 +3807,7 @@ index 95d5f1e8a5c2..20264f9978d9 100644
unsigned char vnd_local_bd_addr[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
typedef enum {
From b09f8b12c937ec58df0581b2d95493e036c86432 Mon Sep 17 00:00:00 2001
From 96e0dfef4073e19927d1a5c3e45b91fc0a7a3827 Mon Sep 17 00:00:00 2001
From: Kamal Negi <kamaln@codeaurora.org>
Date: Thu, 30 Apr 2015 15:53:06 +0530
Subject: [PATCH 15/19] Override IBS settings by reading configuration file
@ -3948,7 +3936,7 @@ index 20264f9978d9..8eaeeed8bc96 100644
** Local type definitions
******************************************************************************/
From b307659dc988054c1fef32c131417cfab2b74c3e Mon Sep 17 00:00:00 2001
From 30168b14444dad98babe8e0dc4474bb1947e60e6 Mon Sep 17 00:00:00 2001
From: Dibyendu Roy <dibyen@codeaurora.org>
Date: Fri, 22 May 2015 18:57:05 +0530
Subject: [PATCH 16/19] bluetooth: Fix flow control operation
@ -4002,7 +3990,7 @@ index 8eaeeed8bc96..3fdaf208e522 100644
#define USERIAL_OP_CLK_OFF 0x5442
From bec6be1174e250c60b48b51933ab6f80a27a093e Mon Sep 17 00:00:00 2001
From ed48ba0a9558ea9e0025210ade514e86579e0801 Mon Sep 17 00:00:00 2001
From: Dibyendu Roy <dibyen@codeaurora.org>
Date: Thu, 11 Jun 2015 12:07:43 +0530
Subject: [PATCH 17/19] Adding MDM specific code under _PLATFORM_MDM_
@ -4069,7 +4057,7 @@ index 3fdaf208e522..89f7db3bef86 100644
unsigned char vnd_local_bd_addr[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
typedef enum {
From 5ab2a193c11eaa8a68a0e060a560a5bd2ee2459c Mon Sep 17 00:00:00 2001
From 73225f2554d77df772d026475d27413161f5aaa6 Mon Sep 17 00:00:00 2001
From: Dibyendu Roy <dibyen@codeaurora.org>
Date: Mon, 6 Jul 2015 13:30:53 +0530
Subject: [PATCH 18/19] Bluetooth: Fix static analysis issues
@ -4108,7 +4096,7 @@ index 1891de24e21a..59bdc16e4e8f 100644
total_segment = tlv_size/MAX_SIZE_PER_TLV_SEGMENT;
From ca52faad6e23bee353e3315f136efb43d1e9d143 Mon Sep 17 00:00:00 2001
From cba902ee7f1d78e8b46d0ce7e2243b2d9dddf063 Mon Sep 17 00:00:00 2001
From: Kamal Negi <kamaln@codeaurora.org>
Date: Fri, 8 May 2015 15:01:02 +0530
Subject: [PATCH 19/19] Handle NULL Pointer derefrencing in AVRCP Target role

28
meta-digi-dey/recipes-connectivity/bluez/bluez5-5.41/0016-bluetooth-Disable-bluetooth-low-power-mode-functionality.patch Normal file
View File

@ -0,0 +1,28 @@
From: Arturo Buzarra <arturo.buzarra@digi.com>
Date: Wed, 10 Oct 2018 09:14:56 +0200
Subject: [PATCH] bluetooth: Disable bluetooth low power mode functionality
In some conditions the low power modes cause communication
errors between the BT chip and the system, for this reason
we disable it by default.
https://jira.digi.com/browse/DEL-3711
Signed-off-by: Arturo Buzarra <arturo.buzarra@digi.com>
---
tools/hciattach.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/hciattach.c b/tools/hciattach.c
index 4aacdafed..234283882 100644
--- a/tools/hciattach.c
+++ b/tools/hciattach.c
@@ -1120,7 +1120,7 @@ struct uart_t uart[] = {
FLOW_CTL, DISABLE_PM, NULL, ath3k_ps, ath3k_pm },
/* QCA ROME */
- { "qca", 0x0000, 0x0000, HCI_UART_IBS, 115200, 115200,
+ { "qca", 0x0000, 0x0000, HCI_UART_H4, 115200, 115200,
FLOW_CTL, DISABLE_PM, NULL, qca, NULL },
/* QUALCOMM BTS */

31
meta-digi-dey/recipes-connectivity/bluez/bluez5-5.46/0004-QCA_bluetooth_chip_support.patch
View File

@ -1,3 +1,4 @@
From 8e337d77edfbc4f69d326e3abbd8f4f1ca65bffb Mon Sep 17 00:00:00 2001
From: Jose Diaz de Grenu <Jose.DiazdeGrenu@digi.com>
Date: Mon, 8 Jan 2018 10:29:51 +0100
Subject: [PATCH 1/4] Add hciattach rome support for Qualcomm chip QCA6564
@ -11,10 +12,10 @@ Signed-off-by: Jose Diaz de Grenu <Jose.DiazdeGrenu@digi.com>
Makefile.tools | 3 +-
profiles/audio/avrcp.c | 27 +-
tools/hciattach.c | 45 +-
tools/hciattach.h | 14 +-
tools/hciattach.h | 2 +
tools/hciattach_rome.c | 1941 ++++++++++++++++++++++++++++++++++++++++++++++++
tools/hciattach_rome.h | 390 ++++++++++
6 files changed, 2406 insertions(+), 14 deletions(-)
6 files changed, 2400 insertions(+), 8 deletions(-)
create mode 100644 tools/hciattach_rome.c
create mode 100644 tools/hciattach_rome.h
@ -163,7 +164,7 @@ index fad176c9b804..dda639cabca3 100644
FLOW_CTL, DISABLE_PM, NULL, ath3k_ps, ath3k_pm },
+ /* QCA ROME */
+ { "qca", 0x0000, 0x0000, HCI_UART_IBS, 115200, 115200,
+ { "qca", 0x0000, 0x0000, HCI_UART_H4, 115200, 115200,
+ FLOW_CTL, DISABLE_PM, NULL, qca, NULL },
+
/* QUALCOMM BTS */
@ -231,26 +232,14 @@ index fad176c9b804..dda639cabca3 100644
return 0;
}
diff --git a/tools/hciattach.h b/tools/hciattach.h
index 249aab49e90d..481e3a65f685 100644
index 249aab49e90d..5724b03bf2a6 100644
--- a/tools/hciattach.h
+++ b/tools/hciattach.h
@@ -39,12 +39,13 @@
#define HCI_UART_H4DS 3
#define HCI_UART_LL 4
#define HCI_UART_ATH3K 5
-#define HCI_UART_INTEL 6
-#define HCI_UART_BCM 7
-#define HCI_UART_QCA 8
-#define HCI_UART_AG6XX 9
-#define HCI_UART_NOKIA 10
-#define HCI_UART_MRVL 11
+#define HCI_UART_IBS 6
+#define HCI_UART_INTEL 7
+#define HCI_UART_BCM 8
+#define HCI_UART_QCA 9
+#define HCI_UART_AG6XX 10
+#define HCI_UART_NOKIA 11
+#define HCI_UART_MRVL 12
@@ -45,6 +45,7 @@
#define HCI_UART_AG6XX 9
#define HCI_UART_NOKIA 10
#define HCI_UART_MRVL 11
+#define HCI_UART_IBS 12
#define HCI_UART_RAW_DEVICE 0
#define HCI_UART_RESET_ON_INIT 1

102
meta-digi-dey/recipes-connectivity/bluez/bluez5-5.46/use-mainline-bsp/bluetooth-init Normal file
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@ -0,0 +1,102 @@
#!/bin/sh
#===============================================================================
#
# Copyright (C) 2012-2018 by Digi International Inc.
# All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License version 2 as published by
# the Free Software Foundation.
#
#
# !Description: Initialize bluetooth hardware
#
#===============================================================================
# Bluetooth power GPIO
BT_EN_QCA_GPIO_NR="137"
# set_gpio_value <gpio_nr> <value>
set_gpio_value() {
local SG_GPIONR="${1}"
local SG_GPIOVAL="${2}"
local SG_GPIOPATH="/sys/class/gpio/gpio${SG_GPIONR}"
[ -d "${SG_GPIOPATH}" ] || printf "%s" "${SG_GPIONR}" > /sys/class/gpio/export
printf out > "${SG_GPIOPATH}/direction" && sleep .2
printf "${SG_GPIOVAL}" > "${SG_GPIOPATH}/value" && sleep .2
[ -d "${SG_GPIOPATH}" ] && printf "%s" "${SG_GPIONR}" > /sys/class/gpio/unexport
}
# powercycle_gpio <gpio_nr>
powercycle_gpio() {
set_gpio_value "${1}" 0
set_gpio_value "${1}" 1
}
error() {
echo ${1}
exit 1
}
set_mac_address() {
# Get MAC address from the device tree. Use a default value if it has not been set.
BT_MACADDR="$(hexdump -ve '1/1 "%02X" ":"' /proc/device-tree/bluetooth/mac-address 2>/dev/null | sed 's/:$//g')"
if [ -z "${BT_MACADDR}" ] || [ "${BT_MACADDR}" = "00:00:00:00:00:00" ]; then
BT_MACADDR="00:04:F3:FF:FF:BB"
fi
# Convert the BT address to the hcitool command format.
# Example: "00:04:F3:11:22:33" coverted to "33 22 11 F3 04 00"
HCI_BT_ADDR="$(echo ${BT_MACADDR} | sed -e 's,^\(..\):\(..\):\(..\):\(..\):\(..\):\(..\)$,\6 \5 \4 \3 \2 \1,g')"
# Up the interface to be able to send hci commands
hciconfig hci0 up || echo "Cannot bring up bluetooth interface after initial attach" || exit 1
# Set the MAC address
hcitool -i hci0 cmd 3F 000B 01 02 06 ${HCI_BT_ADDR} > /dev/null || echo "Unable to set BT MAC Address" || exit 1
# Set the hci interface down so bluetooth main.conf will apply
hciconfig hci0 down || echo "Cannot down the hci interface" || exit 1
}
bluetooth_init() {
# Start the Bluetooth driver and bring up the interface
HCIATTACH_LOG="/var/log/hciattach.log"
killproc hciattach
powercycle_gpio "${BT_EN_QCA_GPIO_NR}"
hciattach ttyBt qualcomm 115200 -t3 flow unused > ${HCIATTACH_LOG} 2>&1 || BT_ERROR="FAIL (hciattach)"
set_mac_address || BT_ERROR="Unable to set MAC address"
}
# Source function library
. /etc/init.d/functions
case "$1" in
start)
if [ -d "/proc/device-tree/bluetooth" ]; then
echo -n "Starting bluetooth hardware: "
bluetooth_init
echo "${BT_ERROR:-done.}"
fi
;;
stop)
if [ -d "/sys/class/bluetooth/hci0" ]; then
echo -n "Stopping bluetooth hardware: "
killproc hciattach
# Power down bluetooth
set_gpio_value "${BT_EN_QCA_GPIO_NR}" 0
echo "done."
fi
;;
restart)
$0 stop
sleep 1
$0 start
;;
*)
echo "Usage: $0 {start|stop|restart}"
exit 1
;;
esac

1
meta-digi-dey/recipes-connectivity/bluez/bluez5_5.41.bbappend
View File

@ -23,6 +23,7 @@ QCA65XX_COMMON_PATCHES = " \
file://0013-hciattach_rome-Respect-the-user-indication-for-noflo.patch \
file://0014-hciattach-If-the-user-supplies-a-bdaddr-use-it.patch \
file://0015-hciattach-Add-verbosity-option.patch \
file://0016-bluetooth-Disable-bluetooth-low-power-mode-functionality.patch \
"
SRC_URI_append_ccimx6ul = " ${QCA65XX_COMMON_PATCHES}"

0
meta-digi-dey/recipes-connectivity/modemmanager/modemmanager/ccimx8x-sbc-express/78-mm-digi-xbee-cellular.rules → meta-digi-dey/recipes-connectivity/modemmanager/modemmanager/ccimx8x/78-mm-digi-xbee-cellular.rules
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4674
meta-digi-dey/recipes-connectivity/openssl/openssl/version-script.patch Normal file
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File diff suppressed because it is too large Load Diff

6
meta-digi-dey/recipes-connectivity/openssl/openssl_%.bbappend
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@ -6,8 +6,14 @@ CRYPTOCHIP_COMMON_PATCHES = " \
file://0003-Modify-openssl.cnf-to-automatically-load-the-cryptoc.patch \
"
SRC_URI_remove = " \
file://debian1.0.2/version-script.patch \
file://debian1.0.2/soname.patch \
"
SRC_URI += " \
file://0001-cryptodev-Fix-issue-with-signature-generation.patch \
file://0002-cryptodev-allow-copying-EVP-contexts.patch \
${@bb.utils.contains("MACHINE_FEATURES", "cryptochip", "${CRYPTOCHIP_COMMON_PATCHES}", "", d)} \
file://version-script.patch \
"

3
meta-digi-dey/recipes-core/busybox/busybox-1.24.1/ccimx8x/acpid.map Normal file
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@ -0,0 +1,3 @@
#s_type n_type(hex) s_code n_code value description
EV_KEY 0x01 KEY_SLEEP 142 1 pswitch-standby
EV_KEY 0x01 KEY_POWER 116 1 pswitch-poweroff

30
meta-digi-dey/recipes-digi/libdigiapix/libdigiapix-git/ccimx8x-sbc-pro/board.conf Normal file
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@ -0,0 +1,30 @@
[board]
model = Digi International ConnectCore 8X SBC Pro.
[GPIO]
# USER LED0 - MCA_IO18
USER_LED = 222
# USER BUTTON - MCA_IO05
USER_BUTTON = 209
[I2C]
# I2C-3 on Expansion connector.
DEFAULT_I2C_BUS = 3
[SPI]
# SPI-0 on Expansion connector.
DEFAULT_SPI = 32766,0
[PWM]
# TODO: PWM not currently supported
DEFAULT_PWM = 0,0
[ADC]
# TODO: only MCA ADCs are supported at the moment, with them being disabled by default
DEFAULT_ADC = 0,0

4
meta-digi-dey/recipes-digi/sysinfo/sysinfo/sysinfo
View File

@ -236,11 +236,13 @@ make_report(){
echo "--------------------------------------"
echo ""
if [ -e /sys/fsl_otp/HW_OCOTP_CFG5 ]; then
if [ "$(($(cat /sys/fsl_otp/HW_OCOTP_CFG5) & 2))" != "0" ]; then
echo "Device status: [CLOSED]"
else
echo "Device status: [OPEN]"
fi
fi
if [ -f "/proc/device-tree/digi,uboot-env,encrypted" ]; then
echo "U-Boot environment is encrypted"
@ -260,7 +262,7 @@ if [ -z "${UBOOT_VERSION}" ]; then
[ -c "/dev/mtd0" ] && UBOOT_PARTITION="/dev/mtd0"
UBOOT_VERSION="$(strings ${UBOOT_PARTITION} | grep -m 1 dub | cut -d' ' -f2)"
fi
MACHINE="$(cat /proc/device-tree/digi,machine,name | tr -d '\0')"
MACHINE="$(cat /proc/device-tree/compatible | tr '\0' '\t' | cut -f 1)"
BOARD_VARIANT="$(cat /proc/device-tree/digi,hwid,variant | tr -d '\0')"
BOARD_SN="$(cat /proc/device-tree/digi,hwid,sn | tr -d '\0')"
BOARD_VERSION="$(cat /proc/device-tree/digi,carrierboard,version | tr -d '\0')"

12
meta-digi-dey/recipes-graphics/xorg-xserver/xserver-xf86-config/use-mainline-bsp/xorg.conf Normal file
View File

@ -0,0 +1,12 @@
Section "Device"
Identifier "Kernel Framebuffer Device"
Driver "fbdev"
Option "fbdev" "/dev/fb0"
EndSection
Section "ServerFlags"
Option "BlankTime" "0"
Option "StandbyTime" "0"
Option "SuspendTime" "0"
Option "OffTime" "0"
EndSection

3
sdk/build-github.sh
View File

@ -22,7 +22,7 @@
set -e
AVAILABLE_PLATFORMS="ccimx8x-sbc-express ccimx6qpsbc ccimx6sbc ccimx6ulsbc ccimx6ulstarter"
AVAILABLE_PLATFORMS="ccimx8x-sbc-pro ccimx8x-sbc-express ccimx6qpsbc ccimx6sbc ccimx6ulsbc ccimx6ulstarter"
MANIFEST_URL="https://github.com/digi-embedded/dey-manifest.git"
@ -121,6 +121,7 @@ while read _pl _tgt; do
# the fly with underscores.
eval "${_pl//-/_}_tgt=\"${_tgt//,/ }\""
done<<-_EOF_
ccimx8x-sbc-pro dey-image-qt
ccimx8x-sbc-express dey-image-qt
ccimx6qpsbc dey-image-qt
ccimx6sbc dey-image-qt

1
sdk/build.sh
View File

@ -171,6 +171,7 @@ while read _pl _var _tgt; do
eval "${_pl//-/_}_var=\"${_var//,/ }\""
eval "${_pl//-/_}_tgt=\"${_tgt//,/ }\""
done<<-_EOF_
ccimx8x-sbc-pro DONTBUILDVARIANTS dey-image-qt
ccimx8x-sbc-express DONTBUILDVARIANTS dey-image-qt
ccimx6qpsbc DONTBUILDVARIANTS dey-image-qt,dey-image-aws
ccimx6sbc DONTBUILDVARIANTS dey-image-qt,dey-image-aws

22
sdk/config/ccimx8x-sbc-pro/bblayers.conf.sample Normal file
View File

@ -0,0 +1,22 @@
# POKY_BBLAYERS_CONF_VERSION is increased each time build/conf/bblayers.conf
# changes incompatibly
POKY_BBLAYERS_CONF_VERSION = "2"
BBPATH = "${TOPDIR}"
BBFILES ?= ""
BBLAYERS ?= " \
##OEROOT##/meta \
##OEROOT##/meta-poky \
##OEROOT##/meta-yocto-bsp \
##DIGIBASE##/meta-openembedded/meta-oe \
##DIGIBASE##/meta-openembedded/meta-python \
##DIGIBASE##/meta-openembedded/meta-networking \
##DIGIBASE##/meta-openembedded/meta-webserver \
##DIGIBASE##/meta-qt5 \
##DIGIBASE##/meta-swupdate \
##DIGIBASE##/meta-freescale \
##DIGIBASE##/meta-fsl-demos \
##DIGIBASE##/meta-digi/meta-digi-arm \
##DIGIBASE##/meta-digi/meta-digi-dey \
"

18
sdk/config/ccimx8x-sbc-pro/conf-notes.txt Normal file
View File

@ -0,0 +1,18 @@
Digi Embedded Yocto provides the following image recipes:
* dey-image-qt: graphical QT image
By default the image is XWayland-based so it provides a full Weston
desktop environment.
To compile the image for the framebuffer (instead of XWayland) add
the following line to the project's conf/local.conf:
DISTRO_FEATURES_remove = "x11 wayland vulkan"
* dey-image-aws: console-only image supporting Amazon Web Services IoT
This image includes the AWS Greengrass Core and an AWS IoT platform
example application. For more information on AWS support in Digi
Embedded Yocto see the online documentation.

254
sdk/config/ccimx8x-sbc-pro/local.conf.sample Normal file
View File

@ -0,0 +1,254 @@
#
# This file is your local configuration file and is where all local user settings
# are placed. The comments in this file give some guide to the options a new user
# to the system might want to change but pretty much any configuration option can
# be set in this file. More adventurous users can look at local.conf.extended
# which contains other examples of configuration which can be placed in this file
# but new users likely won't need any of them initially.
#
# Lines starting with the '#' character are commented out and in some cases the
# default values are provided as comments to show people example syntax. Enabling
# the option is a question of removing the # character and making any change to the
# variable as required.
#
# Machine Selection
#
# You need to select a specific machine to target the build with. There are a selection
# of emulated machines available which can boot and run in the QEMU emulator:
#
#MACHINE ?= "qemuarm"
#MACHINE ?= "qemuarm64"
#MACHINE ?= "qemumips"
#MACHINE ?= "qemumips64"
#MACHINE ?= "qemuppc"
#MACHINE ?= "qemux86"
#MACHINE ?= "qemux86-64"
#
# There are also the following hardware board target machines included for
# demonstration purposes:
#
#MACHINE ?= "beaglebone"
#MACHINE ?= "genericx86"
#MACHINE ?= "genericx86-64"
#MACHINE ?= "mpc8315e-rdb"
#MACHINE ?= "edgerouter"
#
# This sets the default machine to be qemux86 if no other machine is selected:
#MACHINE ??= "qemux86"
MACHINE = "ccimx8x-sbc-pro"
#
# Use Digi's internal git repositories
#
#DIGI_INTERNAL_GIT ?= "1"
#
# Where to place downloads
#
# During a first build the system will download many different source code tarballs
# from various upstream projects. This can take a while, particularly if your network
# connection is slow. These are all stored in DL_DIR. When wiping and rebuilding you
# can preserve this directory to speed up this part of subsequent builds. This directory
# is safe to share between multiple builds on the same machine too.
#
# The default is a downloads directory under TOPDIR which is the build directory.
#
#DL_DIR ?= "${TOPDIR}/downloads"
#
# Where to place shared-state files
#
# BitBake has the capability to accelerate builds based on previously built output.
# This is done using "shared state" files which can be thought of as cache objects
# and this option determines where those files are placed.
#
# You can wipe out TMPDIR leaving this directory intact and the build would regenerate
# from these files if no changes were made to the configuration. If changes were made
# to the configuration, only shared state files where the state was still valid would
# be used (done using checksums).
#
# The default is a sstate-cache directory under TOPDIR.
#
#SSTATE_DIR ?= "${TOPDIR}/sstate-cache"
#
# Where to place the build output
#
# This option specifies where the bulk of the building work should be done and
# where BitBake should place its temporary files and output. Keep in mind that
# this includes the extraction and compilation of many applications and the toolchain
# which can use Gigabytes of hard disk space.
#
# The default is a tmp directory under TOPDIR.
#
#TMPDIR = "${TOPDIR}/tmp"
#
# Default policy config
#
# The distribution setting controls which policy settings are used as defaults.
# The default value is fine for general Yocto project use, at least initially.
# Ultimately when creating custom policy, people will likely end up subclassing
# these defaults.
#
DISTRO ?= "dey"
# As an example of a subclass there is a "bleeding" edge policy configuration
# where many versions are set to the absolute latest code from the upstream
# source control systems. This is just mentioned here as an example, its not
# useful to most new users.
# DISTRO ?= "poky-bleeding"
#
# Package Management configuration
#
# This variable lists which packaging formats to enable. Multiple package backends
# can be enabled at once and the first item listed in the variable will be used
# to generate the root filesystems.
# Options are:
# - 'package_deb' for debian style deb files
# - 'package_ipk' for ipk files are used by opkg (a debian style embedded package manager)
# - 'package_rpm' for rpm style packages
# E.g.: PACKAGE_CLASSES ?= "package_rpm package_deb package_ipk"
# We default to rpm:
PACKAGE_CLASSES ?= "package_rpm"
#
# SDK target architecture
#
# This variable specifies the architecture to build SDK items for and means
# you can build the SDK packages for architectures other than the machine you are
# running the build on (i.e. building i686 packages on an x86_64 host).
# Supported values are i686 and x86_64
#SDKMACHINE ?= "i686"
#
# Extra image configuration defaults
#
# The EXTRA_IMAGE_FEATURES variable allows extra packages to be added to the generated
# images. Some of these options are added to certain image types automatically. The
# variable can contain the following options:
# "dbg-pkgs" - add -dbg packages for all installed packages
# (adds symbol information for debugging/profiling)
# "dev-pkgs" - add -dev packages for all installed packages
# (useful if you want to develop against libs in the image)
# "ptest-pkgs" - add -ptest packages for all ptest-enabled packages
# (useful if you want to run the package test suites)
# "tools-sdk" - add development tools (gcc, make, pkgconfig etc.)
# "tools-debug" - add debugging tools (gdb, strace)
# "eclipse-debug" - add Eclipse remote debugging support
# "tools-profile" - add profiling tools (oprofile, lttng, valgrind)
# "tools-testapps" - add useful testing tools (ts_print, aplay, arecord etc.)
# "debug-tweaks" - make an image suitable for development
# e.g. ssh root access has a blank password
# There are other application targets that can be used here too, see
# meta/classes/image.bbclass and meta/classes/core-image.bbclass for more details.
# We default to enabling the debugging tweaks.
EXTRA_IMAGE_FEATURES ?= "debug-tweaks"
#
# Additional image features
#
# The following is a list of additional classes to use when building images which
# enable extra features. Some available options which can be included in this variable
# are:
# - 'buildstats' collect build statistics
# - 'image-mklibs' to reduce shared library files size for an image
# - 'image-prelink' in order to prelink the filesystem image
# NOTE: if listing mklibs & prelink both, then make sure mklibs is before prelink
# NOTE: mklibs also needs to be explicitly enabled for a given image, see local.conf.extended
USER_CLASSES ?= "buildstats image-mklibs image-prelink"
#
# Runtime testing of images
#
# The build system can test booting virtual machine images under qemu (an emulator)
# after any root filesystems are created and run tests against those images. To
# enable this uncomment this line. See classes/testimage(-auto).bbclass for
# further details.
#TEST_IMAGE = "1"
#
# Interactive shell configuration
#
# Under certain circumstances the system may need input from you and to do this it
# can launch an interactive shell. It needs to do this since the build is
# multithreaded and needs to be able to handle the case where more than one parallel
# process may require the user's attention. The default is iterate over the available
# terminal types to find one that works.
#
# Examples of the occasions this may happen are when resolving patches which cannot
# be applied, to use the devshell or the kernel menuconfig
#
# Supported values are auto, gnome, xfce, rxvt, screen, konsole (KDE 3.x only), none
# Note: currently, Konsole support only works for KDE 3.x due to the way
# newer Konsole versions behave
#OE_TERMINAL = "auto"
# By default disable interactive patch resolution (tasks will just fail instead):
PATCHRESOLVE = "noop"
#
# Disk Space Monitoring during the build
#
# Monitor the disk space during the build. If there is less that 1GB of space or less
# than 100K inodes in any key build location (TMPDIR, DL_DIR, SSTATE_DIR), gracefully
# shutdown the build. If there is less that 100MB or 1K inodes, perform a hard abort
# of the build. The reason for this is that running completely out of space can corrupt
# files and damages the build in ways which may not be easily recoverable.
# It's necesary to monitor /tmp, if there is no space left the build will fail
# with very exotic errors.
BB_DISKMON_DIRS = "\
STOPTASKS,${TMPDIR},1G,100K \
STOPTASKS,${DL_DIR},1G,100K \
STOPTASKS,${SSTATE_DIR},1G,100K \
STOPTASKS,/tmp,100M,100K \
ABORT,${TMPDIR},100M,1K \
ABORT,${DL_DIR},100M,1K \
ABORT,${SSTATE_DIR},100M,1K \
ABORT,/tmp,10M,1K"
#
# Shared-state files from other locations
#
# As mentioned above, shared state files are prebuilt cache data objects which can
# used to accelerate build time. This variable can be used to configure the system
# to search other mirror locations for these objects before it builds the data itself.
#
# This can be a filesystem directory, or a remote url such as http or ftp. These
# would contain the sstate-cache results from previous builds (possibly from other
# machines). This variable works like fetcher MIRRORS/PREMIRRORS and points to the
# cache locations to check for the shared objects.
# NOTE: if the mirror uses the same structure as SSTATE_DIR, you need to add PATH
# at the end as shown in the examples below. This will be substituted with the
# correct path within the directory structure.
#SSTATE_MIRRORS ?= "\
#file://.* http://someserver.tld/share/sstate/PATH;downloadfilename=PATH \n \
#file://.* file:///some/local/dir/sstate/PATH"
#
# Qemu configuration
#
# By default qemu will build with a builtin VNC server where graphical output can be
# seen. The two lines below enable the SDL backend too. By default libsdl-native will
# be built, if you want to use your host's libSDL instead of the minimal libsdl built
# by libsdl-native then uncomment the ASSUME_PROVIDED line below.
PACKAGECONFIG_append_pn-qemu-native = " sdl"
PACKAGECONFIG_append_pn-nativesdk-qemu = " sdl"
#ASSUME_PROVIDED += "libsdl-native"
# CONF_VERSION is increased each time build/conf/ changes incompatibly and is used to
# track the version of this file when it was generated. This can safely be ignored if
# this doesn't mean anything to you.
CONF_VERSION = "1"
#
# Enable local PR server
#
PRSERV_HOST = "localhost:0"
#
# Some libraries and packages are covered by NXP EULA
#
#ACCEPT_FSL_EULA = "1"