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imx-system-manager: use git repository and drop local patches 

Remove the local ccimx95 patch series from imx-system-manager bbappend
and fetch the DEY-specific changes directly from the Digi fork.

https://onedigi.atlassian.net/browse/DEL-10009

Signed-off-by: Javier Viguera <javier.viguera@digi.com>
This commit is contained in:
Javier Viguera 2026-03-13 14:54:37 +01:00
parent fe54927861
commit cf8d771390
16 changed files with 7 additions and 13054 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6356
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0001-ccimx95dvk-add-new-platform-config-and-board.patch
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3534
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0002-ccimx95dvk-configure-board-and-switch-debug-UART-to-.patch
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254
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0003-ccimx95dvk-disable-PCAL6408A-expander-and-move-GPIO1.patch
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@ -1,254 +0,0 @@
From: Javier Viguera <javier.viguera@digi.com>
Date: Mon, 15 Sep 2025 12:37:05 +0200
Subject: [PATCH] ccimx95dvk: disable PCAL6408A expander and move GPIO1 to A55
Our board does not populate that expander, so disable the initialization
and assign GPIO1 to be used by the A55 cpu.
Upstream-Status: Inappropriate [DEY specific]
Signed-off-by: Javier Viguera <javier.viguera@digi.com>
---
boards/ccimx95dvk/board.c | 7 ---
boards/ccimx95dvk/pin_mux.c | 4 --
boards/ccimx95dvk/sm/brd_sm.c | 9 ---
boards/ccimx95dvk/sm/brd_sm_handlers.c | 82 --------------------------
configs/ccimx95dvk.cfg | 3 +-
configs/ccimx95dvk/config_scmi.h | 2 +
configs/ccimx95dvk/config_trdc.h | 2 +-
7 files changed, 5 insertions(+), 104 deletions(-)
diff --git a/boards/ccimx95dvk/board.c b/boards/ccimx95dvk/board.c
index c9b97b2a67d9..fe76d6e1a1a3 100755
--- a/boards/ccimx95dvk/board.c
+++ b/boards/ccimx95dvk/board.c
@@ -355,9 +355,6 @@ void BOARD_InitHandlers(void)
/* Enable FCCU handler */
NVIC_SetPriority(FCCU_INT0_IRQn, IRQ_PRIO_NOPREEMPT_CRITICAL);
NVIC_EnableIRQ(FCCU_INT0_IRQn);
-
- /* Enable GPIO1 handler */
- NVIC_EnableIRQ(GPIO1_0_IRQn);
}
/*--------------------------------------------------------------------------*/
@@ -539,10 +536,6 @@ void BOARD_SystemSleepPrepare(uint32_t sleepMode, uint32_t sleepFlags)
(void) CPU_PerLpiConfigSet(CPU_IDX_M33P, s_uartConfig.perLpiId,
CPU_PER_LPI_ON_RUN_WAIT_STOP);
}
-
- /* Configure LPI for GPIO1 */
- (void) CPU_PerLpiConfigSet(CPU_IDX_M33P, CPU_PER_LPI_IDX_GPIO1,
- CPU_PER_LPI_ON_RUN_WAIT_STOP);
}
/*--------------------------------------------------------------------------*/
diff --git a/boards/ccimx95dvk/pin_mux.c b/boards/ccimx95dvk/pin_mux.c
index ff2b9540ea7a..6f5bb4a51c4c 100755
--- a/boards/ccimx95dvk/pin_mux.c
+++ b/boards/ccimx95dvk/pin_mux.c
@@ -57,9 +57,5 @@ void BOARD_InitPins(void)
IOMUXC_SetPinConfig(IOMUXC_PAD_I2C2_SDA__LPI2C2_SDA, IOMUXC_PAD_DSE(0xFU)
| IOMUXC_PAD_FSEL1(0x3U) | IOMUXC_PAD_PU(0x1U) | IOMUXC_PAD_OD(0x1U));
#endif
-
- /* Configure GPIO1-10 (INT from the PCAL6408A) */
- IOMUXC_SetPinMux(IOMUXC_PAD_PDM_BIT_STREAM1__GPIO1_IO_BIT10, 0U);
- IOMUXC_SetPinConfig(IOMUXC_PAD_PDM_BIT_STREAM1__GPIO1_IO_BIT10, 0U);
}
diff --git a/boards/ccimx95dvk/sm/brd_sm.c b/boards/ccimx95dvk/sm/brd_sm.c
index 36b4b52c6986..ae6c3195f0b2 100755
--- a/boards/ccimx95dvk/sm/brd_sm.c
+++ b/boards/ccimx95dvk/sm/brd_sm.c
@@ -458,15 +458,6 @@ void BRD_SM_ShutdownRecordSave(dev_sm_rst_rec_t shutdownRec)
int32_t BRD_SM_SystemReset(void)
{
int32_t status = SM_ERR_SUCCESS;
- rgpio_pin_config_t gpioConfig =
- {
- kRGPIO_DigitalOutput,
- 0U
- };
-
- /* Drive WDOG_ANY to reset PMIC */
- RGPIO_PinInit(GPIO1, 15U, &gpioConfig);
- IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__GPIO1_IO_BIT15, 0U);
/* Wait for PMIC to react */
SystemTimeDelay(1000U);
diff --git a/boards/ccimx95dvk/sm/brd_sm_handlers.c b/boards/ccimx95dvk/sm/brd_sm_handlers.c
index a96f6ce0e2f4..19ee28e93134 100755
--- a/boards/ccimx95dvk/sm/brd_sm_handlers.c
+++ b/boards/ccimx95dvk/sm/brd_sm_handlers.c
@@ -96,26 +96,6 @@ int32_t BRD_SM_SerialDevicesInit(void)
{
int32_t status = SM_ERR_SUCCESS;
LPI2C_Type *const s_i2cBases[] = LPI2C_BASE_PTRS;
- pcal6408a_config_t pcal6408Config;
-
- /* Fill in PCAL6408A dev */
- g_pcal6408aDev.i2cBase = s_i2cBases[BOARD_I2C_INSTANCE];
- g_pcal6408aDev.devAddr = BOARD_PCAL6408A_DEV_ADDR;
-
- /* Init the bus expander */
- PCAL6408A_GetDefaultConfig(&pcal6408Config);
- pcal6408Config.inputLatch = 0xFFU;
- if (!PCAL6408A_Init(&g_pcal6408aDev, &pcal6408Config))
- {
- status = SM_ERR_HARDWARE_ERROR;
- }
- else
- {
- if (!PCAL6408A_IntMaskSet(&g_pcal6408aDev, PCAL6408A_INITIAL_MASK))
- {
- status = SM_ERR_HARDWARE_ERROR;
- }
- }
if (status == SM_ERR_SUCCESS)
{
@@ -254,20 +234,6 @@ int32_t BRD_SM_SerialDevicesInit(void)
}
}
- if (status == SM_ERR_SUCCESS)
- {
- rgpio_pin_config_t gpioConfig =
- {
- kRGPIO_DigitalInput,
- 0U
- };
-
- /* Init GPIO1-10 */
- RGPIO_PinInit(GPIO1, 10U, &gpioConfig);
- RGPIO_SetPinInterruptConfig(GPIO1, 10U, kRGPIO_InterruptOutput0,
- kRGPIO_InterruptLogicZero);
- }
-
/* Return status */
return status;
}
@@ -300,54 +266,6 @@ int32_t BRD_SM_BusExpMaskSet(uint8_t val, uint8_t mask)
return status;
}
-/*--------------------------------------------------------------------------*/
-/* GPIO1 handler */
-/*--------------------------------------------------------------------------*/
-void GPIO1_0_IRQHandler(void)
-{
- uint32_t flags;
- uint8_t status, val;
-
- /* Get GPIO status */
- flags = RGPIO_GetPinsInterruptFlags(GPIO1, kRGPIO_InterruptOutput0);
-
- /* Get PCAL6408A status */
- (void) PCAL6408A_IntStatusGet(&g_pcal6408aDev, &status);
-
- /* Get value and Clear PCAL6408A interrupts */
- (void) PCAL6408A_InputGet(&g_pcal6408aDev, &val);
-
- /* Clear GPIO interrupts */
- RGPIO_ClearPinsInterruptFlags(GPIO1, kRGPIO_InterruptOutput0, flags);
-
- /* Handle PF09 interrupt */
- if ((status & BIT8(PCAL6408A_INPUT_PF09_INT)) != 0U)
- {
- /* Asserts low */
- if ((val & BIT8(PCAL6408A_INPUT_PF09_INT)) == 0U)
- {
- BRD_SM_Pf09Handler();
- }
- }
-
- /* Handle PCA2131 interrupt */
- if (g_pca2131Used && ((status & BIT8(PCAL6408A_INPUT_PCA2131_INT))
- != 0U))
- {
- /* Asserts low */
- if ((val & BIT8(PCAL6408A_INPUT_PCA2131_INT)) == 0U)
- {
- BRD_SM_BbmHandler();
- }
- }
-
- /* Handle controls interrupts */
- BRD_SM_ControlHandler(status, val);
-
- /* Adjust dynamic IRQ priority */
- (void) DEV_SM_IrqPrioUpdate();
-}
-
/*==========================================================================*/
/*--------------------------------------------------------------------------*/
diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
index 557bba3cecf2..cd6c5c4551c2 100755
--- a/configs/ccimx95dvk.cfg
+++ b/configs/ccimx95dvk.cfg
@@ -217,7 +217,6 @@ ELE OWNER
FSB READONLY
GIC ACCESS
GPC OWNER
-GPIO1 OWNER
GPR0 OWNER
GPR1 OWNER
GPR2 OWNER
@@ -503,6 +502,7 @@ PERLPI_LPUART4 ALL
PERLPI_LPUART5 ALL
PERLPI_LPUART6 ALL
PERLPI_LPUART8 ALL
+PERLPI_GPIO1 ALL
PERLPI_WDOG3 ALL
PERLPI_WDOG4 ALL
SYS ALL
@@ -737,6 +737,7 @@ FLEXIO2 OWNER
FLEXSPI1 OWNER
FSB READONLY
GIC OWNER
+GPIO1 OWNER
GPIO2 OWNER
GPIO3 OWNER
GPIO4 OWNER
diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
index 7032a0efc948..edb2a17eaca1 100644
--- a/configs/ccimx95dvk/config_scmi.h
+++ b/configs/ccimx95dvk/config_scmi.h
@@ -183,6 +183,7 @@
.perlpiPerms[DEV_SM_PERLPI_CAN3] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_CAN4] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_CAN5] = SM_SCMI_PERM_ALL, \
+ .perlpiPerms[DEV_SM_PERLPI_GPIO1] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_GPIO2] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_GPIO3] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_GPIO4] = SM_SCMI_PERM_ALL, \
@@ -465,6 +466,7 @@
.perlpiPerms[DEV_SM_PERLPI_CAN3] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_CAN4] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_CAN5] = SM_SCMI_PERM_ALL, \
+ .perlpiPerms[DEV_SM_PERLPI_GPIO1] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_GPIO2] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_GPIO3] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_GPIO4] = SM_SCMI_PERM_ALL, \
diff --git a/configs/ccimx95dvk/config_trdc.h b/configs/ccimx95dvk/config_trdc.h
index 1d8ed0b6fc95..47df6a7577d5 100644
--- a/configs/ccimx95dvk/config_trdc.h
+++ b/configs/ccimx95dvk/config_trdc.h
@@ -116,7 +116,6 @@
SM_CFG_W1(0x00010470U), 0x33333333U, \
SM_CFG_W1(0x00010474U), 0x00003000U, \
SM_CFG_W1(0x00010580U), 0x000003C0U, \
- SM_CFG_W1(0x000105a8U), 0x00000003U, \
SM_CFG_W1(0x00010640U), 0x99999999U, \
SM_CFG_W1(0x00010644U), 0x99999999U, \
SM_CFG_W1(0x00010648U), 0x99999999U, \
@@ -129,6 +128,7 @@
SM_CFG_W1(0x0001066cU), 0x90909000U, \
SM_CFG_W1(0x00010670U), 0x00009000U, \
SM_CFG_W1(0x00010780U), 0x099330C0U, \
+ SM_CFG_W1(0x000107a8U), 0x00000009U, \
SM_CFG_Z1(0x00010850U), \
SM_CFG_W1(0x00010854U), 0x9000C000U, \
SM_CFG_W1(0x00010858U), 0x00000099U, \

206
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0004-ccimx95dvk-move-resources-from-M7-to-A55.patch
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@ -1,206 +0,0 @@
From: Javier Viguera <javier.viguera@digi.com>
Date: Tue, 16 Sep 2025 17:51:14 +0200
Subject: [PATCH] ccimx95dvk: move resources from M7 to A55
Moved from M7 to A55 domain:
* LPUART7
* PIN_GPIO_IO14
* PIN_GPIO_IO15
Upstream-Status: Inappropriate [DEY specific]
Signed-off-by: Javier Viguera <javier.viguera@digi.com>
---
configs/ccimx95dvk.cfg | 11 ++++-------
configs/ccimx95dvk/config_scmi.h | 15 ++++++++-------
configs/ccimx95dvk/config_test.h | 7 +------
configs/ccimx95dvk/config_trdc.h | 3 +--
4 files changed, 14 insertions(+), 22 deletions(-)
diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
index cd6c5c4551c2..49861f4545ae 100755
--- a/configs/ccimx95dvk.cfg
+++ b/configs/ccimx95dvk.cfg
@@ -390,7 +390,6 @@ LPIT1 OWNER
LPTMR1 OWNER
LPTMR2 OWNER
LPTPM1 OWNER
-LPUART3 OWNER, test
MSGINTR1 OWNER
MSGINTR2 OWNER
MU5_A OWNER
@@ -403,11 +402,6 @@ TSTMR2 OWNER
V2X_SHE1 OWNER
WDOG5 OWNER
-# Pins
-
-PIN_GPIO_IO14 OWNER
-PIN_GPIO_IO15 OWNER
-
# Memory
M7MIX DATA, begin=0x020380000, end=0x02047FFFF
@@ -498,6 +492,7 @@ PERLPI_GPIO4 ALL
PERLPI_GPIO5 ALL
PERLPI_LPUART1 ALL
PERLPI_LPUART2 ALL
+PERLPI_LPUART3 ALL
PERLPI_LPUART4 ALL
PERLPI_LPUART5 ALL
PERLPI_LPUART6 ALL
@@ -784,6 +779,7 @@ LPTPM5 OWNER
LPTPM6 OWNER
LPUART1 OWNER
LPUART2 OWNER
+LPUART3 OWNER
LPUART4 OWNER
LPUART5 OWNER
LPUART6 OWNER
@@ -936,6 +932,8 @@ PIN_GPIO_IO10 OWNER
PIN_GPIO_IO11 OWNER
PIN_GPIO_IO12 OWNER
PIN_GPIO_IO13 OWNER
+PIN_GPIO_IO14 OWNER
+PIN_GPIO_IO15 OWNER
PIN_GPIO_IO16 OWNER
PIN_GPIO_IO17 OWNER
PIN_GPIO_IO18 OWNER
@@ -1015,4 +1013,3 @@ OCRAM EXEC, begin=0x0204C0000, size=96K
GPU DATA, begin=0x04D900000, end=0x04DD7FFFF
DDR EXEC, begin=0x088000000, end=0x089FFFFFF
DDR EXEC, begin=0x08E000000, end=0x87FFFFFFF
-
diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
index edb2a17eaca1..297806453ee1 100644
--- a/configs/ccimx95dvk/config_scmi.h
+++ b/configs/ccimx95dvk/config_scmi.h
@@ -69,7 +69,6 @@
.clkPerms[DEV_SM_CLK_CAN1] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPTMR1] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPTMR2] = SM_SCMI_PERM_ALL, \
- .clkPerms[DEV_SM_CLK_LPUART3] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_M7SYSTICK] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_TSTMR2] = SM_SCMI_PERM_ALL, \
.cpuPerms[DEV_SM_CPU_M7P] = SM_SCMI_PERM_ALL, \
@@ -81,9 +80,6 @@
.daisyPerms[DEV_SM_DAISY_LPTMR2_0] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_LPTMR2_1] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_LPTMR2_2] = SM_SCMI_PERM_ALL, \
- .daisyPerms[DEV_SM_DAISY_LPUART3_CTS] = SM_SCMI_PERM_ALL, \
- .daisyPerms[DEV_SM_DAISY_LPUART3_RXD] = SM_SCMI_PERM_ALL, \
- .daisyPerms[DEV_SM_DAISY_LPUART3_TXD] = SM_SCMI_PERM_ALL, \
.faultPerms[DEV_SM_FAULT_M7_LOCKUP] = SM_SCMI_PERM_ALL, \
.faultPerms[DEV_SM_FAULT_M7_RESET] = SM_SCMI_PERM_ALL, \
.faultPerms[DEV_SM_FAULT_SW0] = SM_SCMI_PERM_ALL, \
@@ -94,10 +90,7 @@
.pdPerms[DEV_SM_PD_M7] = SM_SCMI_PERM_ALL, \
.perfPerms[DEV_SM_PERF_M7] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_CAN1] = SM_SCMI_PERM_ALL, \
- .perlpiPerms[DEV_SM_PERLPI_LPUART3] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_WDOG5] = SM_SCMI_PERM_ALL, \
- .pinPerms[DEV_SM_PIN_GPIO_IO14] = SM_SCMI_PERM_ALL, \
- .pinPerms[DEV_SM_PIN_GPIO_IO15] = SM_SCMI_PERM_ALL, \
.rtcPerms[BRD_SM_RTC_PCA2131] = SM_SCMI_PERM_ALL, \
.rtcPerms[DEV_SM_RTC_BBNSM] = SM_SCMI_PERM_PRIV, \
.sensorPerms[BRD_SM_SENSOR_TEMP_PF09] = SM_SCMI_PERM_SET, \
@@ -190,6 +183,7 @@
.perlpiPerms[DEV_SM_PERLPI_GPIO5] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART1] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART2] = SM_SCMI_PERM_ALL, \
+ .perlpiPerms[DEV_SM_PERLPI_LPUART3] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART4] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART5] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART6] = SM_SCMI_PERM_ALL, \
@@ -281,6 +275,7 @@
.clkPerms[DEV_SM_CLK_LPSPI8] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPUART1] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPUART2] = SM_SCMI_PERM_ALL, \
+ .clkPerms[DEV_SM_CLK_LPUART3] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPUART4] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPUART5] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPUART6] = SM_SCMI_PERM_ALL, \
@@ -389,6 +384,9 @@
.daisyPerms[DEV_SM_DAISY_LPSPI4_SCK] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_LPSPI4_SDI] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_LPSPI4_SDO] = SM_SCMI_PERM_ALL, \
+ .daisyPerms[DEV_SM_DAISY_LPUART3_CTS] = SM_SCMI_PERM_ALL, \
+ .daisyPerms[DEV_SM_DAISY_LPUART3_RXD] = SM_SCMI_PERM_ALL, \
+ .daisyPerms[DEV_SM_DAISY_LPUART3_TXD] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_LPUART4_CTS] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_LPUART4_RXD] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_LPUART4_TXD] = SM_SCMI_PERM_ALL, \
@@ -473,6 +471,7 @@
.perlpiPerms[DEV_SM_PERLPI_GPIO5] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART1] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART2] = SM_SCMI_PERM_ALL, \
+ .perlpiPerms[DEV_SM_PERLPI_LPUART3] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART4] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART5] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART6] = SM_SCMI_PERM_ALL, \
@@ -527,6 +526,8 @@
.pinPerms[DEV_SM_PIN_GPIO_IO11] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_GPIO_IO12] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_GPIO_IO13] = SM_SCMI_PERM_ALL, \
+ .pinPerms[DEV_SM_PIN_GPIO_IO14] = SM_SCMI_PERM_ALL, \
+ .pinPerms[DEV_SM_PIN_GPIO_IO15] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_GPIO_IO16] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_GPIO_IO17] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_GPIO_IO18] = SM_SCMI_PERM_ALL, \
diff --git a/configs/ccimx95dvk/config_test.h b/configs/ccimx95dvk/config_test.h
index e667d2d5bf36..eed7c5a3d9b8 100644
--- a/configs/ccimx95dvk/config_test.h
+++ b/configs/ccimx95dvk/config_test.h
@@ -143,12 +143,11 @@
/*--------------------------------------------------------------------------*/
/*! Config for number of tests */
-#define SM_SCMI_NUM_TEST 42U
+#define SM_SCMI_NUM_TEST 37U
/*! Config data array for tests */
#define SM_SCMI_TEST_CONFIG_DATA \
{.testId = TEST_BUTTON, .channel = 5U, .rsrc = DEV_SM_BUTTON_0}, \
- {.testId = TEST_CLK, .channel = 0U, .rsrc = DEV_SM_CLK_LPUART3}, \
{.testId = TEST_CLK, .channel = 5U, .rsrc = DEV_SM_CLK_ENETREF}, \
{.testId = TEST_CLK, .channel = 5U, .rsrc = DEV_SM_CLK_ENETTIMER1}, \
{.testId = TEST_CLK, .channel = 5U, .rsrc = DEV_SM_CLK_GPU_CGC}, \
@@ -157,9 +156,6 @@
{.testId = TEST_CLK, .channel = 5U, .rsrc = DEV_SM_CLK_SAI1}, \
{.testId = TEST_CTRL, .channel = 5U, .rsrc = DEV_SM_CTRL_MQS1_SETTINGS}, \
{.testId = TEST_CTRL, .channel = 5U, .rsrc = DEV_SM_CTRL_SAI1_MCLK}, \
- {.testId = TEST_DAISY, .channel = 0U, .rsrc = DEV_SM_DAISY_LPUART3_CTS}, \
- {.testId = TEST_DAISY, .channel = 0U, .rsrc = DEV_SM_DAISY_LPUART3_RXD}, \
- {.testId = TEST_DAISY, .channel = 0U, .rsrc = DEV_SM_DAISY_LPUART3_TXD}, \
{.testId = TEST_DAISY, .channel = 5U, .rsrc = DEV_SM_DAISY_NETC_EMDC}, \
{.testId = TEST_DAISY, .channel = 5U, .rsrc = DEV_SM_DAISY_NETC_EMDIO}, \
{.testId = TEST_DAISY, .channel = 5U, .rsrc = DEV_SM_DAISY_NETC_ETH0_RMII_RX_ER}, \
@@ -184,7 +180,6 @@
{.testId = TEST_PERF, .channel = 5U, .rsrc = DEV_SM_PERF_GPU}, \
{.testId = TEST_PERF, .channel = 5U, .rsrc = DEV_SM_PERF_NPU}, \
{.testId = TEST_PERF, .channel = 5U, .rsrc = DEV_SM_PERF_VPU}, \
- {.testId = TEST_PERLPI, .channel = 0U, .rsrc = DEV_SM_PERLPI_LPUART3}, \
{.testId = TEST_PERLPI, .channel = 5U, .rsrc = DEV_SM_PERLPI_LPUART8}, \
{.testId = TEST_PIN, .channel = 5U, .rsrc = DEV_SM_PIN_UART1_RXD}, \
{.testId = TEST_RTC, .channel = 5U, .rsrc = DEV_SM_RTC_BBNSM}, \
diff --git a/configs/ccimx95dvk/config_trdc.h b/configs/ccimx95dvk/config_trdc.h
index 47df6a7577d5..dc6245097316 100644
--- a/configs/ccimx95dvk/config_trdc.h
+++ b/configs/ccimx95dvk/config_trdc.h
@@ -1168,7 +1168,7 @@
SM_CFG_W1(0x0001065cU), 0x99999999U, \
SM_CFG_W1(0x00010660U), 0x00909099U, \
SM_CFG_W1(0x00010664U), 0x99090990U, \
- SM_CFG_W1(0x00010668U), 0x09999999U, \
+ SM_CFG_W1(0x00010668U), 0x99999999U, \
SM_CFG_W1(0x0001066cU), 0x09999999U, \
SM_CFG_W1(0x00010670U), 0x99900009U, \
SM_CFG_W1(0x00010674U), 0x99999909U, \
@@ -1178,7 +1178,6 @@
SM_CFG_W1(0x000107a8U), 0x00000009U, \
SM_CFG_W1(0x00010860U), 0x00090000U, \
SM_CFG_W1(0x00010864U), 0x00909009U, \
- SM_CFG_W1(0x00010868U), 0x90000000U, \
SM_CFG_W1(0x00010878U), 0x00090000U, \
SM_CFG_Z1(0x00010a60U), \
SM_CFG_Z1(0x00010c60U), \

75
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0005-ccimx95dvk-move-pads-to-non-secure-A55.patch
View File

@ -1,75 +0,0 @@
From: Hector Palacios <hector.palacios@digi.com>
Date: Wed, 24 Sep 2025 12:26:07 +0200
Subject: [PATCH] ccimx95dvk: move pads to non-secure A55
The following pads are multiplexed and used by A55 in Linux:
- PIN_UART2_RXD is used as LPUART1 CTS
- PIN_UART2_TXD is used as LPUART1 RTS
- PIN_PDM_BIT_STREAM1 is used as MIKROBUS_RST
Upstream-Status: Inappropriate [DEY specific]
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
configs/ccimx95dvk.cfg | 5 ++++-
configs/ccimx95dvk/config_scmi.h | 3 +++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
index 49861f4545ae..78fad32b4513 100755
--- a/configs/ccimx95dvk.cfg
+++ b/configs/ccimx95dvk.cfg
@@ -1,6 +1,7 @@
## ###################################################################
##
## Copyright 2023-2025 NXP
+## Copyright 2025 Digi International Inc.
##
## Redistribution and use in source and binary forms, with or without modification,
## are permitted provided that the following conditions are met:
@@ -305,7 +306,6 @@ L_STCU_NPUMIX OWNER
PIN_FCCU_ERR0 OWNER
PIN_I2C1_SCL OWNER
PIN_I2C1_SDA OWNER
-PIN_PDM_BIT_STREAM1 OWNER
PIN_GPIO_IO08 OWNER # LPUART7_TX
PIN_GPIO_IO09 OWNER # LPUART7_RX
PIN_WDOG_ANY OWNER
@@ -959,6 +959,7 @@ PIN_GPIO_IO37 OWNER
PIN_I2C2_SCL OWNER
PIN_I2C2_SDA OWNER
PIN_PDM_BIT_STREAM0 OWNER
+PIN_PDM_BIT_STREAM1 OWNER
PIN_PDM_CLK OWNER
PIN_SAI1_RXD0 OWNER
PIN_SAI1_TXC OWNER
@@ -992,6 +993,8 @@ PIN_SD3_DATA2 OWNER
PIN_SD3_DATA3 OWNER
PIN_UART1_RXD OWNER, test
PIN_UART1_TXD OWNER
+PIN_UART2_RXD OWNER
+PIN_UART2_TXD OWNER
PIN_XSPI1_DATA0 OWNER
PIN_XSPI1_DATA1 OWNER
PIN_XSPI1_DATA2 OWNER
diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
index 297806453ee1..3d4b9cad69ad 100644
--- a/configs/ccimx95dvk/config_scmi.h
+++ b/configs/ccimx95dvk/config_scmi.h
@@ -553,6 +553,7 @@
.pinPerms[DEV_SM_PIN_I2C2_SCL] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_I2C2_SDA] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_PDM_BIT_STREAM0] = SM_SCMI_PERM_ALL, \
+ .pinPerms[DEV_SM_PIN_PDM_BIT_STREAM1] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_PDM_CLK] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_SAI1_RXD0] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_SAI1_TXC] = SM_SCMI_PERM_ALL, \
@@ -586,6 +587,8 @@
.pinPerms[DEV_SM_PIN_SD3_DATA3] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_UART1_RXD] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_UART1_TXD] = SM_SCMI_PERM_ALL, \
+ .pinPerms[DEV_SM_PIN_UART2_RXD] = SM_SCMI_PERM_ALL, \
+ .pinPerms[DEV_SM_PIN_UART2_TXD] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_XSPI1_DATA0] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_XSPI1_DATA1] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_XSPI1_DATA2] = SM_SCMI_PERM_ALL, \

151
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0006-ccimx95dvk-move-CAN1-to-be-used-by-A55.patch
View File

@ -1,151 +0,0 @@
From: Hector Palacios <hector.palacios@digi.com>
Date: Wed, 24 Sep 2025 13:01:57 +0200
Subject: [PATCH] ccimx95dvk: move CAN1 to be used by A55
CAN1 is no longer reserved by M7 but instead moved to
non-secure A55 so that it can be used by Linux.
Upstream-Status: Inappropriate [DEY specific]
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
configs/ccimx95dvk.cfg | 3 ++-
configs/ccimx95dvk/config_bctrl.h | 14 +++++++-------
configs/ccimx95dvk/config_scmi.h | 7 ++++---
configs/ccimx95dvk/config_trdc.h | 3 +--
4 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
index 78fad32b4513..c1374d4684a9 100755
--- a/configs/ccimx95dvk.cfg
+++ b/configs/ccimx95dvk.cfg
@@ -383,7 +383,6 @@ SYS ALL
# Resources
M7P OWNER # CPUs must be first
-CAN_FD1 OWNER
FSB READONLY
IRQSTEER_M7 OWNER
LPIT1 OWNER
@@ -482,6 +481,7 @@ CHANNEL db=1, xport=smt, rpc=scmi, type=p2a_notify
PERF_A55 ALL
PERF_DRAM ALL
+PERLPI_CAN1 ALL
PERLPI_CAN2 ALL
PERLPI_CAN3 ALL
PERLPI_CAN4 ALL
@@ -604,6 +604,7 @@ CAMERA5 OWNER
CAMERA6 OWNER
CAMERA7 OWNER
CAMERA8 OWNER
+CAN_FD1 OWNER
CAN_FD2 OWNER
CAN_FD3 OWNER
CAN_FD4 OWNER
diff --git a/configs/ccimx95dvk/config_bctrl.h b/configs/ccimx95dvk/config_bctrl.h
index a757834c32ab..a55abe03ec02 100644
--- a/configs/ccimx95dvk/config_bctrl.h
+++ b/configs/ccimx95dvk/config_bctrl.h
@@ -61,13 +61,13 @@
#define SM_BCTRL_A_CONFIG \
{ \
SM_CFG_W1(0x00000008U), 0x00001804U, \
- SM_CFG_W1(0x0000000CU), 0x0000E56AU, \
- SM_CFG_W1(0x00000010U), 0x0000E56AU, \
- SM_CFG_W1(0x00000014U), 0x0000E56AU, \
- SM_CFG_W1(0x00000018U), 0x0000E56AU, \
- SM_CFG_W1(0x0000001CU), 0x0000E56AU, \
- SM_CFG_W1(0x00000020U), 0x0000E56AU, \
- SM_CFG_W1(0x00000024U), 0x00000291U, \
+ SM_CFG_W1(0x0000000CU), 0x0000E56BU, \
+ SM_CFG_W1(0x00000010U), 0x0000E56BU, \
+ SM_CFG_W1(0x00000014U), 0x0000E56BU, \
+ SM_CFG_W1(0x00000018U), 0x0000E56BU, \
+ SM_CFG_W1(0x0000001CU), 0x0000E56BU, \
+ SM_CFG_W1(0x00000020U), 0x0000E56BU, \
+ SM_CFG_W1(0x00000024U), 0x00000290U, \
SM_CFG_END \
}
diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
index 3d4b9cad69ad..45114d0002f4 100644
--- a/configs/ccimx95dvk/config_scmi.h
+++ b/configs/ccimx95dvk/config_scmi.h
@@ -66,7 +66,6 @@
.secure = 0U, \
.seenvId = 1U, \
.buttonPerms[DEV_SM_BUTTON_0] = SM_SCMI_PERM_NOTIFY, \
- .clkPerms[DEV_SM_CLK_CAN1] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPTMR1] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPTMR2] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_M7SYSTICK] = SM_SCMI_PERM_ALL, \
@@ -76,7 +75,6 @@
.ctrlPerms[BRD_SM_CTRL_PCA2131] = SM_SCMI_PERM_ALL, \
.ctrlPerms[BRD_SM_CTRL_TEST] = SM_SCMI_PERM_ALL, \
.ctrlPerms[BRD_SM_CTRL_TEST_A] = SM_SCMI_PERM_ALL, \
- .daisyPerms[DEV_SM_DAISY_CAN1_RX] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_LPTMR2_0] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_LPTMR2_1] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_LPTMR2_2] = SM_SCMI_PERM_ALL, \
@@ -89,7 +87,6 @@
.lmmPerms[2] = SM_SCMI_PERM_ALL, \
.pdPerms[DEV_SM_PD_M7] = SM_SCMI_PERM_ALL, \
.perfPerms[DEV_SM_PERF_M7] = SM_SCMI_PERM_ALL, \
- .perlpiPerms[DEV_SM_PERLPI_CAN1] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_WDOG5] = SM_SCMI_PERM_ALL, \
.rtcPerms[BRD_SM_RTC_PCA2131] = SM_SCMI_PERM_ALL, \
.rtcPerms[DEV_SM_RTC_BBNSM] = SM_SCMI_PERM_PRIV, \
@@ -172,6 +169,7 @@
.pdPerms[DEV_SM_PD_A55P] = SM_SCMI_PERM_ALL, \
.perfPerms[DEV_SM_PERF_A55] = SM_SCMI_PERM_ALL, \
.perfPerms[DEV_SM_PERF_DRAM] = SM_SCMI_PERM_ALL, \
+ .perlpiPerms[DEV_SM_PERLPI_CAN1] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_CAN2] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_CAN3] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_CAN4] = SM_SCMI_PERM_ALL, \
@@ -228,6 +226,7 @@
.clkPerms[DEV_SM_CLK_AUDIOPLL2] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_AUDIOPLL2_VCO] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_AUDIOXCVR] = SM_SCMI_PERM_ALL, \
+ .clkPerms[DEV_SM_CLK_CAN1] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_CAN2] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_CAN3] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_CAN4] = SM_SCMI_PERM_ALL, \
@@ -318,6 +317,7 @@
.ctrlPerms[DEV_SM_CTRL_SAI3_MCLK] = SM_SCMI_PERM_ALL, \
.ctrlPerms[DEV_SM_CTRL_SAI4_MCLK] = SM_SCMI_PERM_ALL, \
.ctrlPerms[DEV_SM_CTRL_SAI5_MCLK] = SM_SCMI_PERM_ALL, \
+ .daisyPerms[DEV_SM_DAISY_CAN1_RX] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_CAN2_RX] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_CAN3_RX] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_CAN4_RX] = SM_SCMI_PERM_ALL, \
@@ -460,6 +460,7 @@
.perfPerms[DEV_SM_PERF_GPU] = SM_SCMI_PERM_ALL, \
.perfPerms[DEV_SM_PERF_NPU] = SM_SCMI_PERM_ALL, \
.perfPerms[DEV_SM_PERF_VPU] = SM_SCMI_PERM_ALL, \
+ .perlpiPerms[DEV_SM_PERLPI_CAN1] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_CAN2] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_CAN3] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_CAN4] = SM_SCMI_PERM_ALL, \
diff --git a/configs/ccimx95dvk/config_trdc.h b/configs/ccimx95dvk/config_trdc.h
index dc6245097316..12ebbc61ca64 100644
--- a/configs/ccimx95dvk/config_trdc.h
+++ b/configs/ccimx95dvk/config_trdc.h
@@ -123,7 +123,7 @@
SM_CFG_W1(0x00010650U), 0x09000309U, \
SM_CFG_W1(0x00010654U), 0x0000C900U, \
SM_CFG_W1(0x00010658U), 0x99909900U, \
- SM_CFG_W1(0x0001065cU), 0x00009099U, \
+ SM_CFG_W1(0x0001065cU), 0x00009999U, \
SM_CFG_W1(0x00010668U), 0x00009900U, \
SM_CFG_W1(0x0001066cU), 0x90909000U, \
SM_CFG_W1(0x00010670U), 0x00009000U, \
@@ -132,7 +132,6 @@
SM_CFG_Z1(0x00010850U), \
SM_CFG_W1(0x00010854U), 0x9000C000U, \
SM_CFG_W1(0x00010858U), 0x00000099U, \
- SM_CFG_W1(0x0001085cU), 0x00000900U, \
SM_CFG_W1(0x00010870U), 0x00000090U, \
SM_CFG_W1(0x00010874U), 0x00000999U, \
SM_CFG_W1(0x00010980U), 0x900000C0U, \

457
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0007-ccimx95dvk-remove-PCAL6408A-IO-expander-from-EVK.patch
View File

@ -1,457 +0,0 @@
From: Hector Palacios <hector.palacios@digi.com>
Date: Thu, 25 Sep 2025 11:11:20 +0200
Subject: [PATCH] ccimx95dvk: remove PCAL6408A IO expander from EVK
NXP used this I2C IO expander on their EVK to process
wakeup interrupt lines.
This chip is not available on the DVK.
Upstream-Status: Inappropriate [DEY specific]
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
boards/ccimx95dvk/board.c | 1 +
boards/ccimx95dvk/sm/Makefile | 4 +-
boards/ccimx95dvk/sm/brd_sm_bbm.c | 5 +-
boards/ccimx95dvk/sm/brd_sm_control.c | 96 +-------------------------
boards/ccimx95dvk/sm/brd_sm_control.h | 14 ++--
boards/ccimx95dvk/sm/brd_sm_handlers.c | 36 +---------
boards/ccimx95dvk/sm/brd_sm_handlers.h | 21 +-----
configs/ccimx95dvk.cfg | 6 --
configs/ccimx95dvk/config_scmi.h | 6 --
9 files changed, 13 insertions(+), 176 deletions(-)
diff --git a/boards/ccimx95dvk/board.c b/boards/ccimx95dvk/board.c
index fe76d6e1a1a3..2cc8f826b781 100755
--- a/boards/ccimx95dvk/board.c
+++ b/boards/ccimx95dvk/board.c
@@ -1,5 +1,6 @@
/*
* Copyright 2023-2025 NXP
+ * Copyright 2025 Digi International Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/boards/ccimx95dvk/sm/Makefile b/boards/ccimx95dvk/sm/Makefile
index d5b576737636..db27ea922733 100755
--- a/boards/ccimx95dvk/sm/Makefile
+++ b/boards/ccimx95dvk/sm/Makefile
@@ -1,6 +1,7 @@
## ###################################################################
##
## Copyright 2023 NXP
+## Copyright 2025 Digi International Inc.
##
## Redistribution and use in source and binary forms, with or without modification,
## are permitted provided that the following conditions are met:
@@ -40,7 +41,6 @@ INCLUDE += \
-I$(BOARDS_DIR) \
-I$(BOARD_DIR) \
-I$(BOARD_DIR)/sm \
- -I$(COMPONENTS_DIR)/pcal6408a \
-I$(COMPONENTS_DIR)/pf09 \
-I$(COMPONENTS_DIR)/pf53 \
-I$(COMPONENTS_DIR)/pca2131
@@ -50,7 +50,6 @@ VPATH += \
$(BOARDS_DIR) \
$(BOARD_DIR) \
$(BOARD_DIR)/sm \
- $(COMPONENTS_DIR)/pcal6408a \
$(COMPONENTS_DIR)/pf09 \
$(COMPONENTS_DIR)/pf53 \
$(COMPONENTS_DIR)/pca2131
@@ -63,7 +62,6 @@ OBJS += \
$(OUT)/brd_sm_sensor.o \
$(OUT)/brd_sm_voltage.o \
$(OUT)/brd_sm_bbm.o \
- $(OUT)/fsl_pcal6408a.o \
$(OUT)/fsl_pf09.o \
$(OUT)/fsl_pf53.o \
$(OUT)/fsl_pca2131.o
diff --git a/boards/ccimx95dvk/sm/brd_sm_bbm.c b/boards/ccimx95dvk/sm/brd_sm_bbm.c
index 6103583ff69d..2c5cc953b1e2 100755
--- a/boards/ccimx95dvk/sm/brd_sm_bbm.c
+++ b/boards/ccimx95dvk/sm/brd_sm_bbm.c
@@ -2,6 +2,7 @@
** ###################################################################
**
** Copyright 2025 NXP
+** Copyright 2025 Digi International Inc.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
@@ -432,8 +433,6 @@ int32_t BRD_SM_BbmRtcAlarmSet(uint32_t rtcId, bool enable, uint64_t val)
/* Enable interrupt */
if (PCA2131_IntEnable(&g_pca2131Dev, true))
{
- /* Enable bus expander interrupt */
- status = BRD_SM_BusExpMaskSet(0U, BIT8(6));
}
else
{
@@ -457,8 +456,6 @@ int32_t BRD_SM_BbmRtcAlarmSet(uint32_t rtcId, bool enable, uint64_t val)
/* Disable interrupt */
if (PCA2131_IntEnable(&g_pca2131Dev, false))
{
- /* Disable bus expander interrupt */
- status = BRD_SM_BusExpMaskSet(BIT8(6), BIT8(6));
}
else
{
diff --git a/boards/ccimx95dvk/sm/brd_sm_control.c b/boards/ccimx95dvk/sm/brd_sm_control.c
index fde28d939fca..76de9fad9e86 100755
--- a/boards/ccimx95dvk/sm/brd_sm_control.c
+++ b/boards/ccimx95dvk/sm/brd_sm_control.c
@@ -2,6 +2,7 @@
** ###################################################################
**
** Copyright 2023-2025 NXP
+** Copyright 2025 Digi International Inc.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
@@ -44,13 +45,6 @@
/* Local defines */
-/* PCAL6408A input signals */
-#define PCAL6408A_INPUT_SD3_WAKE 0U
-#define PCAL6408A_INPUT_PCIE1_WAKE 4U
-#define PCAL6408A_INPUT_BT_WAKE 5U
-#define PCAL6408A_INPUT_PCIE2_WAKE 6U
-#define PCAL6408A_INPUT_BUTTON 7U
-
/* Local types */
/* Local variables */
@@ -105,26 +99,7 @@ int32_t BRD_SM_ControlGet(uint32_t ctrlId, uint32_t *numRtn, uint32_t *rtn)
}
else if (ctrlId < BRD_SM_CTRL_TEST)
{
- uint8_t data;
-
- /* Read expander data input */
- if (PCAL6408A_InputGet(&g_pcal6408aDev, &data))
- {
- uint32_t shift = ctrlId - DEV_SM_NUM_CTRL;
-
- /* Adjust bit position */
- if (shift > 0U)
- {
- shift += 3U;
- }
-
- *numRtn = 1U;
- rtn[0] = (((uint32_t) data) >> shift) & 0x1UL;
- }
- else
- {
- status = SM_ERR_HARDWARE_ERROR;
- }
+ status = SM_ERR_HARDWARE_ERROR;
}
else
{
@@ -270,41 +245,12 @@ int32_t BRD_SM_ControlFlagsSet(uint32_t ctrlId, uint32_t flags)
}
else
{
- uint8_t mask;
- uint32_t val;
- uint32_t enb = (flags != 0U) ? 0U : 1U;
-
switch (ctrlId)
{
- case BRD_SM_CTRL_SD3_WAKE:
- mask = BIT8(PCAL6408A_INPUT_SD3_WAKE);
- val = (enb & 0x1U) << PCAL6408A_INPUT_SD3_WAKE;
- break;
- case BRD_SM_CTRL_PCIE1_WAKE:
- mask = BIT8(PCAL6408A_INPUT_PCIE1_WAKE);
- val = (enb & 0x1U) << PCAL6408A_INPUT_PCIE1_WAKE;
- break;
- case BRD_SM_CTRL_BT_WAKE:
- mask = BIT8(PCAL6408A_INPUT_BT_WAKE);
- val = (enb & 0x1U) << PCAL6408A_INPUT_BT_WAKE;
- break;
- case BRD_SM_CTRL_PCIE2_WAKE:
- mask = BIT8(PCAL6408A_INPUT_PCIE2_WAKE);
- val = (enb & 0x1U) << PCAL6408A_INPUT_PCIE2_WAKE;
- break;
- case BRD_SM_CTRL_BUTTON:
- mask = BIT8(PCAL6408A_INPUT_BUTTON);
- val = (enb & 0x1U) << PCAL6408A_INPUT_BUTTON;
- break;
default:
status = SM_ERR_NOT_FOUND;
break;
}
-
- if (status == SM_ERR_SUCCESS)
- {
- status = BRD_SM_BusExpMaskSet((uint8_t) val, mask);
- }
}
return status;
@@ -315,42 +261,6 @@ int32_t BRD_SM_ControlFlagsSet(uint32_t ctrlId, uint32_t flags)
/*--------------------------------------------------------------------------*/
void BRD_SM_ControlHandler(uint8_t status, uint8_t val)
{
- uint32_t data = (uint32_t) val;
-
- /* Handle SD3 wake */
- if ((status & BIT8(PCAL6408A_INPUT_SD3_WAKE)) != 0U)
- {
- LMM_MiscControlEvent(BRD_SM_CTRL_SD3_WAKE,
- ((data >> PCAL6408A_INPUT_SD3_WAKE) & 0x1U) + 1U);
- }
-
- /* Handle PCIe1 wake */
- if ((status & BIT8(PCAL6408A_INPUT_PCIE1_WAKE)) != 0U)
- {
- LMM_MiscControlEvent(BRD_SM_CTRL_PCIE1_WAKE,
- ((data >> PCAL6408A_INPUT_PCIE1_WAKE) & 0x1U) + 1U);
- }
-
- /* Handle BT wake */
- if ((status & BIT8(PCAL6408A_INPUT_BT_WAKE)) != 0U)
- {
- LMM_MiscControlEvent(BRD_SM_CTRL_BT_WAKE,
- ((data >> PCAL6408A_INPUT_BT_WAKE) & 0x1U) + 1U);
- }
-
- /* Handle PCIe2 wake */
- if (((status & BIT8(PCAL6408A_INPUT_PCIE2_WAKE)) != 0U)
- && !g_pca2131Used)
- {
- LMM_MiscControlEvent(BRD_SM_CTRL_PCIE2_WAKE,
- ((data >> PCAL6408A_INPUT_PCIE2_WAKE) & 0x1U) + 1U);
- }
-
- /* Handle button */
- if ((status & BIT8(PCAL6408A_INPUT_BUTTON)) != 0U)
- {
- LMM_MiscControlEvent(BRD_SM_CTRL_BUTTON,
- ((data >> PCAL6408A_INPUT_BUTTON) & 0x1U) + 1U);
- }
+ // Call pertinent LMM_MiscControlEvent()
}
diff --git a/boards/ccimx95dvk/sm/brd_sm_control.h b/boards/ccimx95dvk/sm/brd_sm_control.h
index 30ad8e67eb6f..9c61bce72f8e 100755
--- a/boards/ccimx95dvk/sm/brd_sm_control.h
+++ b/boards/ccimx95dvk/sm/brd_sm_control.h
@@ -2,6 +2,7 @@
** ###################################################################
**
** Copyright 2023-2025 NXP
+** Copyright 2025 Digi International Inc.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
@@ -67,7 +68,7 @@
/** @} */
/*! Number of board controls */
-#define BRD_SM_NUM_CTRL 8UL
+#define BRD_SM_NUM_CTRL 3UL
/*! Total number of controls */
#define SM_NUM_CTRL (DEV_SM_NUM_CTRL + BRD_SM_NUM_CTRL)
@@ -76,14 +77,9 @@
* @name BRD_SM control domain indexes
*/
/** @{ */
-#define BRD_SM_CTRL_SD3_WAKE (DEV_SM_NUM_CTRL + 0U) /*!< PCAL6408A-0 */
-#define BRD_SM_CTRL_PCIE1_WAKE (DEV_SM_NUM_CTRL + 1U) /*!< PCAL6408A-4 */
-#define BRD_SM_CTRL_BT_WAKE (DEV_SM_NUM_CTRL + 2U) /*!< PCAL6408A-5 */
-#define BRD_SM_CTRL_PCIE2_WAKE (DEV_SM_NUM_CTRL + 3U) /*!< PCAL6408A-6 */
-#define BRD_SM_CTRL_BUTTON (DEV_SM_NUM_CTRL + 4U) /*!< PCAL6408A-7 */
-#define BRD_SM_CTRL_TEST (DEV_SM_NUM_CTRL + 5U) /*!< Test */
-#define BRD_SM_CTRL_PCA2131 (DEV_SM_NUM_CTRL + 6U) /*!< PCA2131 raw access */
-#define BRD_SM_CTRL_TEST_A (DEV_SM_NUM_CTRL + 7U) /*!< Test action */
+#define BRD_SM_CTRL_TEST (DEV_SM_NUM_CTRL + 0U) /*!< Test */
+#define BRD_SM_CTRL_PCA2131 (DEV_SM_NUM_CTRL + 1U) /*!< PCA2131 raw access */
+#define BRD_SM_CTRL_TEST_A (DEV_SM_NUM_CTRL + 2U) /*!< Test action */
/** @} */
/* Types */
diff --git a/boards/ccimx95dvk/sm/brd_sm_handlers.c b/boards/ccimx95dvk/sm/brd_sm_handlers.c
index 19ee28e93134..a42359f15e8b 100755
--- a/boards/ccimx95dvk/sm/brd_sm_handlers.c
+++ b/boards/ccimx95dvk/sm/brd_sm_handlers.c
@@ -2,6 +2,7 @@
** ###################################################################
**
** Copyright 2023-2025 NXP
+** Copyright 2025 Digi International Inc.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
@@ -48,23 +49,16 @@
/* I2C device addresses */
#define BOARD_PF09_DEV_ADDR 0x08U
-#define BOARD_PCAL6408A_DEV_ADDR 0x20U
#define BOARD_PF5301_DEV_ADDR 0x2AU
#define BOARD_PF5302_DEV_ADDR 0x29U
#define BOARD_PCA2131_DEV_ADDR 0x53U
-#define PCAL6408A_INPUT_PF53_ARM_PG 1U
-#define PCAL6408A_INPUT_PF53_SOC_PG 2U
-#define PCAL6408A_INPUT_PF09_INT 3U
-#define PCAL6408A_INPUT_PCA2131_INT 6U
-
/* Local types */
/* Local variables */
/* Global variables */
-PCAL6408A_Type g_pcal6408aDev;
PF09_Type g_pf09Dev;
PF53_Type g_pf5301Dev;
PF53_Type g_pf5302Dev;
@@ -238,34 +232,6 @@ int32_t BRD_SM_SerialDevicesInit(void)
return status;
}
-/*--------------------------------------------------------------------------*/
-/* Set bus expander interrupt mask */
-/*--------------------------------------------------------------------------*/
-int32_t BRD_SM_BusExpMaskSet(uint8_t val, uint8_t mask)
-{
- int32_t status = SM_ERR_SUCCESS;
- static uint8_t cachedMask = PCAL6408A_INITIAL_MASK;
- uint8_t newMask = (cachedMask & ~mask);
-
- newMask |= val;
-
- /* Mask changed? */
- if (cachedMask != newMask)
- {
- if (PCAL6408A_IntMaskSet(&g_pcal6408aDev, newMask))
- {
- cachedMask = newMask;
- }
- else
- {
- status = SM_ERR_HARDWARE_ERROR;
- }
- }
-
- /* Return status */
- return status;
-}
-
/*==========================================================================*/
/*--------------------------------------------------------------------------*/
diff --git a/boards/ccimx95dvk/sm/brd_sm_handlers.h b/boards/ccimx95dvk/sm/brd_sm_handlers.h
index e34d52b50f7a..781a443e8444 100755
--- a/boards/ccimx95dvk/sm/brd_sm_handlers.h
+++ b/boards/ccimx95dvk/sm/brd_sm_handlers.h
@@ -2,6 +2,7 @@
** ###################################################################
**
** Copyright 2023-2024 NXP
+** Copyright 2025 Digi International Inc.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
@@ -52,16 +53,12 @@
#include "sm.h"
#include "dev_sm.h"
-#include "fsl_pcal6408a.h"
#include "fsl_pf09.h"
#include "fsl_pf53.h"
#include "fsl_pca2131.h"
/* Defines */
-/*! Initial PCAL6408A interrupt mask */
-#define PCAL6408A_INITIAL_MASK 0xF7U
-
/*! Number of board IRQs participating dynamic prioritization */
#define BOARD_NUM_IRQ_PRIO_IDX 1U
@@ -72,9 +69,6 @@
/* External variables */
-/*! Handle to access PCAL6408A */
-extern PCAL6408A_Type g_pcal6408aDev;
-
/*! Handle to access PF09 */
extern PF09_Type g_pf09Dev;
@@ -105,19 +99,6 @@ extern uint32_t g_pmicFaultFlags;
*/
int32_t BRD_SM_SerialDevicesInit(void);
-/*!
- * Enable/disable bus expander interrupts.
- *
- * @param[in] val Value to write
- * @param[in] mask Mask of bits to modify
- *
- * This function allows a caller to configure the bus expander.
- * interrupts.
- *
- * @return Returns the status (::SM_ERR_SUCCESS = success).
- */
-int32_t BRD_SM_BusExpMaskSet(uint8_t val, uint8_t mask);
-
/*!
* GPIO 1 interrupt 0 handler.
*/
diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
index c1374d4684a9..c3c280d275b0 100755
--- a/configs/ccimx95dvk.cfg
+++ b/configs/ccimx95dvk.cfg
@@ -365,7 +365,6 @@ CHANNEL db=2, xport=smt, check=crc32, rpc=scmi, \
# API
-BRD_SM_CTRL_BUTTON NOTIFY
BRD_SM_CTRL_PCA2131 ALL
BRD_SM_CTRL_TEST ALL
BRD_SM_CTRL_TEST_A ALL
@@ -553,11 +552,6 @@ CHANNEL db=1, xport=smt, rpc=scmi, type=p2a_notify
AUDIO_PLL1 ALL
AUDIO_PLL2 ALL
-BRD_SM_CTRL_BT_WAKE NOTIFY
-BRD_SM_CTRL_BUTTON NOTIFY
-BRD_SM_CTRL_PCIE1_WAKE NOTIFY
-BRD_SM_CTRL_PCIE2_WAKE NOTIFY
-BRD_SM_CTRL_SD3_WAKE NOTIFY
BRD_SM_CTRL_TEST_A ALL
BRD_SM_RTC_PCA2131 PRIV
BRD_SM_SENSOR_TEMP_PF09 ALL
diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
index 45114d0002f4..83d7bd94bcd1 100644
--- a/configs/ccimx95dvk/config_scmi.h
+++ b/configs/ccimx95dvk/config_scmi.h
@@ -71,7 +71,6 @@
.clkPerms[DEV_SM_CLK_M7SYSTICK] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_TSTMR2] = SM_SCMI_PERM_ALL, \
.cpuPerms[DEV_SM_CPU_M7P] = SM_SCMI_PERM_ALL, \
- .ctrlPerms[BRD_SM_CTRL_BUTTON] = SM_SCMI_PERM_NOTIFY, \
.ctrlPerms[BRD_SM_CTRL_PCA2131] = SM_SCMI_PERM_ALL, \
.ctrlPerms[BRD_SM_CTRL_TEST] = SM_SCMI_PERM_ALL, \
.ctrlPerms[BRD_SM_CTRL_TEST_A] = SM_SCMI_PERM_ALL, \
@@ -304,11 +303,6 @@
.clkPerms[DEV_SM_CLK_VIDEOPLL1_VCO] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_VPUDSP] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_XSPISLVROOT] = SM_SCMI_PERM_ALL, \
- .ctrlPerms[BRD_SM_CTRL_BT_WAKE] = SM_SCMI_PERM_NOTIFY, \
- .ctrlPerms[BRD_SM_CTRL_BUTTON] = SM_SCMI_PERM_NOTIFY, \
- .ctrlPerms[BRD_SM_CTRL_PCIE1_WAKE] = SM_SCMI_PERM_NOTIFY, \
- .ctrlPerms[BRD_SM_CTRL_PCIE2_WAKE] = SM_SCMI_PERM_NOTIFY, \
- .ctrlPerms[BRD_SM_CTRL_SD3_WAKE] = SM_SCMI_PERM_NOTIFY, \
.ctrlPerms[BRD_SM_CTRL_TEST_A] = SM_SCMI_PERM_ALL, \
.ctrlPerms[DEV_SM_CTRL_ADC_TEST] = SM_SCMI_PERM_ALL, \
.ctrlPerms[DEV_SM_CTRL_MQS1_SETTINGS] = SM_SCMI_PERM_ALL, \

1228
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0008-ccimx95dvk-remove-PCA2123-RTC-from-EVK.patch
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276
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0009-ccimx95-change-names-of-voltage-regulators.patch
View File

@ -1,276 +0,0 @@
From: Hector Palacios <hector.palacios@digi.com>
Date: Mon, 29 Sep 2025 13:02:02 +0200
Subject: [PATCH] ccimx95: change names of voltage regulators
Change the names of voltage regulators for easier identification.
Use the PMIC regulator (SW1, SW2, LDO1...) and then the name of the power
rail used in the SOM.
Upstream-Status: Inappropriate [DEY specific]
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
boards/ccimx95dvk/sm/brd_sm_voltage.c | 85 ++++++++++++++-------------
boards/ccimx95dvk/sm/brd_sm_voltage.h | 15 ++---
2 files changed, 51 insertions(+), 49 deletions(-)
diff --git a/boards/ccimx95dvk/sm/brd_sm_voltage.c b/boards/ccimx95dvk/sm/brd_sm_voltage.c
index b81ffd970294..d7e7c9b3ea27 100755
--- a/boards/ccimx95dvk/sm/brd_sm_voltage.c
+++ b/boards/ccimx95dvk/sm/brd_sm_voltage.c
@@ -2,6 +2,7 @@
** ###################################################################
**
** Copyright 2023-2025 NXP
+** Copyright 2025 Digi International Inc.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
@@ -63,13 +64,13 @@ int32_t BRD_SM_VoltageNameGet(uint32_t domainId, string *voltNameAddr,
static string const s_name[BRD_SM_NUM_VOLT] =
{
- "vdd_gpio_3p3",
- "vdd_ana_0p8",
- "vdd_gpio_1p8",
- "vddq_ddr",
- "vdd2_ddr",
- "sd_card",
- "nvcc_sd2"
+ "vdd_3v3",
+ "vdd_ana_0v8",
+ "vdd_1v8",
+ "lpd5_vddq",
+ "lpd5_vdd2",
+ "vdd_ldo1",
+ "vdd_sdio2"
};
/* Get max string width */
@@ -117,25 +118,25 @@ int32_t BRD_SM_VoltageDescribe(uint32_t domainId,
case DEV_SM_VOLT_ARM:
status = DEV_SM_VoltageDescribe(domainId, range);
break;
- case BRD_SM_VOLT_VDD_GPIO_3P3:
+ case BRD_SM_VOLT_SW1_VDD_3V3:
rc = PF09_RegulatorInfoGet(PF09_REG_SW1, &info);
break;
- case BRD_SM_VOLT_VDD_ANA_0P8:
+ case BRD_SM_VOLT_SW2_VDD_ANA_0V8:
rc = PF09_RegulatorInfoGet(PF09_REG_SW2, &info);
break;
- case BRD_SM_VOLT_VDD_GPIO_1P8:
+ case BRD_SM_VOLT_SW3_VDD_1V8:
rc = PF09_RegulatorInfoGet(PF09_REG_SW3, &info);
break;
- case BRD_SM_VOLT_VDDQ_DDR:
+ case BRD_SM_VOLT_SW4_LPD5_VDDQ:
rc = PF09_RegulatorInfoGet(PF09_REG_SW4, &info);
break;
- case BRD_SM_VOLT_VDD2_DDR:
+ case BRD_SM_VOLT_SW5_LPD5_VDD2:
rc = PF09_RegulatorInfoGet(PF09_REG_SW5, &info);
break;
- case BRD_SM_VOLT_SD_CARD:
+ case BRD_SM_VOLT_LDO1_VDD_LDO1:
rc = PF09_RegulatorInfoGet(PF09_REG_LDO1, &info);
break;
- case BRD_SM_VOLT_NVCC_SD2:
+ case BRD_SM_VOLT_LDO2_VDD_SDIO2:
rc = PF09_RegulatorInfoGet(PF09_REG_LDO2, &info);
break;
default:
@@ -206,31 +207,31 @@ int32_t BRD_SM_VoltageModeSet(uint32_t domainId, uint8_t voltMode)
s_modeArm = voltMode;
}
break;
- case BRD_SM_VOLT_VDD_GPIO_3P3:
+ case BRD_SM_VOLT_SW1_VDD_3V3:
rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
mode);
break;
- case BRD_SM_VOLT_VDD_ANA_0P8:
+ case BRD_SM_VOLT_SW2_VDD_ANA_0V8:
rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
mode);
break;
- case BRD_SM_VOLT_VDD_GPIO_1P8:
+ case BRD_SM_VOLT_SW3_VDD_1V8:
rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
mode);
break;
- case BRD_SM_VOLT_VDDQ_DDR:
+ case BRD_SM_VOLT_SW4_LPD5_VDDQ:
rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
mode);
break;
- case BRD_SM_VOLT_VDD2_DDR:
+ case BRD_SM_VOLT_SW5_LPD5_VDD2:
rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
mode);
break;
- case BRD_SM_VOLT_SD_CARD:
+ case BRD_SM_VOLT_LDO1_VDD_LDO1:
rc = PF09_LdoEnable(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
enable);
break;
- case BRD_SM_VOLT_NVCC_SD2:
+ case BRD_SM_VOLT_LDO2_VDD_SDIO2:
rc = PF09_LdoEnable(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
enable);
break;
@@ -271,36 +272,36 @@ int32_t BRD_SM_VoltageModeGet(uint32_t domainId, uint8_t *voltMode)
rc = PF09_GpioCtrlGet(&g_pf09Dev, PF09_GPIO4, PF53_STATE_VRUN,
&enable);
break;
- case BRD_SM_VOLT_VDD_GPIO_3P3:
+ case BRD_SM_VOLT_SW1_VDD_3V3:
rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
&mode);
enable = (mode != PF09_SW_MODE_OFF);
break;
- case BRD_SM_VOLT_VDD_ANA_0P8:
+ case BRD_SM_VOLT_SW2_VDD_ANA_0V8:
rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
&mode);
enable = (mode != PF09_SW_MODE_OFF);
break;
- case BRD_SM_VOLT_VDD_GPIO_1P8:
+ case BRD_SM_VOLT_SW3_VDD_1V8:
rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
&mode);
enable = (mode != PF09_SW_MODE_OFF);
break;
- case BRD_SM_VOLT_VDDQ_DDR:
+ case BRD_SM_VOLT_SW4_LPD5_VDDQ:
rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
&mode);
enable = (mode != PF09_SW_MODE_OFF);
break;
- case BRD_SM_VOLT_VDD2_DDR:
+ case BRD_SM_VOLT_SW5_LPD5_VDD2:
rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
&mode);
enable = (mode != PF09_SW_MODE_OFF);
break;
- case BRD_SM_VOLT_SD_CARD:
+ case BRD_SM_VOLT_LDO1_VDD_LDO1:
rc = PF09_LdoIsEnabled(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
&enable);
break;
- case BRD_SM_VOLT_NVCC_SD2:
+ case BRD_SM_VOLT_LDO2_VDD_SDIO2:
rc = PF09_LdoIsEnabled(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
&enable);
break;
@@ -359,31 +360,31 @@ int32_t BRD_SM_VoltageLevelSet(uint32_t domainId, int32_t voltageLevel)
s_levelArm = (int32_t) level;
rc = true;
break;
- case BRD_SM_VOLT_VDD_GPIO_3P3:
+ case BRD_SM_VOLT_SW1_VDD_3V3:
rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
level);
break;
- case BRD_SM_VOLT_VDD_ANA_0P8:
+ case BRD_SM_VOLT_SW2_VDD_ANA_0V8:
rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
level);
break;
- case BRD_SM_VOLT_VDD_GPIO_1P8:
+ case BRD_SM_VOLT_SW3_VDD_1V8:
rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
level);
break;
- case BRD_SM_VOLT_VDDQ_DDR:
+ case BRD_SM_VOLT_SW4_LPD5_VDDQ:
rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
level);
break;
- case BRD_SM_VOLT_VDD2_DDR:
+ case BRD_SM_VOLT_SW5_LPD5_VDD2:
rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
level);
break;
- case BRD_SM_VOLT_SD_CARD:
+ case BRD_SM_VOLT_LDO1_VDD_LDO1:
rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
level);
break;
- case BRD_SM_VOLT_NVCC_SD2:
+ case BRD_SM_VOLT_LDO2_VDD_SDIO2:
rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
level);
break;
@@ -458,31 +459,31 @@ int32_t BRD_SM_VoltageLevelGet(uint32_t domainId, int32_t *voltageLevel)
}
}
break;
- case BRD_SM_VOLT_VDD_GPIO_3P3:
+ case BRD_SM_VOLT_SW1_VDD_3V3:
rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
&level);
break;
- case BRD_SM_VOLT_VDD_ANA_0P8:
+ case BRD_SM_VOLT_SW2_VDD_ANA_0V8:
rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
&level);
break;
- case BRD_SM_VOLT_VDD_GPIO_1P8:
+ case BRD_SM_VOLT_SW3_VDD_1V8:
rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
&level);
break;
- case BRD_SM_VOLT_VDDQ_DDR:
+ case BRD_SM_VOLT_SW4_LPD5_VDDQ:
rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
&level);
break;
- case BRD_SM_VOLT_VDD2_DDR:
+ case BRD_SM_VOLT_SW5_LPD5_VDD2:
rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
&level);
break;
- case BRD_SM_VOLT_SD_CARD:
+ case BRD_SM_VOLT_LDO1_VDD_LDO1:
rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
&level);
break;
- case BRD_SM_VOLT_NVCC_SD2:
+ case BRD_SM_VOLT_LDO2_VDD_SDIO2:
rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
&level);
break;
diff --git a/boards/ccimx95dvk/sm/brd_sm_voltage.h b/boards/ccimx95dvk/sm/brd_sm_voltage.h
index 6c9e01286e7e..46ddc9d89096 100755
--- a/boards/ccimx95dvk/sm/brd_sm_voltage.h
+++ b/boards/ccimx95dvk/sm/brd_sm_voltage.h
@@ -2,6 +2,7 @@
** ###################################################################
**
** Copyright 2023-2024 NXP
+** Copyright 2025 Digi International Inc.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
@@ -76,13 +77,13 @@
* @name BRD_SM voltage domains
*/
/** @{ */
-#define BRD_SM_VOLT_VDD_GPIO_3P3 (DEV_SM_NUM_VOLT + 0U) /*!< VDD GPIO 3.3v */
-#define BRD_SM_VOLT_VDD_ANA_0P8 (DEV_SM_NUM_VOLT + 1U) /*!< VDD ANA 0.8v */
-#define BRD_SM_VOLT_VDD_GPIO_1P8 (DEV_SM_NUM_VOLT + 2U) /*!< VDD GPIO 1.8v */
-#define BRD_SM_VOLT_VDDQ_DDR (DEV_SM_NUM_VOLT + 3U) /*!< DDR VDDQ */
-#define BRD_SM_VOLT_VDD2_DDR (DEV_SM_NUM_VOLT + 4U) /*!< DDR VDD2 */
-#define BRD_SM_VOLT_SD_CARD (DEV_SM_NUM_VOLT + 5U) /*!< SD1 */
-#define BRD_SM_VOLT_NVCC_SD2 (DEV_SM_NUM_VOLT + 6U) /*!< SD2 */
+#define BRD_SM_VOLT_SW1_VDD_3V3 (DEV_SM_NUM_VOLT + 0U) /*!< VDD 3V3 */
+#define BRD_SM_VOLT_SW2_VDD_ANA_0V8 (DEV_SM_NUM_VOLT + 1U) /*!< VDD ANA 0V8 */
+#define BRD_SM_VOLT_SW3_VDD_1V8 (DEV_SM_NUM_VOLT + 2U) /*!< VDD 1V8 */
+#define BRD_SM_VOLT_SW4_LPD5_VDDQ (DEV_SM_NUM_VOLT + 3U) /*!< DDR VDDQ */
+#define BRD_SM_VOLT_SW5_LPD5_VDD2 (DEV_SM_NUM_VOLT + 4U) /*!< DDR VDD2 */
+#define BRD_SM_VOLT_LDO1_VDD_LDO1 (DEV_SM_NUM_VOLT + 5U) /*!< LDO1 */
+#define BRD_SM_VOLT_LDO2_VDD_SDIO2 (DEV_SM_NUM_VOLT + 6U) /*!< LDO2 (VDD_SDIO2) */
/** @} */
/* Types */

49
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0010-ccimx95dvk-enable-full-access-to-certain-regulators-.patch
View File

@ -1,49 +0,0 @@
From: Hector Palacios <hector.palacios@digi.com>
Date: Thu, 9 Oct 2025 13:16:00 +0200
Subject: [PATCH] ccimx95dvk: enable full access to certain regulators from
non-secure LVM
The following PMIC regulators are used by the DVK:
- VDD_3V3 (SW1)
- VDD_1V8 (SW3)
- VDD_LDO1 (LDO1)
- VDD_SDIO2 (LDO2)
Upstream-Status: Inappropriate [DEY specific]
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
configs/ccimx95dvk.cfg | 4 ++++
configs/ccimx95dvk/config_scmi.h | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
index c160dbce0b85..d7ee4d0115fa 100755
--- a/configs/ccimx95dvk.cfg
+++ b/configs/ccimx95dvk.cfg
@@ -554,6 +554,10 @@ BRD_SM_CTRL_TEST_A ALL
BRD_SM_SENSOR_TEMP_PF09 ALL
BRD_SM_SENSOR_TEMP_PF5301 SET
BRD_SM_SENSOR_TEMP_PF5302 SET
+BRD_SM_VOLT_SW1_VDD_3V3 ALL
+BRD_SM_VOLT_SW3_VDD_1V8 ALL
+BRD_SM_VOLT_LDO1_VDD_LDO1 ALL
+BRD_SM_VOLT_LDO2_VDD_SDIO2 ALL
BUTTON ALL, test
CLOCK_DISP1PIX ALL
CLOCK_DISP2PIX ALL
diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
index 87de1fd591ca..83084a9d1fbd 100644
--- a/configs/ccimx95dvk/config_scmi.h
+++ b/configs/ccimx95dvk/config_scmi.h
@@ -601,6 +601,10 @@
.sensorPerms[DEV_SM_SENSOR_TEMP_A55] = SM_SCMI_PERM_ALL, \
.sensorPerms[DEV_SM_SENSOR_TEMP_ANA] = SM_SCMI_PERM_SET, \
.sysPerms = SM_SCMI_PERM_NOTIFY, \
+ .voltPerms[BRD_SM_VOLT_LDO1_VDD_LDO1] = SM_SCMI_PERM_ALL, \
+ .voltPerms[BRD_SM_VOLT_LDO2_VDD_SDIO2] = SM_SCMI_PERM_ALL, \
+ .voltPerms[BRD_SM_VOLT_SW1_VDD_3V3] = SM_SCMI_PERM_ALL, \
+ .voltPerms[BRD_SM_VOLT_SW3_VDD_1V8] = SM_SCMI_PERM_ALL, \
}
/*! Config for SCMI channel 5 */

39
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0011-components-pf09-reduce-LDOs-step-to-50mV.patch
View File

@ -1,39 +0,0 @@
From: Hector Palacios <hector.palacios@digi.com>
Date: Mon, 13 Oct 2025 08:49:57 +0200
Subject: [PATCH] components: pf09: reduce LDOs step to 50mV
The voltage values that can be programmed to the LDOs are not linear.
For low voltages, the step is 50mV, but for higher voltages it is 100mV.
Setting the step as 100mV fools the Linux kernel regulator framework
which does not properly calculate the selector it must call when using
the SCMI regulator framework, resulting in -EINVAL errors.
Upstream-Status: Inappropriate [DEY specific]
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
components/pf09/fsl_pf09.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/components/pf09/fsl_pf09.c b/components/pf09/fsl_pf09.c
index fc0638cbdba5..5d842c9a3062 100755
--- a/components/pf09/fsl_pf09.c
+++ b/components/pf09/fsl_pf09.c
@@ -528,7 +528,7 @@ bool PF09_RegulatorInfoGet(uint8_t regulator, PF09_RegInfo *regInfo)
/* set min/max/step in microvolts */
regInfo->minV = 750000U;
regInfo->maxV = 3300000U;
- regInfo->stepV = 100000U;
+ regInfo->stepV = 50000U;
}
break;
case PF09_REG_LDO2:
@@ -537,7 +537,7 @@ bool PF09_RegulatorInfoGet(uint8_t regulator, PF09_RegInfo *regInfo)
/* set min/max/step in microvolts */
regInfo->minV = 650000U;
regInfo->maxV = 3300000U;
- regInfo->stepV = 100000U;
+ regInfo->stepV = 50000U;
}
break;
default:

60
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0012-ccimx95dvk-remove-access-to-VDD_3V3-and-VDD_1V8-from.patch
View File

@ -1,60 +0,0 @@
From: Hector Palacios <hector.palacios@digi.com>
Date: Wed, 29 Oct 2025 16:54:45 +0100
Subject: [PATCH] ccimx95dvk: remove access to VDD_3V3 and VDD_1V8 from
non-secure world
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
There doesn't seem to be a clear registered handler for reboot or shutdown
path from Linux to SM.
When a 'reboot' is requested, Linux falls back to run the global
device_shutdown() path.
The SM will turn these regulators off in their shutdown path or via a
global “disable regulators on reboot” policy. The current SM firmware
doesn't get to know if Linux has marked these regulators as "always-on".
Powering these regulators off removes power to the SOM who is then not
able to continue the reset (it is not powered).
By removing access to Linux, we fully rely on SM managing these regulators,
though apparently support is incomplete (for instance they are not powered
off on the poweroff path from Linux), so this may need to be revisited in
future BSP upgrades.
Upstream-Status: Inappropriate [DEY specific]
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
https://onedigi.atlassian.net/browse/DEL-9804
---
configs/ccimx95dvk.cfg | 2 --
configs/ccimx95dvk/config_scmi.h | 2 --
2 files changed, 4 deletions(-)
diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
index d7ee4d0115fa..b73401792592 100755
--- a/configs/ccimx95dvk.cfg
+++ b/configs/ccimx95dvk.cfg
@@ -554,8 +554,6 @@ BRD_SM_CTRL_TEST_A ALL
BRD_SM_SENSOR_TEMP_PF09 ALL
BRD_SM_SENSOR_TEMP_PF5301 SET
BRD_SM_SENSOR_TEMP_PF5302 SET
-BRD_SM_VOLT_SW1_VDD_3V3 ALL
-BRD_SM_VOLT_SW3_VDD_1V8 ALL
BRD_SM_VOLT_LDO1_VDD_LDO1 ALL
BRD_SM_VOLT_LDO2_VDD_SDIO2 ALL
BUTTON ALL, test
diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
index 83084a9d1fbd..506cb750af65 100644
--- a/configs/ccimx95dvk/config_scmi.h
+++ b/configs/ccimx95dvk/config_scmi.h
@@ -603,8 +603,6 @@
.sysPerms = SM_SCMI_PERM_NOTIFY, \
.voltPerms[BRD_SM_VOLT_LDO1_VDD_LDO1] = SM_SCMI_PERM_ALL, \
.voltPerms[BRD_SM_VOLT_LDO2_VDD_SDIO2] = SM_SCMI_PERM_ALL, \
- .voltPerms[BRD_SM_VOLT_SW1_VDD_3V3] = SM_SCMI_PERM_ALL, \
- .voltPerms[BRD_SM_VOLT_SW3_VDD_1V8] = SM_SCMI_PERM_ALL, \
}
/*! Config for SCMI channel 5 */

226
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0013-ccimx95dvk-change-SM-console-from-LPUART7-to-LPUART2.patch
View File

@ -1,226 +0,0 @@
From: Hector Palacios <hector.palacios@digi.com>
Date: Wed, 14 Jan 2026 16:03:29 +0100
Subject: [PATCH] ccimx95dvk: change SM console from LPUART7 to LPUART2
On version 2 of the SOM, the SM console has changed to LPUART2.
Upstream-Status: Inappropriate [DEY specific]
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
https://onedigi.atlassian.net/browse/DEL-9915
---
configs/ccimx95dvk.cfg | 18 +++++++++---------
configs/ccimx95dvk/config_board.h | 2 +-
configs/ccimx95dvk/config_scmi.h | 12 +++++++-----
configs/ccimx95dvk/config_trdc.h | 7 +++----
4 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
index b73401792592..53444e785270 100755
--- a/configs/ccimx95dvk.cfg
+++ b/configs/ccimx95dvk.cfg
@@ -1,7 +1,7 @@
## ###################################################################
##
## Copyright 2023-2025 NXP
-## Copyright 2025 Digi International Inc.
+## Copyright 2025,2026 Digi International Inc.
##
## Redistribution and use in source and binary forms, with or without modification,
## are permitted provided that the following conditions are met:
@@ -42,7 +42,7 @@ include ../devices/MIMX95/configtool/device.cfg
# Board #
#==========================================================================#
-BOARD DEBUG_UART_INSTANCE=7
+BOARD DEBUG_UART_INSTANCE=2
BOARD DEBUG_UART_BAUDRATE=115200
BOARD I2C_INSTANCE=1
@@ -233,7 +233,7 @@ IOMUXC OWNER
IOMUX_GPR OWNER
JTAG OWNER
LPI2C1 OWNER
-LPUART7 OWNER
+LPUART2 OWNER
M33_CACHE_CTRL OWNER
M33_PCF OWNER
M33_PSF OWNER
@@ -306,8 +306,8 @@ L_STCU_NPUMIX OWNER
PIN_FCCU_ERR0 OWNER
PIN_I2C1_SCL OWNER
PIN_I2C1_SDA OWNER
-PIN_GPIO_IO08 OWNER # LPUART7_TX
-PIN_GPIO_IO09 OWNER # LPUART7_RX
+PIN_UART2_RXD OWNER
+PIN_UART2_TXD OWNER
PIN_WDOG_ANY OWNER
# Memory
@@ -488,11 +488,11 @@ PERLPI_GPIO3 ALL
PERLPI_GPIO4 ALL
PERLPI_GPIO5 ALL
PERLPI_LPUART1 ALL
-PERLPI_LPUART2 ALL
PERLPI_LPUART3 ALL
PERLPI_LPUART4 ALL
PERLPI_LPUART5 ALL
PERLPI_LPUART6 ALL
+PERLPI_LPUART7 ALL
PERLPI_LPUART8 ALL
PERLPI_GPIO1 ALL
PERLPI_WDOG3 ALL
@@ -772,11 +772,11 @@ LPTPM4 OWNER
LPTPM5 OWNER
LPTPM6 OWNER
LPUART1 OWNER
-LPUART2 OWNER
LPUART3 OWNER
LPUART4 OWNER
LPUART5 OWNER
LPUART6 OWNER
+LPUART7 OWNER
LPUART8 OWNER, test
LVDS OWNER
MIPI_CSI0 OWNER
@@ -922,6 +922,8 @@ PIN_GPIO_IO04 OWNER
PIN_GPIO_IO05 OWNER
PIN_GPIO_IO06 OWNER
PIN_GPIO_IO07 OWNER
+PIN_GPIO_IO08 OWNER
+PIN_GPIO_IO09 OWNER
PIN_GPIO_IO10 OWNER
PIN_GPIO_IO11 OWNER
PIN_GPIO_IO12 OWNER
@@ -987,8 +989,6 @@ PIN_SD3_DATA2 OWNER
PIN_SD3_DATA3 OWNER
PIN_UART1_RXD OWNER, test
PIN_UART1_TXD OWNER
-PIN_UART2_RXD OWNER
-PIN_UART2_TXD OWNER
PIN_XSPI1_DATA0 OWNER
PIN_XSPI1_DATA1 OWNER
PIN_XSPI1_DATA2 OWNER
diff --git a/configs/ccimx95dvk/config_board.h b/configs/ccimx95dvk/config_board.h
index 23ecae56cf78..b511a0320a68 100644
--- a/configs/ccimx95dvk/config_board.h
+++ b/configs/ccimx95dvk/config_board.h
@@ -54,7 +54,7 @@
/* Defines */
/*! Config for UART instance */
-#define BOARD_DEBUG_UART_INSTANCE 7U
+#define BOARD_DEBUG_UART_INSTANCE 2U
/*! Config for UART baudrate */
#define BOARD_DEBUG_UART_BAUDRATE 115200U
diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
index 506cb750af65..3b6899a7b9c8 100644
--- a/configs/ccimx95dvk/config_scmi.h
+++ b/configs/ccimx95dvk/config_scmi.h
@@ -177,11 +177,11 @@
.perlpiPerms[DEV_SM_PERLPI_GPIO4] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_GPIO5] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART1] = SM_SCMI_PERM_ALL, \
- .perlpiPerms[DEV_SM_PERLPI_LPUART2] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART3] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART4] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART5] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART6] = SM_SCMI_PERM_ALL, \
+ .perlpiPerms[DEV_SM_PERLPI_LPUART7] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART8] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_WDOG3] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_WDOG4] = SM_SCMI_PERM_ALL, \
@@ -270,11 +270,11 @@
.clkPerms[DEV_SM_CLK_LPSPI7] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPSPI8] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPUART1] = SM_SCMI_PERM_ALL, \
- .clkPerms[DEV_SM_CLK_LPUART2] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPUART3] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPUART4] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPUART5] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPUART6] = SM_SCMI_PERM_ALL, \
+ .clkPerms[DEV_SM_CLK_LPUART7] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_LPUART8] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_MIPIPHYCFG] = SM_SCMI_PERM_ALL, \
.clkPerms[DEV_SM_CLK_MIPIPHYPLLBYPASS] = SM_SCMI_PERM_ALL, \
@@ -388,6 +388,8 @@
.daisyPerms[DEV_SM_DAISY_LPUART6_CTS] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_LPUART6_RXD] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_LPUART6_TXD] = SM_SCMI_PERM_ALL, \
+ .daisyPerms[DEV_SM_DAISY_LPUART7_RXD] = SM_SCMI_PERM_ALL, \
+ .daisyPerms[DEV_SM_DAISY_LPUART7_TXD] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_NETC_EMDC] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_NETC_EMDIO] = SM_SCMI_PERM_ALL, \
.daisyPerms[DEV_SM_DAISY_NETC_ETH0_RMII_RX_ER] = SM_SCMI_PERM_ALL, \
@@ -463,11 +465,11 @@
.perlpiPerms[DEV_SM_PERLPI_GPIO4] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_GPIO5] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART1] = SM_SCMI_PERM_ALL, \
- .perlpiPerms[DEV_SM_PERLPI_LPUART2] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART3] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART4] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART5] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART6] = SM_SCMI_PERM_ALL, \
+ .perlpiPerms[DEV_SM_PERLPI_LPUART7] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_LPUART8] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_WDOG3] = SM_SCMI_PERM_ALL, \
.perlpiPerms[DEV_SM_PERLPI_WDOG4] = SM_SCMI_PERM_ALL, \
@@ -515,6 +517,8 @@
.pinPerms[DEV_SM_PIN_GPIO_IO05] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_GPIO_IO06] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_GPIO_IO07] = SM_SCMI_PERM_ALL, \
+ .pinPerms[DEV_SM_PIN_GPIO_IO08] = SM_SCMI_PERM_ALL, \
+ .pinPerms[DEV_SM_PIN_GPIO_IO09] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_GPIO_IO10] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_GPIO_IO11] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_GPIO_IO12] = SM_SCMI_PERM_ALL, \
@@ -580,8 +584,6 @@
.pinPerms[DEV_SM_PIN_SD3_DATA3] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_UART1_RXD] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_UART1_TXD] = SM_SCMI_PERM_ALL, \
- .pinPerms[DEV_SM_PIN_UART2_RXD] = SM_SCMI_PERM_ALL, \
- .pinPerms[DEV_SM_PIN_UART2_TXD] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_XSPI1_DATA0] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_XSPI1_DATA1] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_XSPI1_DATA2] = SM_SCMI_PERM_ALL, \
diff --git a/configs/ccimx95dvk/config_trdc.h b/configs/ccimx95dvk/config_trdc.h
index 12ebbc61ca64..5758f62bdef5 100644
--- a/configs/ccimx95dvk/config_trdc.h
+++ b/configs/ccimx95dvk/config_trdc.h
@@ -108,7 +108,7 @@
SM_CFG_W1(0x00010450U), 0x30003330U, \
SM_CFG_W1(0x00010454U), 0x03333033U, \
SM_CFG_W1(0x00010458U), 0x00030000U, \
- SM_CFG_W1(0x0001045cU), 0x33330000U, \
+ SM_CFG_W1(0x0001045cU), 0x33330030U, \
SM_CFG_W1(0x00010460U), 0x33333333U, \
SM_CFG_W1(0x00010464U), 0x30000003U, \
SM_CFG_W1(0x00010468U), 0x33330030U, \
@@ -123,7 +123,7 @@
SM_CFG_W1(0x00010650U), 0x09000309U, \
SM_CFG_W1(0x00010654U), 0x0000C900U, \
SM_CFG_W1(0x00010658U), 0x99909900U, \
- SM_CFG_W1(0x0001065cU), 0x00009999U, \
+ SM_CFG_W1(0x0001065cU), 0x00009909U, \
SM_CFG_W1(0x00010668U), 0x00009900U, \
SM_CFG_W1(0x0001066cU), 0x90909000U, \
SM_CFG_W1(0x00010670U), 0x00009000U, \
@@ -1151,7 +1151,6 @@
SM_CFG_Z1(0x00010260U), \
SM_CFG_W1(0x00010270U), 0x00000090U, \
SM_CFG_W1(0x00010460U), 0x33000300U, \
- SM_CFG_W1(0x00010474U), 0x00000030U, \
SM_CFG_W1(0x00010478U), 0x33300000U, \
SM_CFG_W1(0x0001047cU), 0x00003333U, \
SM_CFG_W1(0x000105d0U), 0x33333333U, \
@@ -1170,7 +1169,7 @@
SM_CFG_W1(0x00010668U), 0x99999999U, \
SM_CFG_W1(0x0001066cU), 0x09999999U, \
SM_CFG_W1(0x00010670U), 0x99900009U, \
- SM_CFG_W1(0x00010674U), 0x99999909U, \
+ SM_CFG_W1(0x00010674U), 0x99999999U, \
SM_CFG_W1(0x00010678U), 0x00009999U, \
SM_CFG_W1(0x0001067cU), 0x00990000U, \
SM_CFG_W1(0x00010780U), 0x00000009U, \

68
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0014-ccimx95dvk-PF09-PMIC-interrupt-moved-to-PDM_BIT_STRE.patch
View File

@ -1,68 +0,0 @@
From: Hector Palacios <hector.palacios@digi.com>
Date: Wed, 14 Jan 2026 14:05:57 +0100
Subject: [PATCH] ccimx95dvk: PF09 PMIC interrupt moved to PDM_BIT_STREAM1
Upstream-Status: Inappropriate [DEY specific]
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
https://onedigi.atlassian.net/browse/DEL-9915
---
boards/ccimx95dvk/pin_mux.c | 5 +++++
configs/ccimx95dvk.cfg | 2 +-
configs/ccimx95dvk/config_scmi.h | 1 -
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/boards/ccimx95dvk/pin_mux.c b/boards/ccimx95dvk/pin_mux.c
index 6f5bb4a51c4c..41ad97dd4e75 100755
--- a/boards/ccimx95dvk/pin_mux.c
+++ b/boards/ccimx95dvk/pin_mux.c
@@ -1,5 +1,6 @@
/*
* Copyright 2023, 2025 NXP
+ * Copyright 2025, 2026 Digi International Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -57,5 +58,9 @@ void BOARD_InitPins(void)
IOMUXC_SetPinConfig(IOMUXC_PAD_I2C2_SDA__LPI2C2_SDA, IOMUXC_PAD_DSE(0xFU)
| IOMUXC_PAD_FSEL1(0x3U) | IOMUXC_PAD_PU(0x1U) | IOMUXC_PAD_OD(0x1U));
#endif
+
+ /* Configure GPIO1-10 (INT from PF09) */
+ IOMUXC_SetPinMux(IOMUXC_PAD_PDM_BIT_STREAM1__GPIO1_IO_BIT10, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_PAD_PDM_BIT_STREAM1__GPIO1_IO_BIT10, 0U);
}
diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
index 53444e785270..ba7cc9e0499a 100755
--- a/configs/ccimx95dvk.cfg
+++ b/configs/ccimx95dvk.cfg
@@ -306,6 +306,7 @@ L_STCU_NPUMIX OWNER
PIN_FCCU_ERR0 OWNER
PIN_I2C1_SCL OWNER
PIN_I2C1_SDA OWNER
+PIN_PDM_BIT_STREAM1 OWNER # PF09_INT_B
PIN_UART2_RXD OWNER
PIN_UART2_TXD OWNER
PIN_WDOG_ANY OWNER
@@ -955,7 +956,6 @@ PIN_GPIO_IO37 OWNER
PIN_I2C2_SCL OWNER
PIN_I2C2_SDA OWNER
PIN_PDM_BIT_STREAM0 OWNER
-PIN_PDM_BIT_STREAM1 OWNER
PIN_PDM_CLK OWNER
PIN_SAI1_RXD0 OWNER
PIN_SAI1_TXC OWNER
diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
index 3b6899a7b9c8..20168f81df9d 100644
--- a/configs/ccimx95dvk/config_scmi.h
+++ b/configs/ccimx95dvk/config_scmi.h
@@ -550,7 +550,6 @@
.pinPerms[DEV_SM_PIN_I2C2_SCL] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_I2C2_SDA] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_PDM_BIT_STREAM0] = SM_SCMI_PERM_ALL, \
- .pinPerms[DEV_SM_PIN_PDM_BIT_STREAM1] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_PDM_CLK] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_SAI1_RXD0] = SM_SCMI_PERM_ALL, \
.pinPerms[DEV_SM_PIN_SAI1_TXC] = SM_SCMI_PERM_ALL, \

57
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0015-SM-319-Fix-issue-with-one-chip-select-DRAMs.patch
View File

@ -1,57 +0,0 @@
From: Chuck Cannon <chuck.cannon@nxp.com>
Date: Thu, 30 Oct 2025 10:06:57 -0500
Subject: [PATCH] SM-319: Fix issue with one chip select DRAMs.
Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>
(cherry picked from commit d6f582baa73046f4167549567781a4ea0df4a9ba)
Signed-off-by: Javier Viguera <javier.viguera@digi.com>
Upstream-Status: Inappropriate [DEY specific]
---
drivers/ddr/fsl_ddr.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/ddr/fsl_ddr.c b/drivers/ddr/fsl_ddr.c
index 1042f6a0ba7c..275af15c0ce7 100644
--- a/drivers/ddr/fsl_ddr.c
+++ b/drivers/ddr/fsl_ddr.c
@@ -533,10 +533,10 @@ bool DDR_GetDRAMInfo(const struct ddr_info *ddrp, struct dram_info *info)
info->eccEnb = false;
}
- /* extract MTS from DDR info */
+ /* Extract MTS from DDR info */
info->mts = ddrp->pstate_freq[0];
- /* start address from CS0 bounds (top 12 of 36 bits addr)
+ /* Start address from CS0 bounds (top 12 of 36 bits addr)
+ DDR AXI start */
addr = ((DDRC->CS_BNDS[0].CS_BNDS & DDRC_CS_BNDS_CS_BNDS_SA_MASK)
>> DDRC_CS_BNDS_CS_BNDS_SA_SHIFT);
@@ -544,12 +544,13 @@ bool DDR_GetDRAMInfo(const struct ddr_info *ddrp, struct dram_info *info)
info->startAddr <<= 24U;
info->startAddr += 0x80000000ULL;
- /* end address from CS0 bounds if Rank interleaving set
+ /* End address from CS0 bounds if Rank interleaving set
+ DDR AXI start */
- if ((DDRC->DDR_SDRAM_CFG & DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_MASK)
- != 0U)
+ if (((DDRC->DDR_SDRAM_CFG & DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_MASK)
+ != 0U) || ((DDRC->CS_CONFIG[1] & DDRC_CS_CONFIG_CS_EN_MASK)
+ == 0U))
{
- /* end address from CS0 bounds if Rank interleaving set
+ /* End address from CS0 bounds if Rank interleaving set
+ DDR AXI start */
addr = ((DDRC->CS_BNDS[0].CS_BNDS
& DDRC_CS_BNDS_CS_BNDS_EA_MASK)
@@ -557,7 +558,7 @@ bool DDR_GetDRAMInfo(const struct ddr_info *ddrp, struct dram_info *info)
}
else
{
- /* end address from CS1 bounds + DDR AXI start */
+ /* End address from CS1 bounds + DDR AXI start */
addr = ((DDRC->CS_BNDS[1].CS_BNDS
& DDRC_CS_BNDS_CS_BNDS_EA_MASK)
>> DDRC_CS_BNDS_CS_BNDS_EA_SHIFT);

25
meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager_2025q3.bbappend
View File

@ -1,24 +1,13 @@
# Copyright (C) 2025, 2026, Digi International Inc.
FILESEXTRAPATHS:prepend := "${THISDIR}/${BPN}:"
# Select internal or Github imx-system-manager repo
IMX_SYSTEM_MANAGER_URI_STASH = "${DIGI_MTK_GIT}/emp/imx-sm.git;protocol=ssh"
IMX_SYSTEM_MANAGER_URI_GITHUB = "${DIGI_GITHUB_GIT}/imx-sm.git;protocol=https"
IMX_SYSTEM_MANAGER_SRC:dey = "${@oe.utils.conditional('DIGI_INTERNAL_GIT', '1', '${IMX_SYSTEM_MANAGER_URI_STASH}', '${IMX_SYSTEM_MANAGER_URI_GITHUB}', d)}"
SRC_URI:append:dey = " \
file://0001-ccimx95dvk-add-new-platform-config-and-board.patch \
file://0002-ccimx95dvk-configure-board-and-switch-debug-UART-to-.patch \
file://0003-ccimx95dvk-disable-PCAL6408A-expander-and-move-GPIO1.patch \
file://0004-ccimx95dvk-move-resources-from-M7-to-A55.patch \
file://0005-ccimx95dvk-move-pads-to-non-secure-A55.patch \
file://0006-ccimx95dvk-move-CAN1-to-be-used-by-A55.patch \
file://0007-ccimx95dvk-remove-PCAL6408A-IO-expander-from-EVK.patch \
file://0008-ccimx95dvk-remove-PCA2123-RTC-from-EVK.patch \
file://0009-ccimx95-change-names-of-voltage-regulators.patch \
file://0010-ccimx95dvk-enable-full-access-to-certain-regulators-.patch \
file://0011-components-pf09-reduce-LDOs-step-to-50mV.patch \
file://0012-ccimx95dvk-remove-access-to-VDD_3V3-and-VDD_1V8-from.patch \
file://0013-ccimx95dvk-change-SM-console-from-LPUART7-to-LPUART2.patch \
file://0014-ccimx95dvk-PF09-PMIC-interrupt-moved-to-PDM_BIT_STRE.patch \
file://0015-SM-319-Fix-issue-with-one-chip-select-DRAMs.patch \
"
SRCBRANCH:dey = "dey/scarthgap/lf-6.6.52-2.2.2"
# NXP's 'lf-6.6.52_2.2.2' release + patches
SRCREV:dey = "421dfb2c1d760fb877284b0b2f1ee80b7ce37480"
# Disable debug monitor by default
PACKAGECONFIG ??= "m0"