updat

update ,fix branch name to dey5.0/maint
2026-06-04 00:13:25 -05:00 · 2026-06-04 00:03:41 -05:00 · 2026-06-03 19:20:59 -05:00 · 2026-06-03 04:34:45 -05:00 · 2026-06-02 19:36:00 -05:00 · 2026-06-02 19:22:51 -05:00
41 changed files with 340 additions and 80299 deletions
--- a/meta-digi-arm/conf/machine/ccimx95-dvk.conf
+++ b/meta-digi-arm/conf/machine/ccimx95-dvk.conf
@ -8,8 +8,11 @@ MACHINEOVERRIDES =. "mx95:${DIGI_FAMILY}:${DIGI_SOM}:"
 # Include the machine configuration for Digi's ConnectCore 9 module
 include conf/machine/include/ccimx9.inc

+# SMARC module
+SMARC ?= "1"
+
 # Machine features
-MACHINE_FEATURES += "mca"
+MACHINE_FEATURES += "${@oe.utils.conditional('SMARC', '1', 'mca', '', d)}"

 # Console
 SERIAL_CONSOLES = "115200;ttyLP0"
@ -61,11 +64,8 @@ DDR_FIRMWARE_NAME = " \

 KERNEL_DEVICETREE ?= " \
    digi/ccimx95-dvk.dtb \
-    digi/ccimx95-dvk_enet2.dtbo \
    digi/ccimx95-dvk_lvds0_g101evn010.dtbo \
    digi/ccimx95-dvk_lvds1_g101evn010.dtbo \
-    digi/ccimx95-dvk_mikroe-accel2-click.dtbo \
-    digi/ccimx95-dvk_mikroe-gyro-click.dtbo \
    digi/ccimx95-dvk_pcam5c.dtbo \
    digi/ccimx95_bt.dtbo \
    digi/ccimx95_npu.dtbo \
@ -80,3 +80,13 @@ DEFAULT_IMAGE_NAME ?= "dey-image-chromium"
 BOOTABLE_ARTIFACTS = " \
    imx-boot##SIGNED##-ccimx95-dvk.bin \
 "
+
+# Systemd logind power key event.
+# short press:
+#   SMARC=1: graceful poweroff
+#   SMARC=0: suspend
+# long press:
+#   SMARC=1: ignored by systemd (absorbed by MCA fw for a forceful poweroff)
+#   SMARC=0: graceful poweroff
+LOGIND_HANDLE_POWER_KEY ?= "${@oe.utils.conditional('SMARC', '1', 'poweroff', 'suspend', d)}"
+LOGIND_HANDLE_POWER_KEY_LONGPRESS ?= "${@oe.utils.conditional('SMARC', '1', 'ignore', 'poweroff', d)}"
--- a/meta-digi-arm/conf/machine/include/digi-defaults.inc
+++ b/meta-digi-arm/conf/machine/include/digi-defaults.inc
@ -130,3 +130,7 @@ IMAGE_FSTYPES ?= "${@ \
 		'' , d), \
 	d) \
 }"
+
+# Systemd logind power key event
+LOGIND_HANDLE_POWER_KEY ??= "suspend"
+LOGIND_HANDLE_POWER_KEY_LONGPRESS ??= "poweroff"
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-oei/imx-oei/0001-boards-ccimx95-add-platform-as-a-clone-of-mx95lp5.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-oei/imx-oei/0001-boards-ccimx95-add-platform-as-a-clone-of-mx95lp5.patch
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-oei/imx-oei/0002-ddr-add-DDR-configuration-file-for-ccimx95.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-oei/imx-oei/0002-ddr-add-DDR-configuration-file-for-ccimx95.patch
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-oei/imx-oei/0003-ccimx95-configure-console-on-LPUART6.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-oei/imx-oei/0003-ccimx95-configure-console-on-LPUART6.patch
@ -1,56 +0,0 @@
-From: Isaac Hermida <isaac.hermida@digi.com>
-Date: Mon, 15 Sep 2025 11:38:55 +0200
-Subject: [PATCH] ccimx95: configure console on LPUART6
-
-Upstream-Status: Inappropriate [DEY specific]
-
-Signed-off-by: Javier Viguera <javier.viguera@digi.com>
---
- boards/ccimx95/config_board.h  | 2 +-
- boards/ccimx95/pin_mux.c       | 7 +++++++
- devices/MIMX95/oei/soc_clock.c | 2 ++
- 3 files changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/boards/ccimx95/config_board.h b/boards/ccimx95/config_board.h
-index 3095ebf1d8ce..ec97626a2a28 100644
--- a/boards/ccimx95/config_board.h
-+++ b/boards/ccimx95/config_board.h
-@@ -52,7 +52,7 @@
- /* Defines */
- 
- /*! Config for UART instance */
-#define BOARD_DEBUG_UART_INSTANCE    2U
-+#define BOARD_DEBUG_UART_INSTANCE    6U
- /*! Config for UART baudrate */
- #define BOARD_DEBUG_UART_BAUDRATE    115200U
- 
-diff --git a/boards/ccimx95/pin_mux.c b/boards/ccimx95/pin_mux.c
-index a8c15513b578..3cb33909f740 100644
--- a/boards/ccimx95/pin_mux.c
-+++ b/boards/ccimx95/pin_mux.c
-@@ -29,5 +29,12 @@ void BOARD_InitPins(void)
- 
-     IOMUXC_SetPinMux(IOMUXC_PAD_UART2_TXD__LPUART2_TX, 0);
-     IOMUXC_SetPinConfig(IOMUXC_PAD_UART2_TXD__LPUART2_TX, IOMUXC_PAD_DSE(0xFU));
-+#elif (BOARD_DEBUG_UART_INSTANCE == 6U)
-+    /* Configure LPUART 6 */
-+    IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO05__LPUART6_RX, 0);
-+    IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO05__LPUART6_RX, IOMUXC_PAD_PD(1U));
-+
-+    IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO04__LPUART6_TX, 0);
-+    IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO04__LPUART6_TX, IOMUXC_PAD_DSE(0xFU));
- #endif
- }
-diff --git a/devices/MIMX95/oei/soc_clock.c b/devices/MIMX95/oei/soc_clock.c
-index 17493b08e1b8..c1f5cecfa9b6 100644
--- a/devices/MIMX95/oei/soc_clock.c
-+++ b/devices/MIMX95/oei/soc_clock.c
-@@ -25,6 +25,8 @@ static struct clk_root_cfg clk_root_cfgs[] = {
- 	{ CLOCK_ROOT_LPUART1, CLOCK_SRC_OSC24M, 1}, /* 24MHz */
- #elif (BOARD_DEBUG_UART_INSTANCE == 2)
- 	{ CLOCK_ROOT_LPUART2, CLOCK_SRC_OSC24M, 1}, /* 24MHz */
-+#elif (BOARD_DEBUG_UART_INSTANCE == 6)
-+	{ CLOCK_ROOT_LPUART6, CLOCK_SRC_OSC24M, 1}, /* 24MHz */
- #endif
- #endif
- };
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-oei/imx-oei/0004-ccimx95-add-DDR-configuration-file-for-ccimx95-B0-si.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-oei/imx-oei/0004-ccimx95-add-DDR-configuration-file-for-ccimx95-B0-si.patch
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-oei/imx-oei/0005-ccimx95-configure-console-on-LPUART1.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-oei/imx-oei/0005-ccimx95-configure-console-on-LPUART1.patch
@ -1,37 +0,0 @@
-From: Hector Palacios <hector.palacios@digi.com>
-Date: Wed, 14 Jan 2026 17:11:28 +0100
-Subject: [PATCH] ccimx95: configure console on LPUART1
-
-On version 2 of the SOM, the console has been changed
-to LPUART1.
-
-Upstream-Status: Inappropriate [DEY specific]
-
-Signed-off-by: Hector Palacios <hector.palacios@digi.com>
-
-https://onedigi.atlassian.net/browse/DEL-9915
---
- boards/ccimx95/config_board.h | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/boards/ccimx95/config_board.h b/boards/ccimx95/config_board.h
-index ec97626a2a28..e666575ae6e8 100644
--- a/boards/ccimx95/config_board.h
-+++ b/boards/ccimx95/config_board.h
-@@ -2,6 +2,7 @@
- ** ###################################################################
- **
- ** Copyright 2023-2024 NXP
-+** Copyright 2025-2026 Digi International Inc.
- **
- ** Redistribution and use in source and binary forms, with or without modification,
- ** are permitted provided that the following conditions are met:
-@@ -52,7 +53,7 @@
- /* Defines */
- 
- /*! Config for UART instance */
-#define BOARD_DEBUG_UART_INSTANCE    6U
-+#define BOARD_DEBUG_UART_INSTANCE    1U
- /*! Config for UART baudrate */
- #define BOARD_DEBUG_UART_BAUDRATE    115200U
- 
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-oei/imx-oei_1.0.0.bbappend
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-oei/imx-oei_1.0.0.bbappend
@ -1,15 +1,12 @@
 # Copyright (C) 2025,2026 Digi International Inc.

-FILESEXTRAPATHS:prepend := "${THISDIR}/${BPN}:"
+# Select internal or Github imx-oei repo
+IMX_OEI_URI_STASH = "${DIGI_MTK_GIT}/emp/imx-oei.git;protocol=ssh"
+IMX_OEI_URI_GITHUB = "${DIGI_GITHUB_GIT}/imx-oei.git;protocol=https"
+IMX_OEI_SRC:dey = "${@oe.utils.conditional('DIGI_INTERNAL_GIT', '1', '${IMX_OEI_URI_STASH}', '${IMX_OEI_URI_GITHUB}', d)}"

-SRC_URI:append:dey = " \
-    file://0001-boards-ccimx95-add-platform-as-a-clone-of-mx95lp5.patch \
-    file://0002-ddr-add-DDR-configuration-file-for-ccimx95.patch \
-    file://0003-ccimx95-configure-console-on-LPUART6.patch \
-    file://0004-ccimx95-add-DDR-configuration-file-for-ccimx95-B0-si.patch \
-    file://0005-ccimx95-configure-console-on-LPUART1.patch \
-"
-# NXP's 'lf-6.6.52_2.2.2' release
-SRCREV = "49bfaa93e9d1fe213866bcb9507927a59a9ede5a"
+SRCBRANCH:dey = "dey/scarthgap/lf-6.6.52-2.2.2"
+# NXP's 'lf-6.6.52_2.2.2' release + patches
+SRCREV:dey = "0a1fbc5ce9c4bed08d0add95c911749e56a7d57a"

 OEI_DEBUG:dey = "1"
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0001-ccimx95dvk-add-new-platform-config-and-board.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0001-ccimx95dvk-add-new-platform-config-and-board.patch
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0002-ccimx95dvk-configure-board-and-switch-debug-UART-to-.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0002-ccimx95dvk-configure-board-and-switch-debug-UART-to-.patch
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0003-ccimx95dvk-disable-PCAL6408A-expander-and-move-GPIO1.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0003-ccimx95dvk-disable-PCAL6408A-expander-and-move-GPIO1.patch
@ -1,254 +0,0 @@
-From: Javier Viguera <javier.viguera@digi.com>
-Date: Mon, 15 Sep 2025 12:37:05 +0200
-Subject: [PATCH] ccimx95dvk: disable PCAL6408A expander and move GPIO1 to A55
-
-Our board does not populate that expander, so disable the initialization
-and assign GPIO1 to be used by the A55 cpu.
-
-Upstream-Status: Inappropriate [DEY specific]
-
-Signed-off-by: Javier Viguera <javier.viguera@digi.com>
---
- boards/ccimx95dvk/board.c              |  7 ---
- boards/ccimx95dvk/pin_mux.c            |  4 --
- boards/ccimx95dvk/sm/brd_sm.c          |  9 ---
- boards/ccimx95dvk/sm/brd_sm_handlers.c | 82 --------------------------
- configs/ccimx95dvk.cfg                 |  3 +-
- configs/ccimx95dvk/config_scmi.h       |  2 +
- configs/ccimx95dvk/config_trdc.h       |  2 +-
- 7 files changed, 5 insertions(+), 104 deletions(-)
-
-diff --git a/boards/ccimx95dvk/board.c b/boards/ccimx95dvk/board.c
-index c9b97b2a67d9..fe76d6e1a1a3 100755
--- a/boards/ccimx95dvk/board.c
-+++ b/boards/ccimx95dvk/board.c
-@@ -355,9 +355,6 @@ void BOARD_InitHandlers(void)
-     /* Enable FCCU handler */
-     NVIC_SetPriority(FCCU_INT0_IRQn, IRQ_PRIO_NOPREEMPT_CRITICAL);
-     NVIC_EnableIRQ(FCCU_INT0_IRQn);
-
-    /* Enable GPIO1 handler */
-    NVIC_EnableIRQ(GPIO1_0_IRQn);
- }
- 
- /*--------------------------------------------------------------------------*/
-@@ -539,10 +536,6 @@ void BOARD_SystemSleepPrepare(uint32_t sleepMode, uint32_t sleepFlags)
-         (void) CPU_PerLpiConfigSet(CPU_IDX_M33P, s_uartConfig.perLpiId,
-             CPU_PER_LPI_ON_RUN_WAIT_STOP);
-     }
-
-    /* Configure LPI for GPIO1 */
-    (void) CPU_PerLpiConfigSet(CPU_IDX_M33P, CPU_PER_LPI_IDX_GPIO1,
-        CPU_PER_LPI_ON_RUN_WAIT_STOP);
- }
- 
- /*--------------------------------------------------------------------------*/
-diff --git a/boards/ccimx95dvk/pin_mux.c b/boards/ccimx95dvk/pin_mux.c
-index ff2b9540ea7a..6f5bb4a51c4c 100755
--- a/boards/ccimx95dvk/pin_mux.c
-+++ b/boards/ccimx95dvk/pin_mux.c
-@@ -57,9 +57,5 @@ void BOARD_InitPins(void)
-     IOMUXC_SetPinConfig(IOMUXC_PAD_I2C2_SDA__LPI2C2_SDA, IOMUXC_PAD_DSE(0xFU)
-         | IOMUXC_PAD_FSEL1(0x3U) | IOMUXC_PAD_PU(0x1U) | IOMUXC_PAD_OD(0x1U));
- #endif
-
-    /* Configure GPIO1-10 (INT from the PCAL6408A) */
-    IOMUXC_SetPinMux(IOMUXC_PAD_PDM_BIT_STREAM1__GPIO1_IO_BIT10, 0U);
-    IOMUXC_SetPinConfig(IOMUXC_PAD_PDM_BIT_STREAM1__GPIO1_IO_BIT10, 0U);
- }
- 
-diff --git a/boards/ccimx95dvk/sm/brd_sm.c b/boards/ccimx95dvk/sm/brd_sm.c
-index 36b4b52c6986..ae6c3195f0b2 100755
--- a/boards/ccimx95dvk/sm/brd_sm.c
-+++ b/boards/ccimx95dvk/sm/brd_sm.c
-@@ -458,15 +458,6 @@ void BRD_SM_ShutdownRecordSave(dev_sm_rst_rec_t shutdownRec)
- int32_t BRD_SM_SystemReset(void)
- {
-     int32_t status = SM_ERR_SUCCESS;
-    rgpio_pin_config_t gpioConfig =
-    {
-        kRGPIO_DigitalOutput,
-        0U
-    };
-
-    /* Drive WDOG_ANY to reset PMIC */
-    RGPIO_PinInit(GPIO1, 15U, &gpioConfig);
-    IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__GPIO1_IO_BIT15, 0U);
- 
-     /* Wait for PMIC to react */
-     SystemTimeDelay(1000U);
-diff --git a/boards/ccimx95dvk/sm/brd_sm_handlers.c b/boards/ccimx95dvk/sm/brd_sm_handlers.c
-index a96f6ce0e2f4..19ee28e93134 100755
--- a/boards/ccimx95dvk/sm/brd_sm_handlers.c
-+++ b/boards/ccimx95dvk/sm/brd_sm_handlers.c
-@@ -96,26 +96,6 @@ int32_t BRD_SM_SerialDevicesInit(void)
- {
-     int32_t status = SM_ERR_SUCCESS;
-     LPI2C_Type *const s_i2cBases[] = LPI2C_BASE_PTRS;
-    pcal6408a_config_t pcal6408Config;
-
-    /* Fill in PCAL6408A dev */
-    g_pcal6408aDev.i2cBase = s_i2cBases[BOARD_I2C_INSTANCE];
-    g_pcal6408aDev.devAddr = BOARD_PCAL6408A_DEV_ADDR;
-
-    /* Init the bus expander */
-    PCAL6408A_GetDefaultConfig(&pcal6408Config);
-    pcal6408Config.inputLatch = 0xFFU;
-    if (!PCAL6408A_Init(&g_pcal6408aDev, &pcal6408Config))
-    {
-        status = SM_ERR_HARDWARE_ERROR;
-    }
-    else
-    {
-        if (!PCAL6408A_IntMaskSet(&g_pcal6408aDev, PCAL6408A_INITIAL_MASK))
-        {
-            status = SM_ERR_HARDWARE_ERROR;
-        }
-    }
- 
-     if (status == SM_ERR_SUCCESS)
-     {
-@@ -254,20 +234,6 @@ int32_t BRD_SM_SerialDevicesInit(void)
-         }
-     }
- 
-    if (status == SM_ERR_SUCCESS)
-    {
-        rgpio_pin_config_t gpioConfig =
-        {
-            kRGPIO_DigitalInput,
-            0U
-        };
-
-        /* Init GPIO1-10 */
-        RGPIO_PinInit(GPIO1, 10U, &gpioConfig);
-        RGPIO_SetPinInterruptConfig(GPIO1, 10U, kRGPIO_InterruptOutput0,
-            kRGPIO_InterruptLogicZero);
-    }
-
-     /* Return status */
-     return status;
- }
-@@ -300,54 +266,6 @@ int32_t BRD_SM_BusExpMaskSet(uint8_t val, uint8_t mask)
-     return status;
- }
- 
-/*--------------------------------------------------------------------------*/
-/* GPIO1 handler                                                            */
-/*--------------------------------------------------------------------------*/
-void GPIO1_0_IRQHandler(void)
-{
-    uint32_t flags;
-    uint8_t status, val;
-
-    /* Get GPIO status */
-    flags = RGPIO_GetPinsInterruptFlags(GPIO1, kRGPIO_InterruptOutput0);
-
-    /* Get PCAL6408A status */
-    (void) PCAL6408A_IntStatusGet(&g_pcal6408aDev, &status);
-
-    /* Get value and Clear PCAL6408A interrupts */
-    (void) PCAL6408A_InputGet(&g_pcal6408aDev, &val);
-
-    /* Clear GPIO interrupts */
-    RGPIO_ClearPinsInterruptFlags(GPIO1, kRGPIO_InterruptOutput0, flags);
-
-    /* Handle PF09 interrupt */
-    if ((status & BIT8(PCAL6408A_INPUT_PF09_INT)) != 0U)
-    {
-        /* Asserts low */
-        if ((val & BIT8(PCAL6408A_INPUT_PF09_INT)) == 0U)
-        {
-            BRD_SM_Pf09Handler();
-        }
-    }
-
-    /* Handle PCA2131 interrupt */
-    if (g_pca2131Used && ((status & BIT8(PCAL6408A_INPUT_PCA2131_INT))
-        != 0U))
-    {
-        /* Asserts low */
-        if ((val & BIT8(PCAL6408A_INPUT_PCA2131_INT)) == 0U)
-        {
-            BRD_SM_BbmHandler();
-        }
-    }
-
-    /* Handle controls interrupts */
-    BRD_SM_ControlHandler(status, val);
-
-    /* Adjust dynamic IRQ priority */
-    (void) DEV_SM_IrqPrioUpdate();
-}
-
- /*==========================================================================*/
- 
- /*--------------------------------------------------------------------------*/
-diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
-index 557bba3cecf2..cd6c5c4551c2 100755
--- a/configs/ccimx95dvk.cfg
-+++ b/configs/ccimx95dvk.cfg
-@@ -217,7 +217,6 @@ ELE                 OWNER
- FSB                 READONLY
- GIC                 ACCESS
- GPC                 OWNER
-GPIO1               OWNER
- GPR0                OWNER
- GPR1                OWNER
- GPR2                OWNER
-@@ -503,6 +502,7 @@ PERLPI_LPUART4      ALL
- PERLPI_LPUART5      ALL
- PERLPI_LPUART6      ALL
- PERLPI_LPUART8      ALL
-+PERLPI_GPIO1        ALL
- PERLPI_WDOG3        ALL
- PERLPI_WDOG4        ALL
- SYS                 ALL
-@@ -737,6 +737,7 @@ FLEXIO2             OWNER
- FLEXSPI1            OWNER
- FSB                 READONLY
- GIC                 OWNER
-+GPIO1               OWNER
- GPIO2               OWNER
- GPIO3               OWNER
- GPIO4               OWNER
-diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
-index 7032a0efc948..edb2a17eaca1 100644
--- a/configs/ccimx95dvk/config_scmi.h
-+++ b/configs/ccimx95dvk/config_scmi.h
-@@ -183,6 +183,7 @@
-         .perlpiPerms[DEV_SM_PERLPI_CAN3] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_CAN4] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_CAN5] = SM_SCMI_PERM_ALL, \
-+        .perlpiPerms[DEV_SM_PERLPI_GPIO1] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_GPIO2] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_GPIO3] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_GPIO4] = SM_SCMI_PERM_ALL, \
-@@ -465,6 +466,7 @@
-         .perlpiPerms[DEV_SM_PERLPI_CAN3] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_CAN4] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_CAN5] = SM_SCMI_PERM_ALL, \
-+        .perlpiPerms[DEV_SM_PERLPI_GPIO1] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_GPIO2] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_GPIO3] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_GPIO4] = SM_SCMI_PERM_ALL, \
-diff --git a/configs/ccimx95dvk/config_trdc.h b/configs/ccimx95dvk/config_trdc.h
-index 1d8ed0b6fc95..47df6a7577d5 100644
--- a/configs/ccimx95dvk/config_trdc.h
-+++ b/configs/ccimx95dvk/config_trdc.h
-@@ -116,7 +116,6 @@
-         SM_CFG_W1(0x00010470U), 0x33333333U, \
-         SM_CFG_W1(0x00010474U), 0x00003000U, \
-         SM_CFG_W1(0x00010580U), 0x000003C0U, \
-        SM_CFG_W1(0x000105a8U), 0x00000003U, \
-         SM_CFG_W1(0x00010640U), 0x99999999U, \
-         SM_CFG_W1(0x00010644U), 0x99999999U, \
-         SM_CFG_W1(0x00010648U), 0x99999999U, \
-@@ -129,6 +128,7 @@
-         SM_CFG_W1(0x0001066cU), 0x90909000U, \
-         SM_CFG_W1(0x00010670U), 0x00009000U, \
-         SM_CFG_W1(0x00010780U), 0x099330C0U, \
-+        SM_CFG_W1(0x000107a8U), 0x00000009U, \
-         SM_CFG_Z1(0x00010850U), \
-         SM_CFG_W1(0x00010854U), 0x9000C000U, \
-         SM_CFG_W1(0x00010858U), 0x00000099U, \
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0004-ccimx95dvk-move-resources-from-M7-to-A55.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0004-ccimx95dvk-move-resources-from-M7-to-A55.patch
@ -1,206 +0,0 @@
-From: Javier Viguera <javier.viguera@digi.com>
-Date: Tue, 16 Sep 2025 17:51:14 +0200
-Subject: [PATCH] ccimx95dvk: move resources from M7 to A55
-
-Moved from M7 to A55 domain:
-* LPUART7
-* PIN_GPIO_IO14
-* PIN_GPIO_IO15
-
-Upstream-Status: Inappropriate [DEY specific]
-
-Signed-off-by: Javier Viguera <javier.viguera@digi.com>
---
- configs/ccimx95dvk.cfg           | 11 ++++-------
- configs/ccimx95dvk/config_scmi.h | 15 ++++++++-------
- configs/ccimx95dvk/config_test.h |  7 +------
- configs/ccimx95dvk/config_trdc.h |  3 +--
- 4 files changed, 14 insertions(+), 22 deletions(-)
-
-diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
-index cd6c5c4551c2..49861f4545ae 100755
--- a/configs/ccimx95dvk.cfg
-+++ b/configs/ccimx95dvk.cfg
-@@ -390,7 +390,6 @@ LPIT1               OWNER
- LPTMR1              OWNER
- LPTMR2              OWNER
- LPTPM1              OWNER
-LPUART3             OWNER, test
- MSGINTR1            OWNER
- MSGINTR2            OWNER
- MU5_A               OWNER
-@@ -403,11 +402,6 @@ TSTMR2              OWNER
- V2X_SHE1            OWNER
- WDOG5               OWNER
- 
-# Pins
-
-PIN_GPIO_IO14       OWNER
-PIN_GPIO_IO15       OWNER
-
- # Memory
- 
- M7MIX               DATA, begin=0x020380000, end=0x02047FFFF
-@@ -498,6 +492,7 @@ PERLPI_GPIO4        ALL
- PERLPI_GPIO5        ALL
- PERLPI_LPUART1      ALL
- PERLPI_LPUART2      ALL
-+PERLPI_LPUART3      ALL
- PERLPI_LPUART4      ALL
- PERLPI_LPUART5      ALL
- PERLPI_LPUART6      ALL
-@@ -784,6 +779,7 @@ LPTPM5              OWNER
- LPTPM6              OWNER
- LPUART1             OWNER
- LPUART2             OWNER
-+LPUART3             OWNER
- LPUART4             OWNER
- LPUART5             OWNER
- LPUART6             OWNER
-@@ -936,6 +932,8 @@ PIN_GPIO_IO10        OWNER
- PIN_GPIO_IO11        OWNER
- PIN_GPIO_IO12        OWNER
- PIN_GPIO_IO13        OWNER
-+PIN_GPIO_IO14        OWNER
-+PIN_GPIO_IO15        OWNER
- PIN_GPIO_IO16        OWNER
- PIN_GPIO_IO17        OWNER
- PIN_GPIO_IO18        OWNER
-@@ -1015,4 +1013,3 @@ OCRAM               EXEC, begin=0x0204C0000, size=96K
- GPU                 DATA, begin=0x04D900000, end=0x04DD7FFFF
- DDR                 EXEC, begin=0x088000000, end=0x089FFFFFF
- DDR                 EXEC, begin=0x08E000000, end=0x87FFFFFFF
-
-diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
-index edb2a17eaca1..297806453ee1 100644
--- a/configs/ccimx95dvk/config_scmi.h
-+++ b/configs/ccimx95dvk/config_scmi.h
-@@ -69,7 +69,6 @@
-         .clkPerms[DEV_SM_CLK_CAN1] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPTMR1] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPTMR2] = SM_SCMI_PERM_ALL, \
-        .clkPerms[DEV_SM_CLK_LPUART3] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_M7SYSTICK] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_TSTMR2] = SM_SCMI_PERM_ALL, \
-         .cpuPerms[DEV_SM_CPU_M7P] = SM_SCMI_PERM_ALL, \
-@@ -81,9 +80,6 @@
-         .daisyPerms[DEV_SM_DAISY_LPTMR2_0] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_LPTMR2_1] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_LPTMR2_2] = SM_SCMI_PERM_ALL, \
-        .daisyPerms[DEV_SM_DAISY_LPUART3_CTS] = SM_SCMI_PERM_ALL, \
-        .daisyPerms[DEV_SM_DAISY_LPUART3_RXD] = SM_SCMI_PERM_ALL, \
-        .daisyPerms[DEV_SM_DAISY_LPUART3_TXD] = SM_SCMI_PERM_ALL, \
-         .faultPerms[DEV_SM_FAULT_M7_LOCKUP] = SM_SCMI_PERM_ALL, \
-         .faultPerms[DEV_SM_FAULT_M7_RESET] = SM_SCMI_PERM_ALL, \
-         .faultPerms[DEV_SM_FAULT_SW0] = SM_SCMI_PERM_ALL, \
-@@ -94,10 +90,7 @@
-         .pdPerms[DEV_SM_PD_M7] = SM_SCMI_PERM_ALL, \
-         .perfPerms[DEV_SM_PERF_M7] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_CAN1] = SM_SCMI_PERM_ALL, \
-        .perlpiPerms[DEV_SM_PERLPI_LPUART3] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_WDOG5] = SM_SCMI_PERM_ALL, \
-        .pinPerms[DEV_SM_PIN_GPIO_IO14] = SM_SCMI_PERM_ALL, \
-        .pinPerms[DEV_SM_PIN_GPIO_IO15] = SM_SCMI_PERM_ALL, \
-         .rtcPerms[BRD_SM_RTC_PCA2131] = SM_SCMI_PERM_ALL, \
-         .rtcPerms[DEV_SM_RTC_BBNSM] = SM_SCMI_PERM_PRIV, \
-         .sensorPerms[BRD_SM_SENSOR_TEMP_PF09] = SM_SCMI_PERM_SET, \
-@@ -190,6 +183,7 @@
-         .perlpiPerms[DEV_SM_PERLPI_GPIO5] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART1] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART2] = SM_SCMI_PERM_ALL, \
-+        .perlpiPerms[DEV_SM_PERLPI_LPUART3] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART4] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART5] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART6] = SM_SCMI_PERM_ALL, \
-@@ -281,6 +275,7 @@
-         .clkPerms[DEV_SM_CLK_LPSPI8] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPUART1] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPUART2] = SM_SCMI_PERM_ALL, \
-+        .clkPerms[DEV_SM_CLK_LPUART3] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPUART4] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPUART5] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPUART6] = SM_SCMI_PERM_ALL, \
-@@ -389,6 +384,9 @@
-         .daisyPerms[DEV_SM_DAISY_LPSPI4_SCK] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_LPSPI4_SDI] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_LPSPI4_SDO] = SM_SCMI_PERM_ALL, \
-+        .daisyPerms[DEV_SM_DAISY_LPUART3_CTS] = SM_SCMI_PERM_ALL, \
-+        .daisyPerms[DEV_SM_DAISY_LPUART3_RXD] = SM_SCMI_PERM_ALL, \
-+        .daisyPerms[DEV_SM_DAISY_LPUART3_TXD] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_LPUART4_CTS] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_LPUART4_RXD] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_LPUART4_TXD] = SM_SCMI_PERM_ALL, \
-@@ -473,6 +471,7 @@
-         .perlpiPerms[DEV_SM_PERLPI_GPIO5] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART1] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART2] = SM_SCMI_PERM_ALL, \
-+        .perlpiPerms[DEV_SM_PERLPI_LPUART3] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART4] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART5] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART6] = SM_SCMI_PERM_ALL, \
-@@ -527,6 +526,8 @@
-         .pinPerms[DEV_SM_PIN_GPIO_IO11] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_GPIO_IO12] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_GPIO_IO13] = SM_SCMI_PERM_ALL, \
-+        .pinPerms[DEV_SM_PIN_GPIO_IO14] = SM_SCMI_PERM_ALL, \
-+        .pinPerms[DEV_SM_PIN_GPIO_IO15] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_GPIO_IO16] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_GPIO_IO17] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_GPIO_IO18] = SM_SCMI_PERM_ALL, \
-diff --git a/configs/ccimx95dvk/config_test.h b/configs/ccimx95dvk/config_test.h
-index e667d2d5bf36..eed7c5a3d9b8 100644
--- a/configs/ccimx95dvk/config_test.h
-+++ b/configs/ccimx95dvk/config_test.h
-@@ -143,12 +143,11 @@
- /*--------------------------------------------------------------------------*/
- 
- /*! Config for number of tests */
-#define SM_SCMI_NUM_TEST  42U
-+#define SM_SCMI_NUM_TEST  37U
- 
- /*! Config data array for tests */
- #define SM_SCMI_TEST_CONFIG_DATA \
-     {.testId = TEST_BUTTON, .channel = 5U, .rsrc = DEV_SM_BUTTON_0}, \
-    {.testId = TEST_CLK, .channel = 0U, .rsrc = DEV_SM_CLK_LPUART3}, \
-     {.testId = TEST_CLK, .channel = 5U, .rsrc = DEV_SM_CLK_ENETREF}, \
-     {.testId = TEST_CLK, .channel = 5U, .rsrc = DEV_SM_CLK_ENETTIMER1}, \
-     {.testId = TEST_CLK, .channel = 5U, .rsrc = DEV_SM_CLK_GPU_CGC}, \
-@@ -157,9 +156,6 @@
-     {.testId = TEST_CLK, .channel = 5U, .rsrc = DEV_SM_CLK_SAI1}, \
-     {.testId = TEST_CTRL, .channel = 5U, .rsrc = DEV_SM_CTRL_MQS1_SETTINGS}, \
-     {.testId = TEST_CTRL, .channel = 5U, .rsrc = DEV_SM_CTRL_SAI1_MCLK}, \
-    {.testId = TEST_DAISY, .channel = 0U, .rsrc = DEV_SM_DAISY_LPUART3_CTS}, \
-    {.testId = TEST_DAISY, .channel = 0U, .rsrc = DEV_SM_DAISY_LPUART3_RXD}, \
-    {.testId = TEST_DAISY, .channel = 0U, .rsrc = DEV_SM_DAISY_LPUART3_TXD}, \
-     {.testId = TEST_DAISY, .channel = 5U, .rsrc = DEV_SM_DAISY_NETC_EMDC}, \
-     {.testId = TEST_DAISY, .channel = 5U, .rsrc = DEV_SM_DAISY_NETC_EMDIO}, \
-     {.testId = TEST_DAISY, .channel = 5U, .rsrc = DEV_SM_DAISY_NETC_ETH0_RMII_RX_ER}, \
-@@ -184,7 +180,6 @@
-     {.testId = TEST_PERF, .channel = 5U, .rsrc = DEV_SM_PERF_GPU}, \
-     {.testId = TEST_PERF, .channel = 5U, .rsrc = DEV_SM_PERF_NPU}, \
-     {.testId = TEST_PERF, .channel = 5U, .rsrc = DEV_SM_PERF_VPU}, \
-    {.testId = TEST_PERLPI, .channel = 0U, .rsrc = DEV_SM_PERLPI_LPUART3}, \
-     {.testId = TEST_PERLPI, .channel = 5U, .rsrc = DEV_SM_PERLPI_LPUART8}, \
-     {.testId = TEST_PIN, .channel = 5U, .rsrc = DEV_SM_PIN_UART1_RXD}, \
-     {.testId = TEST_RTC, .channel = 5U, .rsrc = DEV_SM_RTC_BBNSM}, \
-diff --git a/configs/ccimx95dvk/config_trdc.h b/configs/ccimx95dvk/config_trdc.h
-index 47df6a7577d5..dc6245097316 100644
--- a/configs/ccimx95dvk/config_trdc.h
-+++ b/configs/ccimx95dvk/config_trdc.h
-@@ -1168,7 +1168,7 @@
-         SM_CFG_W1(0x0001065cU), 0x99999999U, \
-         SM_CFG_W1(0x00010660U), 0x00909099U, \
-         SM_CFG_W1(0x00010664U), 0x99090990U, \
-        SM_CFG_W1(0x00010668U), 0x09999999U, \
-+        SM_CFG_W1(0x00010668U), 0x99999999U, \
-         SM_CFG_W1(0x0001066cU), 0x09999999U, \
-         SM_CFG_W1(0x00010670U), 0x99900009U, \
-         SM_CFG_W1(0x00010674U), 0x99999909U, \
-@@ -1178,7 +1178,6 @@
-         SM_CFG_W1(0x000107a8U), 0x00000009U, \
-         SM_CFG_W1(0x00010860U), 0x00090000U, \
-         SM_CFG_W1(0x00010864U), 0x00909009U, \
-        SM_CFG_W1(0x00010868U), 0x90000000U, \
-         SM_CFG_W1(0x00010878U), 0x00090000U, \
-         SM_CFG_Z1(0x00010a60U), \
-         SM_CFG_Z1(0x00010c60U), \
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0005-ccimx95dvk-move-pads-to-non-secure-A55.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0005-ccimx95dvk-move-pads-to-non-secure-A55.patch
@ -1,75 +0,0 @@
-From: Hector Palacios <hector.palacios@digi.com>
-Date: Wed, 24 Sep 2025 12:26:07 +0200
-Subject: [PATCH] ccimx95dvk: move pads to non-secure A55
-
-The following pads are multiplexed and used by A55 in Linux:
- PIN_UART2_RXD is used as LPUART1 CTS
- PIN_UART2_TXD is used as LPUART1 RTS
- PIN_PDM_BIT_STREAM1 is used as MIKROBUS_RST
-
-Upstream-Status: Inappropriate [DEY specific]
-
-Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
- configs/ccimx95dvk.cfg           | 5 ++++-
- configs/ccimx95dvk/config_scmi.h | 3 +++
- 2 files changed, 7 insertions(+), 1 deletion(-)
-
-diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
-index 49861f4545ae..78fad32b4513 100755
--- a/configs/ccimx95dvk.cfg
-+++ b/configs/ccimx95dvk.cfg
-@@ -1,6 +1,7 @@
- ## ###################################################################
- ##
- ## Copyright 2023-2025 NXP
-+## Copyright 2025 Digi International Inc.
- ##
- ## Redistribution and use in source and binary forms, with or without modification,
- ## are permitted provided that the following conditions are met:
-@@ -305,7 +306,6 @@ L_STCU_NPUMIX       OWNER
- PIN_FCCU_ERR0         OWNER
- PIN_I2C1_SCL          OWNER
- PIN_I2C1_SDA          OWNER
-PIN_PDM_BIT_STREAM1   OWNER
- PIN_GPIO_IO08         OWNER  # LPUART7_TX
- PIN_GPIO_IO09         OWNER  # LPUART7_RX
- PIN_WDOG_ANY          OWNER
-@@ -959,6 +959,7 @@ PIN_GPIO_IO37        OWNER
- PIN_I2C2_SCL         OWNER
- PIN_I2C2_SDA         OWNER
- PIN_PDM_BIT_STREAM0  OWNER
-+PIN_PDM_BIT_STREAM1  OWNER
- PIN_PDM_CLK          OWNER
- PIN_SAI1_RXD0        OWNER
- PIN_SAI1_TXC         OWNER
-@@ -992,6 +993,8 @@ PIN_SD3_DATA2        OWNER
- PIN_SD3_DATA3        OWNER
- PIN_UART1_RXD        OWNER, test
- PIN_UART1_TXD        OWNER
-+PIN_UART2_RXD        OWNER
-+PIN_UART2_TXD        OWNER
- PIN_XSPI1_DATA0      OWNER
- PIN_XSPI1_DATA1      OWNER
- PIN_XSPI1_DATA2      OWNER
-diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
-index 297806453ee1..3d4b9cad69ad 100644
--- a/configs/ccimx95dvk/config_scmi.h
-+++ b/configs/ccimx95dvk/config_scmi.h
-@@ -553,6 +553,7 @@
-         .pinPerms[DEV_SM_PIN_I2C2_SCL] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_I2C2_SDA] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_PDM_BIT_STREAM0] = SM_SCMI_PERM_ALL, \
-+        .pinPerms[DEV_SM_PIN_PDM_BIT_STREAM1] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_PDM_CLK] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_SAI1_RXD0] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_SAI1_TXC] = SM_SCMI_PERM_ALL, \
-@@ -586,6 +587,8 @@
-         .pinPerms[DEV_SM_PIN_SD3_DATA3] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_UART1_RXD] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_UART1_TXD] = SM_SCMI_PERM_ALL, \
-+        .pinPerms[DEV_SM_PIN_UART2_RXD] = SM_SCMI_PERM_ALL, \
-+        .pinPerms[DEV_SM_PIN_UART2_TXD] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_XSPI1_DATA0] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_XSPI1_DATA1] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_XSPI1_DATA2] = SM_SCMI_PERM_ALL, \
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0006-ccimx95dvk-move-CAN1-to-be-used-by-A55.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0006-ccimx95dvk-move-CAN1-to-be-used-by-A55.patch
@ -1,151 +0,0 @@
-From: Hector Palacios <hector.palacios@digi.com>
-Date: Wed, 24 Sep 2025 13:01:57 +0200
-Subject: [PATCH] ccimx95dvk: move CAN1 to be used by A55
-
-CAN1 is no longer reserved by M7 but instead moved to
-non-secure A55 so that it can be used by Linux.
-
-Upstream-Status: Inappropriate [DEY specific]
-
-Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
- configs/ccimx95dvk.cfg            |  3 ++-
- configs/ccimx95dvk/config_bctrl.h | 14 +++++++-------
- configs/ccimx95dvk/config_scmi.h  |  7 ++++---
- configs/ccimx95dvk/config_trdc.h  |  3 +--
- 4 files changed, 14 insertions(+), 13 deletions(-)
-
-diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
-index 78fad32b4513..c1374d4684a9 100755
--- a/configs/ccimx95dvk.cfg
-+++ b/configs/ccimx95dvk.cfg
-@@ -383,7 +383,6 @@ SYS                       ALL
- # Resources
- 
- M7P                 OWNER  # CPUs must be first
-CAN_FD1             OWNER
- FSB                 READONLY
- IRQSTEER_M7         OWNER
- LPIT1               OWNER
-@@ -482,6 +481,7 @@ CHANNEL             db=1, xport=smt, rpc=scmi, type=p2a_notify
- 
- PERF_A55            ALL
- PERF_DRAM           ALL
-+PERLPI_CAN1         ALL
- PERLPI_CAN2         ALL
- PERLPI_CAN3         ALL
- PERLPI_CAN4         ALL
-@@ -604,6 +604,7 @@ CAMERA5             OWNER
- CAMERA6             OWNER
- CAMERA7             OWNER
- CAMERA8             OWNER
-+CAN_FD1             OWNER
- CAN_FD2             OWNER
- CAN_FD3             OWNER
- CAN_FD4             OWNER
-diff --git a/configs/ccimx95dvk/config_bctrl.h b/configs/ccimx95dvk/config_bctrl.h
-index a757834c32ab..a55abe03ec02 100644
--- a/configs/ccimx95dvk/config_bctrl.h
-+++ b/configs/ccimx95dvk/config_bctrl.h
-@@ -61,13 +61,13 @@
- #define SM_BCTRL_A_CONFIG \
-     { \
-         SM_CFG_W1(0x00000008U), 0x00001804U, \
-        SM_CFG_W1(0x0000000CU), 0x0000E56AU, \
-        SM_CFG_W1(0x00000010U), 0x0000E56AU, \
-        SM_CFG_W1(0x00000014U), 0x0000E56AU, \
-        SM_CFG_W1(0x00000018U), 0x0000E56AU, \
-        SM_CFG_W1(0x0000001CU), 0x0000E56AU, \
-        SM_CFG_W1(0x00000020U), 0x0000E56AU, \
-        SM_CFG_W1(0x00000024U), 0x00000291U, \
-+        SM_CFG_W1(0x0000000CU), 0x0000E56BU, \
-+        SM_CFG_W1(0x00000010U), 0x0000E56BU, \
-+        SM_CFG_W1(0x00000014U), 0x0000E56BU, \
-+        SM_CFG_W1(0x00000018U), 0x0000E56BU, \
-+        SM_CFG_W1(0x0000001CU), 0x0000E56BU, \
-+        SM_CFG_W1(0x00000020U), 0x0000E56BU, \
-+        SM_CFG_W1(0x00000024U), 0x00000290U, \
-         SM_CFG_END \
-     }
- 
-diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
-index 3d4b9cad69ad..45114d0002f4 100644
--- a/configs/ccimx95dvk/config_scmi.h
-+++ b/configs/ccimx95dvk/config_scmi.h
-@@ -66,7 +66,6 @@
-         .secure = 0U, \
-         .seenvId = 1U, \
-         .buttonPerms[DEV_SM_BUTTON_0] = SM_SCMI_PERM_NOTIFY, \
-        .clkPerms[DEV_SM_CLK_CAN1] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPTMR1] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPTMR2] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_M7SYSTICK] = SM_SCMI_PERM_ALL, \
-@@ -76,7 +75,6 @@
-         .ctrlPerms[BRD_SM_CTRL_PCA2131] = SM_SCMI_PERM_ALL, \
-         .ctrlPerms[BRD_SM_CTRL_TEST] = SM_SCMI_PERM_ALL, \
-         .ctrlPerms[BRD_SM_CTRL_TEST_A] = SM_SCMI_PERM_ALL, \
-        .daisyPerms[DEV_SM_DAISY_CAN1_RX] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_LPTMR2_0] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_LPTMR2_1] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_LPTMR2_2] = SM_SCMI_PERM_ALL, \
-@@ -89,7 +87,6 @@
-         .lmmPerms[2] = SM_SCMI_PERM_ALL, \
-         .pdPerms[DEV_SM_PD_M7] = SM_SCMI_PERM_ALL, \
-         .perfPerms[DEV_SM_PERF_M7] = SM_SCMI_PERM_ALL, \
-        .perlpiPerms[DEV_SM_PERLPI_CAN1] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_WDOG5] = SM_SCMI_PERM_ALL, \
-         .rtcPerms[BRD_SM_RTC_PCA2131] = SM_SCMI_PERM_ALL, \
-         .rtcPerms[DEV_SM_RTC_BBNSM] = SM_SCMI_PERM_PRIV, \
-@@ -172,6 +169,7 @@
-         .pdPerms[DEV_SM_PD_A55P] = SM_SCMI_PERM_ALL, \
-         .perfPerms[DEV_SM_PERF_A55] = SM_SCMI_PERM_ALL, \
-         .perfPerms[DEV_SM_PERF_DRAM] = SM_SCMI_PERM_ALL, \
-+        .perlpiPerms[DEV_SM_PERLPI_CAN1] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_CAN2] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_CAN3] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_CAN4] = SM_SCMI_PERM_ALL, \
-@@ -228,6 +226,7 @@
-         .clkPerms[DEV_SM_CLK_AUDIOPLL2] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_AUDIOPLL2_VCO] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_AUDIOXCVR] = SM_SCMI_PERM_ALL, \
-+        .clkPerms[DEV_SM_CLK_CAN1] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_CAN2] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_CAN3] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_CAN4] = SM_SCMI_PERM_ALL, \
-@@ -318,6 +317,7 @@
-         .ctrlPerms[DEV_SM_CTRL_SAI3_MCLK] = SM_SCMI_PERM_ALL, \
-         .ctrlPerms[DEV_SM_CTRL_SAI4_MCLK] = SM_SCMI_PERM_ALL, \
-         .ctrlPerms[DEV_SM_CTRL_SAI5_MCLK] = SM_SCMI_PERM_ALL, \
-+        .daisyPerms[DEV_SM_DAISY_CAN1_RX] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_CAN2_RX] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_CAN3_RX] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_CAN4_RX] = SM_SCMI_PERM_ALL, \
-@@ -460,6 +460,7 @@
-         .perfPerms[DEV_SM_PERF_GPU] = SM_SCMI_PERM_ALL, \
-         .perfPerms[DEV_SM_PERF_NPU] = SM_SCMI_PERM_ALL, \
-         .perfPerms[DEV_SM_PERF_VPU] = SM_SCMI_PERM_ALL, \
-+        .perlpiPerms[DEV_SM_PERLPI_CAN1] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_CAN2] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_CAN3] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_CAN4] = SM_SCMI_PERM_ALL, \
-diff --git a/configs/ccimx95dvk/config_trdc.h b/configs/ccimx95dvk/config_trdc.h
-index dc6245097316..12ebbc61ca64 100644
--- a/configs/ccimx95dvk/config_trdc.h
-+++ b/configs/ccimx95dvk/config_trdc.h
-@@ -123,7 +123,7 @@
-         SM_CFG_W1(0x00010650U), 0x09000309U, \
-         SM_CFG_W1(0x00010654U), 0x0000C900U, \
-         SM_CFG_W1(0x00010658U), 0x99909900U, \
-        SM_CFG_W1(0x0001065cU), 0x00009099U, \
-+        SM_CFG_W1(0x0001065cU), 0x00009999U, \
-         SM_CFG_W1(0x00010668U), 0x00009900U, \
-         SM_CFG_W1(0x0001066cU), 0x90909000U, \
-         SM_CFG_W1(0x00010670U), 0x00009000U, \
-@@ -132,7 +132,6 @@
-         SM_CFG_Z1(0x00010850U), \
-         SM_CFG_W1(0x00010854U), 0x9000C000U, \
-         SM_CFG_W1(0x00010858U), 0x00000099U, \
-        SM_CFG_W1(0x0001085cU), 0x00000900U, \
-         SM_CFG_W1(0x00010870U), 0x00000090U, \
-         SM_CFG_W1(0x00010874U), 0x00000999U, \
-         SM_CFG_W1(0x00010980U), 0x900000C0U, \
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0007-ccimx95dvk-remove-PCAL6408A-IO-expander-from-EVK.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0007-ccimx95dvk-remove-PCAL6408A-IO-expander-from-EVK.patch
@ -1,457 +0,0 @@
-From: Hector Palacios <hector.palacios@digi.com>
-Date: Thu, 25 Sep 2025 11:11:20 +0200
-Subject: [PATCH] ccimx95dvk: remove PCAL6408A IO expander from EVK
-
-NXP used this I2C IO expander on their EVK to process
-wakeup interrupt lines.
-This chip is not available on the DVK.
-
-Upstream-Status: Inappropriate [DEY specific]
-
-Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
- boards/ccimx95dvk/board.c              |  1 +
- boards/ccimx95dvk/sm/Makefile          |  4 +-
- boards/ccimx95dvk/sm/brd_sm_bbm.c      |  5 +-
- boards/ccimx95dvk/sm/brd_sm_control.c  | 96 +-------------------------
- boards/ccimx95dvk/sm/brd_sm_control.h  | 14 ++--
- boards/ccimx95dvk/sm/brd_sm_handlers.c | 36 +---------
- boards/ccimx95dvk/sm/brd_sm_handlers.h | 21 +-----
- configs/ccimx95dvk.cfg                 |  6 --
- configs/ccimx95dvk/config_scmi.h       |  6 --
- 9 files changed, 13 insertions(+), 176 deletions(-)
-
-diff --git a/boards/ccimx95dvk/board.c b/boards/ccimx95dvk/board.c
-index fe76d6e1a1a3..2cc8f826b781 100755
--- a/boards/ccimx95dvk/board.c
-+++ b/boards/ccimx95dvk/board.c
-@@ -1,5 +1,6 @@
- /*
-  * Copyright 2023-2025 NXP
-+ * Copyright 2025 Digi International Inc.
-  *
-  * SPDX-License-Identifier: BSD-3-Clause
-  */
-diff --git a/boards/ccimx95dvk/sm/Makefile b/boards/ccimx95dvk/sm/Makefile
-index d5b576737636..db27ea922733 100755
--- a/boards/ccimx95dvk/sm/Makefile
-+++ b/boards/ccimx95dvk/sm/Makefile
-@@ -1,6 +1,7 @@
- ## ###################################################################
- ##
- ## Copyright 2023 NXP
-+## Copyright 2025 Digi International Inc.
- ##
- ## Redistribution and use in source and binary forms, with or without modification,
- ## are permitted provided that the following conditions are met:
-@@ -40,7 +41,6 @@ INCLUDE +=  \
- 	-I$(BOARDS_DIR)  \
- 	-I$(BOARD_DIR)  \
- 	-I$(BOARD_DIR)/sm \
-	-I$(COMPONENTS_DIR)/pcal6408a  \
- 	-I$(COMPONENTS_DIR)/pf09  \
- 	-I$(COMPONENTS_DIR)/pf53  \
- 	-I$(COMPONENTS_DIR)/pca2131
-@@ -50,7 +50,6 @@ VPATH +=  \
- 	$(BOARDS_DIR)  \
- 	$(BOARD_DIR)  \
- 	$(BOARD_DIR)/sm  \
-	$(COMPONENTS_DIR)/pcal6408a  \
- 	$(COMPONENTS_DIR)/pf09  \
- 	$(COMPONENTS_DIR)/pf53  \
- 	$(COMPONENTS_DIR)/pca2131
-@@ -63,7 +62,6 @@ OBJS += \
- 	$(OUT)/brd_sm_sensor.o  \
- 	$(OUT)/brd_sm_voltage.o  \
- 	$(OUT)/brd_sm_bbm.o  \
-	$(OUT)/fsl_pcal6408a.o  \
- 	$(OUT)/fsl_pf09.o  \
- 	$(OUT)/fsl_pf53.o  \
- 	$(OUT)/fsl_pca2131.o
-diff --git a/boards/ccimx95dvk/sm/brd_sm_bbm.c b/boards/ccimx95dvk/sm/brd_sm_bbm.c
-index 6103583ff69d..2c5cc953b1e2 100755
--- a/boards/ccimx95dvk/sm/brd_sm_bbm.c
-+++ b/boards/ccimx95dvk/sm/brd_sm_bbm.c
-@@ -2,6 +2,7 @@
- ** ###################################################################
- **
- ** Copyright 2025 NXP
-+** Copyright 2025 Digi International Inc.
- **
- ** Redistribution and use in source and binary forms, with or without modification,
- ** are permitted provided that the following conditions are met:
-@@ -432,8 +433,6 @@ int32_t BRD_SM_BbmRtcAlarmSet(uint32_t rtcId, bool enable, uint64_t val)
-                     /* Enable interrupt */
-                     if (PCA2131_IntEnable(&g_pca2131Dev, true))
-                     {
-                        /* Enable bus expander interrupt */
-                        status = BRD_SM_BusExpMaskSet(0U, BIT8(6));
-                     }
-                     else
-                     {
-@@ -457,8 +456,6 @@ int32_t BRD_SM_BbmRtcAlarmSet(uint32_t rtcId, bool enable, uint64_t val)
-             /* Disable interrupt */
-             if (PCA2131_IntEnable(&g_pca2131Dev, false))
-             {
-                /* Disable bus expander interrupt */
-                status = BRD_SM_BusExpMaskSet(BIT8(6), BIT8(6));
-             }
-             else
-             {
-diff --git a/boards/ccimx95dvk/sm/brd_sm_control.c b/boards/ccimx95dvk/sm/brd_sm_control.c
-index fde28d939fca..76de9fad9e86 100755
--- a/boards/ccimx95dvk/sm/brd_sm_control.c
-+++ b/boards/ccimx95dvk/sm/brd_sm_control.c
-@@ -2,6 +2,7 @@
- ** ###################################################################
- **
- **     Copyright 2023-2025 NXP
-+**     Copyright 2025 Digi International Inc.
- **
- **     Redistribution and use in source and binary forms, with or without modification,
- **     are permitted provided that the following conditions are met:
-@@ -44,13 +45,6 @@
- 
- /* Local defines */
- 
-/* PCAL6408A input signals */
-#define PCAL6408A_INPUT_SD3_WAKE     0U
-#define PCAL6408A_INPUT_PCIE1_WAKE   4U
-#define PCAL6408A_INPUT_BT_WAKE      5U
-#define PCAL6408A_INPUT_PCIE2_WAKE   6U
-#define PCAL6408A_INPUT_BUTTON       7U
-
- /* Local types */
- 
- /* Local variables */
-@@ -105,26 +99,7 @@ int32_t BRD_SM_ControlGet(uint32_t ctrlId, uint32_t *numRtn, uint32_t *rtn)
-         }
-         else if (ctrlId < BRD_SM_CTRL_TEST)
-         {
-            uint8_t data;
-
-            /* Read expander data input */
-            if (PCAL6408A_InputGet(&g_pcal6408aDev, &data))
-            {
-                uint32_t shift = ctrlId - DEV_SM_NUM_CTRL;
-
-                /* Adjust bit position */
-                if (shift > 0U)
-                {
-                    shift += 3U;
-                }
-
-                *numRtn = 1U;
-                rtn[0] = (((uint32_t) data) >> shift) & 0x1UL;
-            }
-            else
-            {
-                status = SM_ERR_HARDWARE_ERROR;
-            }
-+            status = SM_ERR_HARDWARE_ERROR;
-         }
-         else
-         {
-@@ -270,41 +245,12 @@ int32_t BRD_SM_ControlFlagsSet(uint32_t ctrlId, uint32_t flags)
-     }
-     else
-     {
-        uint8_t mask;
-        uint32_t val;
-        uint32_t enb = (flags != 0U) ? 0U : 1U;
-
-         switch (ctrlId)
-         {
-            case BRD_SM_CTRL_SD3_WAKE:
-                mask = BIT8(PCAL6408A_INPUT_SD3_WAKE);
-                val = (enb & 0x1U) << PCAL6408A_INPUT_SD3_WAKE;
-                break;
-            case BRD_SM_CTRL_PCIE1_WAKE:
-                mask = BIT8(PCAL6408A_INPUT_PCIE1_WAKE);
-                val = (enb & 0x1U) << PCAL6408A_INPUT_PCIE1_WAKE;
-                break;
-            case BRD_SM_CTRL_BT_WAKE:
-                mask = BIT8(PCAL6408A_INPUT_BT_WAKE);
-                val = (enb & 0x1U) << PCAL6408A_INPUT_BT_WAKE;
-                break;
-            case BRD_SM_CTRL_PCIE2_WAKE:
-                mask = BIT8(PCAL6408A_INPUT_PCIE2_WAKE);
-                val = (enb & 0x1U) << PCAL6408A_INPUT_PCIE2_WAKE;
-                break;
-            case BRD_SM_CTRL_BUTTON:
-                mask = BIT8(PCAL6408A_INPUT_BUTTON);
-                val = (enb & 0x1U) << PCAL6408A_INPUT_BUTTON;
-                break;
-             default:
-                 status = SM_ERR_NOT_FOUND;
-                 break;
-         }
-
-        if (status == SM_ERR_SUCCESS)
-        {
-            status = BRD_SM_BusExpMaskSet((uint8_t) val, mask);
-        }
-     }
- 
-     return status;
-@@ -315,42 +261,6 @@ int32_t BRD_SM_ControlFlagsSet(uint32_t ctrlId, uint32_t flags)
- /*--------------------------------------------------------------------------*/
- void BRD_SM_ControlHandler(uint8_t status, uint8_t val)
- {
-    uint32_t data = (uint32_t) val;
-
-    /* Handle SD3 wake */
-    if ((status & BIT8(PCAL6408A_INPUT_SD3_WAKE)) != 0U)
-    {
-        LMM_MiscControlEvent(BRD_SM_CTRL_SD3_WAKE,
-            ((data >> PCAL6408A_INPUT_SD3_WAKE) & 0x1U) + 1U);
-    }
-
-    /* Handle PCIe1 wake */
-    if ((status & BIT8(PCAL6408A_INPUT_PCIE1_WAKE)) != 0U)
-    {
-        LMM_MiscControlEvent(BRD_SM_CTRL_PCIE1_WAKE,
-            ((data >> PCAL6408A_INPUT_PCIE1_WAKE) & 0x1U) + 1U);
-    }
-
-    /* Handle BT wake */
-    if ((status & BIT8(PCAL6408A_INPUT_BT_WAKE)) != 0U)
-    {
-        LMM_MiscControlEvent(BRD_SM_CTRL_BT_WAKE,
-            ((data >> PCAL6408A_INPUT_BT_WAKE) & 0x1U) + 1U);
-    }
-
-    /* Handle PCIe2 wake */
-    if (((status & BIT8(PCAL6408A_INPUT_PCIE2_WAKE)) != 0U)
-        && !g_pca2131Used)
-    {
-        LMM_MiscControlEvent(BRD_SM_CTRL_PCIE2_WAKE,
-            ((data >> PCAL6408A_INPUT_PCIE2_WAKE) & 0x1U) + 1U);
-    }
-
-    /* Handle button */
-    if ((status & BIT8(PCAL6408A_INPUT_BUTTON)) != 0U)
-    {
-        LMM_MiscControlEvent(BRD_SM_CTRL_BUTTON,
-            ((data >> PCAL6408A_INPUT_BUTTON) & 0x1U) + 1U);
-    }
-+    // Call pertinent LMM_MiscControlEvent()
- }
- 
-diff --git a/boards/ccimx95dvk/sm/brd_sm_control.h b/boards/ccimx95dvk/sm/brd_sm_control.h
-index 30ad8e67eb6f..9c61bce72f8e 100755
--- a/boards/ccimx95dvk/sm/brd_sm_control.h
-+++ b/boards/ccimx95dvk/sm/brd_sm_control.h
-@@ -2,6 +2,7 @@
- ** ###################################################################
- **
- **     Copyright 2023-2025 NXP
-+**     Copyright 2025 Digi International Inc.
- **
- **     Redistribution and use in source and binary forms, with or without modification,
- **     are permitted provided that the following conditions are met:
-@@ -67,7 +68,7 @@
- /** @} */
- 
- /*! Number of board controls */
-#define BRD_SM_NUM_CTRL  8UL
-+#define BRD_SM_NUM_CTRL  3UL
- 
- /*! Total number of controls */
- #define SM_NUM_CTRL  (DEV_SM_NUM_CTRL + BRD_SM_NUM_CTRL)
-@@ -76,14 +77,9 @@
-  * @name BRD_SM control domain indexes
-  */
- /** @{ */
-#define BRD_SM_CTRL_SD3_WAKE    (DEV_SM_NUM_CTRL + 0U)  /*!< PCAL6408A-0 */
-#define BRD_SM_CTRL_PCIE1_WAKE  (DEV_SM_NUM_CTRL + 1U)  /*!< PCAL6408A-4 */
-#define BRD_SM_CTRL_BT_WAKE     (DEV_SM_NUM_CTRL + 2U)  /*!< PCAL6408A-5 */
-#define BRD_SM_CTRL_PCIE2_WAKE  (DEV_SM_NUM_CTRL + 3U)  /*!< PCAL6408A-6 */
-#define BRD_SM_CTRL_BUTTON      (DEV_SM_NUM_CTRL + 4U)  /*!< PCAL6408A-7 */
-#define BRD_SM_CTRL_TEST        (DEV_SM_NUM_CTRL + 5U)  /*!< Test */
-#define BRD_SM_CTRL_PCA2131     (DEV_SM_NUM_CTRL + 6U)  /*!< PCA2131 raw access */
-#define BRD_SM_CTRL_TEST_A      (DEV_SM_NUM_CTRL + 7U)  /*!< Test action */
-+#define BRD_SM_CTRL_TEST        (DEV_SM_NUM_CTRL + 0U)  /*!< Test */
-+#define BRD_SM_CTRL_PCA2131     (DEV_SM_NUM_CTRL + 1U)  /*!< PCA2131 raw access */
-+#define BRD_SM_CTRL_TEST_A      (DEV_SM_NUM_CTRL + 2U)  /*!< Test action */
- /** @} */
- 
- /* Types */
-diff --git a/boards/ccimx95dvk/sm/brd_sm_handlers.c b/boards/ccimx95dvk/sm/brd_sm_handlers.c
-index 19ee28e93134..a42359f15e8b 100755
--- a/boards/ccimx95dvk/sm/brd_sm_handlers.c
-+++ b/boards/ccimx95dvk/sm/brd_sm_handlers.c
-@@ -2,6 +2,7 @@
- ** ###################################################################
- **
- ** Copyright 2023-2025 NXP
-+** Copyright 2025 Digi International Inc.
- **
- ** Redistribution and use in source and binary forms, with or without modification,
- ** are permitted provided that the following conditions are met:
-@@ -48,23 +49,16 @@
- 
- /* I2C device addresses */
- #define BOARD_PF09_DEV_ADDR         0x08U
-#define BOARD_PCAL6408A_DEV_ADDR    0x20U
- #define BOARD_PF5301_DEV_ADDR       0x2AU
- #define BOARD_PF5302_DEV_ADDR       0x29U
- #define BOARD_PCA2131_DEV_ADDR      0x53U
- 
-#define PCAL6408A_INPUT_PF53_ARM_PG  1U
-#define PCAL6408A_INPUT_PF53_SOC_PG  2U
-#define PCAL6408A_INPUT_PF09_INT     3U
-#define PCAL6408A_INPUT_PCA2131_INT  6U
-
- /* Local types */
- 
- /* Local variables */
- 
- /* Global variables */
- 
-PCAL6408A_Type g_pcal6408aDev;
- PF09_Type g_pf09Dev;
- PF53_Type g_pf5301Dev;
- PF53_Type g_pf5302Dev;
-@@ -238,34 +232,6 @@ int32_t BRD_SM_SerialDevicesInit(void)
-     return status;
- }
- 
-/*--------------------------------------------------------------------------*/
-/* Set bus expander interrupt mask                                          */
-/*--------------------------------------------------------------------------*/
-int32_t BRD_SM_BusExpMaskSet(uint8_t val, uint8_t mask)
-{
-    int32_t status = SM_ERR_SUCCESS;
-    static uint8_t cachedMask = PCAL6408A_INITIAL_MASK;
-    uint8_t newMask = (cachedMask & ~mask);
-
-    newMask |= val;
-
-    /* Mask changed? */
-    if (cachedMask != newMask)
-    {
-        if (PCAL6408A_IntMaskSet(&g_pcal6408aDev, newMask))
-        {
-            cachedMask = newMask;
-        }
-        else
-        {
-            status = SM_ERR_HARDWARE_ERROR;
-        }
-    }
-
-    /* Return status */
-    return status;
-}
-
- /*==========================================================================*/
- 
- /*--------------------------------------------------------------------------*/
-diff --git a/boards/ccimx95dvk/sm/brd_sm_handlers.h b/boards/ccimx95dvk/sm/brd_sm_handlers.h
-index e34d52b50f7a..781a443e8444 100755
--- a/boards/ccimx95dvk/sm/brd_sm_handlers.h
-+++ b/boards/ccimx95dvk/sm/brd_sm_handlers.h
-@@ -2,6 +2,7 @@
- ** ###################################################################
- **
- ** Copyright 2023-2024 NXP
-+** Copyright 2025 Digi International Inc.
- **
- ** Redistribution and use in source and binary forms, with or without modification,
- ** are permitted provided that the following conditions are met:
-@@ -52,16 +53,12 @@
- 
- #include "sm.h"
- #include "dev_sm.h"
-#include "fsl_pcal6408a.h"
- #include "fsl_pf09.h"
- #include "fsl_pf53.h"
- #include "fsl_pca2131.h"
- 
- /* Defines */
- 
-/*! Initial PCAL6408A interrupt mask */
-#define PCAL6408A_INITIAL_MASK  0xF7U
-
- /*! Number of board IRQs participating dynamic prioritization */
- #define BOARD_NUM_IRQ_PRIO_IDX                 1U
- 
-@@ -72,9 +69,6 @@
- 
- /* External variables */
- 
-/*! Handle to access PCAL6408A */
-extern PCAL6408A_Type g_pcal6408aDev;
-
- /*! Handle to access PF09 */
- extern PF09_Type g_pf09Dev;
- 
-@@ -105,19 +99,6 @@ extern uint32_t g_pmicFaultFlags;
-  */
- int32_t BRD_SM_SerialDevicesInit(void);
- 
-/*!
- * Enable/disable bus expander interrupts.
- *
- * @param[in]     val      Value to write
- * @param[in]     mask     Mask of bits to modify
- *
- * This function allows a caller to configure the bus expander.
- * interrupts.
- *
- * @return Returns the status (::SM_ERR_SUCCESS = success).
- */
-int32_t BRD_SM_BusExpMaskSet(uint8_t val, uint8_t mask);
-
- /*!
-  * GPIO 1 interrupt 0 handler.
-  */
-diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
-index c1374d4684a9..c3c280d275b0 100755
--- a/configs/ccimx95dvk.cfg
-+++ b/configs/ccimx95dvk.cfg
-@@ -365,7 +365,6 @@ CHANNEL             db=2, xport=smt, check=crc32, rpc=scmi, \
- 
- # API
- 
-BRD_SM_CTRL_BUTTON        NOTIFY
- BRD_SM_CTRL_PCA2131       ALL
- BRD_SM_CTRL_TEST          ALL
- BRD_SM_CTRL_TEST_A        ALL
-@@ -553,11 +552,6 @@ CHANNEL             db=1, xport=smt, rpc=scmi, type=p2a_notify
- 
- AUDIO_PLL1                ALL
- AUDIO_PLL2                ALL
-BRD_SM_CTRL_BT_WAKE       NOTIFY
-BRD_SM_CTRL_BUTTON        NOTIFY
-BRD_SM_CTRL_PCIE1_WAKE    NOTIFY
-BRD_SM_CTRL_PCIE2_WAKE    NOTIFY
-BRD_SM_CTRL_SD3_WAKE      NOTIFY
- BRD_SM_CTRL_TEST_A        ALL
- BRD_SM_RTC_PCA2131        PRIV
- BRD_SM_SENSOR_TEMP_PF09   ALL
-diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
-index 45114d0002f4..83d7bd94bcd1 100644
--- a/configs/ccimx95dvk/config_scmi.h
-+++ b/configs/ccimx95dvk/config_scmi.h
-@@ -71,7 +71,6 @@
-         .clkPerms[DEV_SM_CLK_M7SYSTICK] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_TSTMR2] = SM_SCMI_PERM_ALL, \
-         .cpuPerms[DEV_SM_CPU_M7P] = SM_SCMI_PERM_ALL, \
-        .ctrlPerms[BRD_SM_CTRL_BUTTON] = SM_SCMI_PERM_NOTIFY, \
-         .ctrlPerms[BRD_SM_CTRL_PCA2131] = SM_SCMI_PERM_ALL, \
-         .ctrlPerms[BRD_SM_CTRL_TEST] = SM_SCMI_PERM_ALL, \
-         .ctrlPerms[BRD_SM_CTRL_TEST_A] = SM_SCMI_PERM_ALL, \
-@@ -304,11 +303,6 @@
-         .clkPerms[DEV_SM_CLK_VIDEOPLL1_VCO] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_VPUDSP] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_XSPISLVROOT] = SM_SCMI_PERM_ALL, \
-        .ctrlPerms[BRD_SM_CTRL_BT_WAKE] = SM_SCMI_PERM_NOTIFY, \
-        .ctrlPerms[BRD_SM_CTRL_BUTTON] = SM_SCMI_PERM_NOTIFY, \
-        .ctrlPerms[BRD_SM_CTRL_PCIE1_WAKE] = SM_SCMI_PERM_NOTIFY, \
-        .ctrlPerms[BRD_SM_CTRL_PCIE2_WAKE] = SM_SCMI_PERM_NOTIFY, \
-        .ctrlPerms[BRD_SM_CTRL_SD3_WAKE] = SM_SCMI_PERM_NOTIFY, \
-         .ctrlPerms[BRD_SM_CTRL_TEST_A] = SM_SCMI_PERM_ALL, \
-         .ctrlPerms[DEV_SM_CTRL_ADC_TEST] = SM_SCMI_PERM_ALL, \
-         .ctrlPerms[DEV_SM_CTRL_MQS1_SETTINGS] = SM_SCMI_PERM_ALL, \
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0008-ccimx95dvk-remove-PCA2123-RTC-from-EVK.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0008-ccimx95dvk-remove-PCA2123-RTC-from-EVK.patch
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0009-ccimx95-change-names-of-voltage-regulators.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0009-ccimx95-change-names-of-voltage-regulators.patch
@ -1,276 +0,0 @@
-From: Hector Palacios <hector.palacios@digi.com>
-Date: Mon, 29 Sep 2025 13:02:02 +0200
-Subject: [PATCH] ccimx95: change names of voltage regulators
-
-Change the names of voltage regulators for easier identification.
-Use the PMIC regulator (SW1, SW2, LDO1...) and then the name of the power
-rail used in the SOM.
-
-Upstream-Status: Inappropriate [DEY specific]
-
-Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
- boards/ccimx95dvk/sm/brd_sm_voltage.c | 85 ++++++++++++++-------------
- boards/ccimx95dvk/sm/brd_sm_voltage.h | 15 ++---
- 2 files changed, 51 insertions(+), 49 deletions(-)
-
-diff --git a/boards/ccimx95dvk/sm/brd_sm_voltage.c b/boards/ccimx95dvk/sm/brd_sm_voltage.c
-index b81ffd970294..d7e7c9b3ea27 100755
--- a/boards/ccimx95dvk/sm/brd_sm_voltage.c
-+++ b/boards/ccimx95dvk/sm/brd_sm_voltage.c
-@@ -2,6 +2,7 @@
- ** ###################################################################
- **
- **     Copyright 2023-2025 NXP
-+**     Copyright 2025 Digi International Inc.
- **
- **     Redistribution and use in source and binary forms, with or without modification,
- **     are permitted provided that the following conditions are met:
-@@ -63,13 +64,13 @@ int32_t BRD_SM_VoltageNameGet(uint32_t domainId, string *voltNameAddr,
- 
-     static string const s_name[BRD_SM_NUM_VOLT] =
-     {
-        "vdd_gpio_3p3",
-        "vdd_ana_0p8",
-        "vdd_gpio_1p8",
-        "vddq_ddr",
-        "vdd2_ddr",
-        "sd_card",
-        "nvcc_sd2"
-+        "vdd_3v3",
-+        "vdd_ana_0v8",
-+        "vdd_1v8",
-+        "lpd5_vddq",
-+        "lpd5_vdd2",
-+        "vdd_ldo1",
-+        "vdd_sdio2"
-     };
- 
-     /* Get max string width */
-@@ -117,25 +118,25 @@ int32_t BRD_SM_VoltageDescribe(uint32_t domainId,
-         case DEV_SM_VOLT_ARM:
-             status = DEV_SM_VoltageDescribe(domainId, range);
-             break;
-        case BRD_SM_VOLT_VDD_GPIO_3P3:
-+        case BRD_SM_VOLT_SW1_VDD_3V3:
-             rc = PF09_RegulatorInfoGet(PF09_REG_SW1, &info);
-             break;
-        case BRD_SM_VOLT_VDD_ANA_0P8:
-+        case BRD_SM_VOLT_SW2_VDD_ANA_0V8:
-             rc = PF09_RegulatorInfoGet(PF09_REG_SW2, &info);
-             break;
-        case BRD_SM_VOLT_VDD_GPIO_1P8:
-+        case BRD_SM_VOLT_SW3_VDD_1V8:
-             rc = PF09_RegulatorInfoGet(PF09_REG_SW3, &info);
-             break;
-        case BRD_SM_VOLT_VDDQ_DDR:
-+        case BRD_SM_VOLT_SW4_LPD5_VDDQ:
-             rc = PF09_RegulatorInfoGet(PF09_REG_SW4, &info);
-             break;
-        case BRD_SM_VOLT_VDD2_DDR:
-+        case BRD_SM_VOLT_SW5_LPD5_VDD2:
-             rc = PF09_RegulatorInfoGet(PF09_REG_SW5, &info);
-             break;
-        case BRD_SM_VOLT_SD_CARD:
-+        case BRD_SM_VOLT_LDO1_VDD_LDO1:
-             rc = PF09_RegulatorInfoGet(PF09_REG_LDO1, &info);
-             break;
-        case BRD_SM_VOLT_NVCC_SD2:
-+        case BRD_SM_VOLT_LDO2_VDD_SDIO2:
-             rc = PF09_RegulatorInfoGet(PF09_REG_LDO2, &info);
-             break;
-         default:
-@@ -206,31 +207,31 @@ int32_t BRD_SM_VoltageModeSet(uint32_t domainId, uint8_t voltMode)
-                 s_modeArm = voltMode;
-             }
-             break;
-        case BRD_SM_VOLT_VDD_GPIO_3P3:
-+        case BRD_SM_VOLT_SW1_VDD_3V3:
-             rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
-                 mode);
-             break;
-        case BRD_SM_VOLT_VDD_ANA_0P8:
-+        case BRD_SM_VOLT_SW2_VDD_ANA_0V8:
-             rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
-                 mode);
-             break;
-        case BRD_SM_VOLT_VDD_GPIO_1P8:
-+        case BRD_SM_VOLT_SW3_VDD_1V8:
-             rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
-                 mode);
-             break;
-        case BRD_SM_VOLT_VDDQ_DDR:
-+        case BRD_SM_VOLT_SW4_LPD5_VDDQ:
-             rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
-                 mode);
-             break;
-        case BRD_SM_VOLT_VDD2_DDR:
-+        case BRD_SM_VOLT_SW5_LPD5_VDD2:
-             rc = PF09_SwModeSet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
-                 mode);
-             break;
-        case BRD_SM_VOLT_SD_CARD:
-+        case BRD_SM_VOLT_LDO1_VDD_LDO1:
-             rc = PF09_LdoEnable(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
-                 enable);
-             break;
-        case BRD_SM_VOLT_NVCC_SD2:
-+        case BRD_SM_VOLT_LDO2_VDD_SDIO2:
-             rc = PF09_LdoEnable(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
-                 enable);
-             break;
-@@ -271,36 +272,36 @@ int32_t BRD_SM_VoltageModeGet(uint32_t domainId, uint8_t *voltMode)
-             rc = PF09_GpioCtrlGet(&g_pf09Dev, PF09_GPIO4, PF53_STATE_VRUN,
-                 &enable);
-             break;
-        case BRD_SM_VOLT_VDD_GPIO_3P3:
-+        case BRD_SM_VOLT_SW1_VDD_3V3:
-             rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
-                 &mode);
-             enable = (mode != PF09_SW_MODE_OFF);
-             break;
-        case BRD_SM_VOLT_VDD_ANA_0P8:
-+        case BRD_SM_VOLT_SW2_VDD_ANA_0V8:
-             rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
-                 &mode);
-             enable = (mode != PF09_SW_MODE_OFF);
-             break;
-        case BRD_SM_VOLT_VDD_GPIO_1P8:
-+        case BRD_SM_VOLT_SW3_VDD_1V8:
-             rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
-                 &mode);
-             enable = (mode != PF09_SW_MODE_OFF);
-             break;
-        case BRD_SM_VOLT_VDDQ_DDR:
-+        case BRD_SM_VOLT_SW4_LPD5_VDDQ:
-             rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
-                 &mode);
-             enable = (mode != PF09_SW_MODE_OFF);
-             break;
-        case BRD_SM_VOLT_VDD2_DDR:
-+        case BRD_SM_VOLT_SW5_LPD5_VDD2:
-             rc = PF09_SwModeGet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
-                 &mode);
-             enable = (mode != PF09_SW_MODE_OFF);
-             break;
-        case BRD_SM_VOLT_SD_CARD:
-+        case BRD_SM_VOLT_LDO1_VDD_LDO1:
-             rc = PF09_LdoIsEnabled(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
-                 &enable);
-             break;
-        case BRD_SM_VOLT_NVCC_SD2:
-+        case BRD_SM_VOLT_LDO2_VDD_SDIO2:
-             rc = PF09_LdoIsEnabled(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
-                 &enable);
-             break;
-@@ -359,31 +360,31 @@ int32_t BRD_SM_VoltageLevelSet(uint32_t domainId, int32_t voltageLevel)
-                 s_levelArm = (int32_t) level;
-                 rc = true;
-                 break;
-            case BRD_SM_VOLT_VDD_GPIO_3P3:
-+            case BRD_SM_VOLT_SW1_VDD_3V3:
-                 rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
-                     level);
-                 break;
-            case BRD_SM_VOLT_VDD_ANA_0P8:
-+            case BRD_SM_VOLT_SW2_VDD_ANA_0V8:
-                 rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
-                     level);
-                 break;
-            case BRD_SM_VOLT_VDD_GPIO_1P8:
-+            case BRD_SM_VOLT_SW3_VDD_1V8:
-                 rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
-                     level);
-                 break;
-            case BRD_SM_VOLT_VDDQ_DDR:
-+            case BRD_SM_VOLT_SW4_LPD5_VDDQ:
-                 rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
-                     level);
-                 break;
-            case BRD_SM_VOLT_VDD2_DDR:
-+            case BRD_SM_VOLT_SW5_LPD5_VDD2:
-                 rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
-                     level);
-                 break;
-            case BRD_SM_VOLT_SD_CARD:
-+            case BRD_SM_VOLT_LDO1_VDD_LDO1:
-                 rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
-                     level);
-                 break;
-            case BRD_SM_VOLT_NVCC_SD2:
-+            case BRD_SM_VOLT_LDO2_VDD_SDIO2:
-                 rc = PF09_VoltageSet(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
-                     level);
-                 break;
-@@ -458,31 +459,31 @@ int32_t BRD_SM_VoltageLevelGet(uint32_t domainId, int32_t *voltageLevel)
-                 }
-             }
-             break;
-        case BRD_SM_VOLT_VDD_GPIO_3P3:
-+        case BRD_SM_VOLT_SW1_VDD_3V3:
-             rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW1, PF09_STATE_VRUN,
-                 &level);
-             break;
-        case BRD_SM_VOLT_VDD_ANA_0P8:
-+        case BRD_SM_VOLT_SW2_VDD_ANA_0V8:
-             rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW2, PF09_STATE_VRUN,
-                 &level);
-             break;
-        case BRD_SM_VOLT_VDD_GPIO_1P8:
-+        case BRD_SM_VOLT_SW3_VDD_1V8:
-             rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW3, PF09_STATE_VRUN,
-                 &level);
-             break;
-        case BRD_SM_VOLT_VDDQ_DDR:
-+        case BRD_SM_VOLT_SW4_LPD5_VDDQ:
-             rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW4, PF09_STATE_VRUN,
-                 &level);
-             break;
-        case BRD_SM_VOLT_VDD2_DDR:
-+        case BRD_SM_VOLT_SW5_LPD5_VDD2:
-             rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_SW5, PF09_STATE_VRUN,
-                 &level);
-             break;
-        case BRD_SM_VOLT_SD_CARD:
-+        case BRD_SM_VOLT_LDO1_VDD_LDO1:
-             rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_LDO1, PF09_STATE_VRUN,
-                 &level);
-             break;
-        case BRD_SM_VOLT_NVCC_SD2:
-+        case BRD_SM_VOLT_LDO2_VDD_SDIO2:
-             rc = PF09_VoltageGet(&g_pf09Dev, PF09_REG_LDO2, PF09_STATE_VRUN,
-                 &level);
-             break;
-diff --git a/boards/ccimx95dvk/sm/brd_sm_voltage.h b/boards/ccimx95dvk/sm/brd_sm_voltage.h
-index 6c9e01286e7e..46ddc9d89096 100755
--- a/boards/ccimx95dvk/sm/brd_sm_voltage.h
-+++ b/boards/ccimx95dvk/sm/brd_sm_voltage.h
-@@ -2,6 +2,7 @@
- ** ###################################################################
- **
- **     Copyright 2023-2024 NXP
-+**     Copyright 2025 Digi International Inc.
- **
- **     Redistribution and use in source and binary forms, with or without modification,
- **     are permitted provided that the following conditions are met:
-@@ -76,13 +77,13 @@
-  * @name BRD_SM voltage domains
-  */
- /** @{ */
-#define BRD_SM_VOLT_VDD_GPIO_3P3  (DEV_SM_NUM_VOLT + 0U)  /*!< VDD GPIO 3.3v */
-#define BRD_SM_VOLT_VDD_ANA_0P8   (DEV_SM_NUM_VOLT + 1U)  /*!< VDD ANA 0.8v */
-#define BRD_SM_VOLT_VDD_GPIO_1P8  (DEV_SM_NUM_VOLT + 2U)  /*!< VDD GPIO 1.8v */
-#define BRD_SM_VOLT_VDDQ_DDR      (DEV_SM_NUM_VOLT + 3U)  /*!< DDR VDDQ */
-#define BRD_SM_VOLT_VDD2_DDR      (DEV_SM_NUM_VOLT + 4U)  /*!< DDR VDD2 */
-#define BRD_SM_VOLT_SD_CARD       (DEV_SM_NUM_VOLT + 5U)  /*!< SD1 */
-#define BRD_SM_VOLT_NVCC_SD2      (DEV_SM_NUM_VOLT + 6U)  /*!< SD2 */
-+#define BRD_SM_VOLT_SW1_VDD_3V3     (DEV_SM_NUM_VOLT + 0U)  /*!< VDD 3V3 */
-+#define BRD_SM_VOLT_SW2_VDD_ANA_0V8 (DEV_SM_NUM_VOLT + 1U)  /*!< VDD ANA 0V8 */
-+#define BRD_SM_VOLT_SW3_VDD_1V8     (DEV_SM_NUM_VOLT + 2U)  /*!< VDD 1V8 */
-+#define BRD_SM_VOLT_SW4_LPD5_VDDQ   (DEV_SM_NUM_VOLT + 3U)  /*!< DDR VDDQ */
-+#define BRD_SM_VOLT_SW5_LPD5_VDD2   (DEV_SM_NUM_VOLT + 4U)  /*!< DDR VDD2 */
-+#define BRD_SM_VOLT_LDO1_VDD_LDO1   (DEV_SM_NUM_VOLT + 5U)  /*!< LDO1 */
-+#define BRD_SM_VOLT_LDO2_VDD_SDIO2  (DEV_SM_NUM_VOLT + 6U)  /*!< LDO2 (VDD_SDIO2) */
- /** @} */
- 
- /* Types */
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0010-ccimx95dvk-enable-full-access-to-certain-regulators-.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0010-ccimx95dvk-enable-full-access-to-certain-regulators-.patch
@ -1,49 +0,0 @@
-From: Hector Palacios <hector.palacios@digi.com>
-Date: Thu, 9 Oct 2025 13:16:00 +0200
-Subject: [PATCH] ccimx95dvk: enable full access to certain regulators from
- non-secure LVM
-
-The following PMIC regulators are used by the DVK:
- VDD_3V3 (SW1)
- VDD_1V8 (SW3)
- VDD_LDO1 (LDO1)
- VDD_SDIO2 (LDO2)
-
-Upstream-Status: Inappropriate [DEY specific]
-
-Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
- configs/ccimx95dvk.cfg           | 4 ++++
- configs/ccimx95dvk/config_scmi.h | 4 ++++
- 2 files changed, 8 insertions(+)
-
-diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
-index c160dbce0b85..d7ee4d0115fa 100755
--- a/configs/ccimx95dvk.cfg
-+++ b/configs/ccimx95dvk.cfg
-@@ -554,6 +554,10 @@ BRD_SM_CTRL_TEST_A        ALL
- BRD_SM_SENSOR_TEMP_PF09   ALL
- BRD_SM_SENSOR_TEMP_PF5301 SET
- BRD_SM_SENSOR_TEMP_PF5302 SET
-+BRD_SM_VOLT_SW1_VDD_3V3      ALL
-+BRD_SM_VOLT_SW3_VDD_1V8      ALL
-+BRD_SM_VOLT_LDO1_VDD_LDO1    ALL
-+BRD_SM_VOLT_LDO2_VDD_SDIO2   ALL
- BUTTON                    ALL, test
- CLOCK_DISP1PIX            ALL
- CLOCK_DISP2PIX            ALL
-diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
-index 87de1fd591ca..83084a9d1fbd 100644
--- a/configs/ccimx95dvk/config_scmi.h
-+++ b/configs/ccimx95dvk/config_scmi.h
-@@ -601,6 +601,10 @@
-         .sensorPerms[DEV_SM_SENSOR_TEMP_A55] = SM_SCMI_PERM_ALL, \
-         .sensorPerms[DEV_SM_SENSOR_TEMP_ANA] = SM_SCMI_PERM_SET, \
-         .sysPerms = SM_SCMI_PERM_NOTIFY, \
-+        .voltPerms[BRD_SM_VOLT_LDO1_VDD_LDO1] = SM_SCMI_PERM_ALL, \
-+        .voltPerms[BRD_SM_VOLT_LDO2_VDD_SDIO2] = SM_SCMI_PERM_ALL, \
-+        .voltPerms[BRD_SM_VOLT_SW1_VDD_3V3] = SM_SCMI_PERM_ALL, \
-+        .voltPerms[BRD_SM_VOLT_SW3_VDD_1V8] = SM_SCMI_PERM_ALL, \
-     }
- 
- /*! Config for SCMI channel 5 */
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0011-components-pf09-reduce-LDOs-step-to-50mV.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0011-components-pf09-reduce-LDOs-step-to-50mV.patch
@ -1,39 +0,0 @@
-From: Hector Palacios <hector.palacios@digi.com>
-Date: Mon, 13 Oct 2025 08:49:57 +0200
-Subject: [PATCH] components: pf09: reduce LDOs step to 50mV
-
-The voltage values that can be programmed to the LDOs are not linear.
-For low voltages, the step is 50mV, but for higher voltages it is 100mV.
-Setting the step as 100mV fools the Linux kernel regulator framework
-which does not properly calculate the selector it must call when using
-the SCMI regulator framework, resulting in -EINVAL errors.
-
-Upstream-Status: Inappropriate [DEY specific]
-
-Signed-off-by: Hector Palacios <hector.palacios@digi.com>
---
- components/pf09/fsl_pf09.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/components/pf09/fsl_pf09.c b/components/pf09/fsl_pf09.c
-index fc0638cbdba5..5d842c9a3062 100755
--- a/components/pf09/fsl_pf09.c
-+++ b/components/pf09/fsl_pf09.c
-@@ -528,7 +528,7 @@ bool PF09_RegulatorInfoGet(uint8_t regulator, PF09_RegInfo *regInfo)
-                     /* set min/max/step in microvolts */
-                     regInfo->minV = 750000U;
-                     regInfo->maxV = 3300000U;
-                    regInfo->stepV = 100000U;
-+                    regInfo->stepV = 50000U;
-                 }
-                 break;
-             case PF09_REG_LDO2:
-@@ -537,7 +537,7 @@ bool PF09_RegulatorInfoGet(uint8_t regulator, PF09_RegInfo *regInfo)
-                     /* set min/max/step in microvolts */
-                     regInfo->minV = 650000U;
-                     regInfo->maxV = 3300000U;
-                    regInfo->stepV = 100000U;
-+                    regInfo->stepV = 50000U;
-                 }
-                 break;
-             default:
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0012-ccimx95dvk-remove-access-to-VDD_3V3-and-VDD_1V8-from.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0012-ccimx95dvk-remove-access-to-VDD_3V3-and-VDD_1V8-from.patch
@ -1,60 +0,0 @@
-From: Hector Palacios <hector.palacios@digi.com>
-Date: Wed, 29 Oct 2025 16:54:45 +0100
-Subject: [PATCH] ccimx95dvk: remove access to VDD_3V3 and VDD_1V8 from
- non-secure world
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-There doesn't seem to be a clear registered handler for reboot or shutdown
-path from Linux to SM.
-When a 'reboot' is requested, Linux falls back to run the global
-device_shutdown() path.
-The SM will turn these regulators off in their shutdown path or via a
-global “disable regulators on reboot” policy. The current SM firmware
-doesn't get to know if Linux has marked these regulators as "always-on".
-
-Powering these regulators off removes power to the SOM who is then not
-able to continue the reset (it is not powered).
-
-By removing access to Linux, we fully rely on SM managing these regulators,
-though apparently support is incomplete (for instance they are not powered
-off on the poweroff path from Linux), so this may need to be revisited in
-future BSP upgrades.
-
-Upstream-Status: Inappropriate [DEY specific]
-
-Signed-off-by: Hector Palacios <hector.palacios@digi.com>
-
-https://onedigi.atlassian.net/browse/DEL-9804
---
- configs/ccimx95dvk.cfg           | 2 --
- configs/ccimx95dvk/config_scmi.h | 2 --
- 2 files changed, 4 deletions(-)
-
-diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
-index d7ee4d0115fa..b73401792592 100755
--- a/configs/ccimx95dvk.cfg
-+++ b/configs/ccimx95dvk.cfg
-@@ -554,8 +554,6 @@ BRD_SM_CTRL_TEST_A        ALL
- BRD_SM_SENSOR_TEMP_PF09   ALL
- BRD_SM_SENSOR_TEMP_PF5301 SET
- BRD_SM_SENSOR_TEMP_PF5302 SET
-BRD_SM_VOLT_SW1_VDD_3V3      ALL
-BRD_SM_VOLT_SW3_VDD_1V8      ALL
- BRD_SM_VOLT_LDO1_VDD_LDO1    ALL
- BRD_SM_VOLT_LDO2_VDD_SDIO2   ALL
- BUTTON                    ALL, test
-diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
-index 83084a9d1fbd..506cb750af65 100644
--- a/configs/ccimx95dvk/config_scmi.h
-+++ b/configs/ccimx95dvk/config_scmi.h
-@@ -603,8 +603,6 @@
-         .sysPerms = SM_SCMI_PERM_NOTIFY, \
-         .voltPerms[BRD_SM_VOLT_LDO1_VDD_LDO1] = SM_SCMI_PERM_ALL, \
-         .voltPerms[BRD_SM_VOLT_LDO2_VDD_SDIO2] = SM_SCMI_PERM_ALL, \
-        .voltPerms[BRD_SM_VOLT_SW1_VDD_3V3] = SM_SCMI_PERM_ALL, \
-        .voltPerms[BRD_SM_VOLT_SW3_VDD_1V8] = SM_SCMI_PERM_ALL, \
-     }
- 
- /*! Config for SCMI channel 5 */
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0013-ccimx95dvk-change-SM-console-from-LPUART7-to-LPUART2.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0013-ccimx95dvk-change-SM-console-from-LPUART7-to-LPUART2.patch
@ -1,226 +0,0 @@
-From: Hector Palacios <hector.palacios@digi.com>
-Date: Wed, 14 Jan 2026 16:03:29 +0100
-Subject: [PATCH 13/14] ccimx95dvk: change SM console from LPUART7 to LPUART2
-
-On version 2 of the SOM, the SM console has changed to LPUART2.
-
-Upstream-Status: Inappropriate [DEY specific]
-
-Signed-off-by: Hector Palacios <hector.palacios@digi.com>
-
-https://onedigi.atlassian.net/browse/DEL-9915
---
- configs/ccimx95dvk.cfg            | 18 +++++++++---------
- configs/ccimx95dvk/config_board.h |  2 +-
- configs/ccimx95dvk/config_scmi.h  | 12 +++++++-----
- configs/ccimx95dvk/config_trdc.h  |  7 +++----
- 4 files changed, 20 insertions(+), 19 deletions(-)
-
-diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
-index b73401792592..53444e785270 100755
--- a/configs/ccimx95dvk.cfg
-+++ b/configs/ccimx95dvk.cfg
-@@ -1,7 +1,7 @@
- ## ###################################################################
- ##
- ## Copyright 2023-2025 NXP
-## Copyright 2025 Digi International Inc.
-+## Copyright 2025,2026 Digi International Inc.
- ##
- ## Redistribution and use in source and binary forms, with or without modification,
- ## are permitted provided that the following conditions are met:
-@@ -42,7 +42,7 @@ include ../devices/MIMX95/configtool/device.cfg
- # Board                                                                    #
- #==========================================================================#
- 
-BOARD               DEBUG_UART_INSTANCE=7
-+BOARD               DEBUG_UART_INSTANCE=2
- BOARD               DEBUG_UART_BAUDRATE=115200
- 
- BOARD               I2C_INSTANCE=1
-@@ -233,7 +233,7 @@ IOMUXC              OWNER
- IOMUX_GPR           OWNER
- JTAG                OWNER
- LPI2C1              OWNER
-LPUART7             OWNER
-+LPUART2             OWNER
- M33_CACHE_CTRL      OWNER
- M33_PCF             OWNER
- M33_PSF             OWNER
-@@ -306,8 +306,8 @@ L_STCU_NPUMIX       OWNER
- PIN_FCCU_ERR0         OWNER
- PIN_I2C1_SCL          OWNER
- PIN_I2C1_SDA          OWNER
-PIN_GPIO_IO08         OWNER  # LPUART7_TX
-PIN_GPIO_IO09         OWNER  # LPUART7_RX
-+PIN_UART2_RXD         OWNER
-+PIN_UART2_TXD         OWNER
- PIN_WDOG_ANY          OWNER
- 
- # Memory
-@@ -488,11 +488,11 @@ PERLPI_GPIO3        ALL
- PERLPI_GPIO4        ALL
- PERLPI_GPIO5        ALL
- PERLPI_LPUART1      ALL
-PERLPI_LPUART2      ALL
- PERLPI_LPUART3      ALL
- PERLPI_LPUART4      ALL
- PERLPI_LPUART5      ALL
- PERLPI_LPUART6      ALL
-+PERLPI_LPUART7      ALL
- PERLPI_LPUART8      ALL
- PERLPI_GPIO1        ALL
- PERLPI_WDOG3        ALL
-@@ -772,11 +772,11 @@ LPTPM4              OWNER
- LPTPM5              OWNER
- LPTPM6              OWNER
- LPUART1             OWNER
-LPUART2             OWNER
- LPUART3             OWNER
- LPUART4             OWNER
- LPUART5             OWNER
- LPUART6             OWNER
-+LPUART7             OWNER
- LPUART8             OWNER, test
- LVDS                OWNER
- MIPI_CSI0           OWNER
-@@ -922,6 +922,8 @@ PIN_GPIO_IO04        OWNER
- PIN_GPIO_IO05        OWNER
- PIN_GPIO_IO06        OWNER
- PIN_GPIO_IO07        OWNER
-+PIN_GPIO_IO08        OWNER
-+PIN_GPIO_IO09        OWNER
- PIN_GPIO_IO10        OWNER
- PIN_GPIO_IO11        OWNER
- PIN_GPIO_IO12        OWNER
-@@ -987,8 +989,6 @@ PIN_SD3_DATA2        OWNER
- PIN_SD3_DATA3        OWNER
- PIN_UART1_RXD        OWNER, test
- PIN_UART1_TXD        OWNER
-PIN_UART2_RXD        OWNER
-PIN_UART2_TXD        OWNER
- PIN_XSPI1_DATA0      OWNER
- PIN_XSPI1_DATA1      OWNER
- PIN_XSPI1_DATA2      OWNER
-diff --git a/configs/ccimx95dvk/config_board.h b/configs/ccimx95dvk/config_board.h
-index 23ecae56cf78..b511a0320a68 100644
--- a/configs/ccimx95dvk/config_board.h
-+++ b/configs/ccimx95dvk/config_board.h
-@@ -54,7 +54,7 @@
- /* Defines */
- 
- /*! Config for UART instance */
-#define BOARD_DEBUG_UART_INSTANCE    7U
-+#define BOARD_DEBUG_UART_INSTANCE    2U
- /*! Config for UART baudrate */
- #define BOARD_DEBUG_UART_BAUDRATE    115200U
- 
-diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
-index 506cb750af65..3b6899a7b9c8 100644
--- a/configs/ccimx95dvk/config_scmi.h
-+++ b/configs/ccimx95dvk/config_scmi.h
-@@ -177,11 +177,11 @@
-         .perlpiPerms[DEV_SM_PERLPI_GPIO4] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_GPIO5] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART1] = SM_SCMI_PERM_ALL, \
-        .perlpiPerms[DEV_SM_PERLPI_LPUART2] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART3] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART4] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART5] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART6] = SM_SCMI_PERM_ALL, \
-+        .perlpiPerms[DEV_SM_PERLPI_LPUART7] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART8] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_WDOG3] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_WDOG4] = SM_SCMI_PERM_ALL, \
-@@ -270,11 +270,11 @@
-         .clkPerms[DEV_SM_CLK_LPSPI7] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPSPI8] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPUART1] = SM_SCMI_PERM_ALL, \
-        .clkPerms[DEV_SM_CLK_LPUART2] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPUART3] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPUART4] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPUART5] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPUART6] = SM_SCMI_PERM_ALL, \
-+        .clkPerms[DEV_SM_CLK_LPUART7] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_LPUART8] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_MIPIPHYCFG] = SM_SCMI_PERM_ALL, \
-         .clkPerms[DEV_SM_CLK_MIPIPHYPLLBYPASS] = SM_SCMI_PERM_ALL, \
-@@ -388,6 +388,8 @@
-         .daisyPerms[DEV_SM_DAISY_LPUART6_CTS] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_LPUART6_RXD] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_LPUART6_TXD] = SM_SCMI_PERM_ALL, \
-+        .daisyPerms[DEV_SM_DAISY_LPUART7_RXD] = SM_SCMI_PERM_ALL, \
-+        .daisyPerms[DEV_SM_DAISY_LPUART7_TXD] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_NETC_EMDC] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_NETC_EMDIO] = SM_SCMI_PERM_ALL, \
-         .daisyPerms[DEV_SM_DAISY_NETC_ETH0_RMII_RX_ER] = SM_SCMI_PERM_ALL, \
-@@ -463,11 +465,11 @@
-         .perlpiPerms[DEV_SM_PERLPI_GPIO4] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_GPIO5] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART1] = SM_SCMI_PERM_ALL, \
-        .perlpiPerms[DEV_SM_PERLPI_LPUART2] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART3] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART4] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART5] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART6] = SM_SCMI_PERM_ALL, \
-+        .perlpiPerms[DEV_SM_PERLPI_LPUART7] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_LPUART8] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_WDOG3] = SM_SCMI_PERM_ALL, \
-         .perlpiPerms[DEV_SM_PERLPI_WDOG4] = SM_SCMI_PERM_ALL, \
-@@ -515,6 +517,8 @@
-         .pinPerms[DEV_SM_PIN_GPIO_IO05] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_GPIO_IO06] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_GPIO_IO07] = SM_SCMI_PERM_ALL, \
-+        .pinPerms[DEV_SM_PIN_GPIO_IO08] = SM_SCMI_PERM_ALL, \
-+        .pinPerms[DEV_SM_PIN_GPIO_IO09] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_GPIO_IO10] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_GPIO_IO11] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_GPIO_IO12] = SM_SCMI_PERM_ALL, \
-@@ -580,8 +584,6 @@
-         .pinPerms[DEV_SM_PIN_SD3_DATA3] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_UART1_RXD] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_UART1_TXD] = SM_SCMI_PERM_ALL, \
-        .pinPerms[DEV_SM_PIN_UART2_RXD] = SM_SCMI_PERM_ALL, \
-        .pinPerms[DEV_SM_PIN_UART2_TXD] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_XSPI1_DATA0] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_XSPI1_DATA1] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_XSPI1_DATA2] = SM_SCMI_PERM_ALL, \
-diff --git a/configs/ccimx95dvk/config_trdc.h b/configs/ccimx95dvk/config_trdc.h
-index 12ebbc61ca64..5758f62bdef5 100644
--- a/configs/ccimx95dvk/config_trdc.h
-+++ b/configs/ccimx95dvk/config_trdc.h
-@@ -108,7 +108,7 @@
-         SM_CFG_W1(0x00010450U), 0x30003330U, \
-         SM_CFG_W1(0x00010454U), 0x03333033U, \
-         SM_CFG_W1(0x00010458U), 0x00030000U, \
-        SM_CFG_W1(0x0001045cU), 0x33330000U, \
-+        SM_CFG_W1(0x0001045cU), 0x33330030U, \
-         SM_CFG_W1(0x00010460U), 0x33333333U, \
-         SM_CFG_W1(0x00010464U), 0x30000003U, \
-         SM_CFG_W1(0x00010468U), 0x33330030U, \
-@@ -123,7 +123,7 @@
-         SM_CFG_W1(0x00010650U), 0x09000309U, \
-         SM_CFG_W1(0x00010654U), 0x0000C900U, \
-         SM_CFG_W1(0x00010658U), 0x99909900U, \
-        SM_CFG_W1(0x0001065cU), 0x00009999U, \
-+        SM_CFG_W1(0x0001065cU), 0x00009909U, \
-         SM_CFG_W1(0x00010668U), 0x00009900U, \
-         SM_CFG_W1(0x0001066cU), 0x90909000U, \
-         SM_CFG_W1(0x00010670U), 0x00009000U, \
-@@ -1151,7 +1151,6 @@
-         SM_CFG_Z1(0x00010260U), \
-         SM_CFG_W1(0x00010270U), 0x00000090U, \
-         SM_CFG_W1(0x00010460U), 0x33000300U, \
-        SM_CFG_W1(0x00010474U), 0x00000030U, \
-         SM_CFG_W1(0x00010478U), 0x33300000U, \
-         SM_CFG_W1(0x0001047cU), 0x00003333U, \
-         SM_CFG_W1(0x000105d0U), 0x33333333U, \
-@@ -1170,7 +1169,7 @@
-         SM_CFG_W1(0x00010668U), 0x99999999U, \
-         SM_CFG_W1(0x0001066cU), 0x09999999U, \
-         SM_CFG_W1(0x00010670U), 0x99900009U, \
-        SM_CFG_W1(0x00010674U), 0x99999909U, \
-+        SM_CFG_W1(0x00010674U), 0x99999999U, \
-         SM_CFG_W1(0x00010678U), 0x00009999U, \
-         SM_CFG_W1(0x0001067cU), 0x00990000U, \
-         SM_CFG_W1(0x00010780U), 0x00000009U, \
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0014-ccimx95dvk-PF09-PMIC-interrupt-moved-to-PDM_BIT_STRE.patch
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager/0014-ccimx95dvk-PF09-PMIC-interrupt-moved-to-PDM_BIT_STRE.patch
@ -1,69 +0,0 @@
-From: Hector Palacios <hector.palacios@digi.com>
-Date: Wed, 14 Jan 2026 14:05:57 +0100
-Subject: [PATCH 14/14] ccimx95dvk: PF09 PMIC interrupt moved to
- PDM_BIT_STREAM1
-
-Upstream-Status: Inappropriate [DEY specific]
-
-Signed-off-by: Hector Palacios <hector.palacios@digi.com>
-
-https://onedigi.atlassian.net/browse/DEL-9915
---
- boards/ccimx95dvk/pin_mux.c      | 5 +++++
- configs/ccimx95dvk.cfg           | 2 +-
- configs/ccimx95dvk/config_scmi.h | 1 -
- 3 files changed, 6 insertions(+), 2 deletions(-)
-
-diff --git a/boards/ccimx95dvk/pin_mux.c b/boards/ccimx95dvk/pin_mux.c
-index 6f5bb4a51c4c..41ad97dd4e75 100755
--- a/boards/ccimx95dvk/pin_mux.c
-+++ b/boards/ccimx95dvk/pin_mux.c
-@@ -1,5 +1,6 @@
- /*
-  * Copyright 2023, 2025 NXP
-+ * Copyright 2025, 2026 Digi International Inc.
-  *
-  * SPDX-License-Identifier: BSD-3-Clause
-  */
-@@ -57,5 +58,9 @@ void BOARD_InitPins(void)
-     IOMUXC_SetPinConfig(IOMUXC_PAD_I2C2_SDA__LPI2C2_SDA, IOMUXC_PAD_DSE(0xFU)
-         | IOMUXC_PAD_FSEL1(0x3U) | IOMUXC_PAD_PU(0x1U) | IOMUXC_PAD_OD(0x1U));
- #endif
-+
-+    /* Configure GPIO1-10 (INT from PF09) */
-+    IOMUXC_SetPinMux(IOMUXC_PAD_PDM_BIT_STREAM1__GPIO1_IO_BIT10, 0U);
-+    IOMUXC_SetPinConfig(IOMUXC_PAD_PDM_BIT_STREAM1__GPIO1_IO_BIT10, 0U);
- }
- 
-diff --git a/configs/ccimx95dvk.cfg b/configs/ccimx95dvk.cfg
-index 53444e785270..ba7cc9e0499a 100755
--- a/configs/ccimx95dvk.cfg
-+++ b/configs/ccimx95dvk.cfg
-@@ -306,6 +306,7 @@ L_STCU_NPUMIX       OWNER
- PIN_FCCU_ERR0         OWNER
- PIN_I2C1_SCL          OWNER
- PIN_I2C1_SDA          OWNER
-+PIN_PDM_BIT_STREAM1   OWNER	# PF09_INT_B
- PIN_UART2_RXD         OWNER
- PIN_UART2_TXD         OWNER
- PIN_WDOG_ANY          OWNER
-@@ -955,7 +956,6 @@ PIN_GPIO_IO37        OWNER
- PIN_I2C2_SCL         OWNER
- PIN_I2C2_SDA         OWNER
- PIN_PDM_BIT_STREAM0  OWNER
-PIN_PDM_BIT_STREAM1  OWNER
- PIN_PDM_CLK          OWNER
- PIN_SAI1_RXD0        OWNER
- PIN_SAI1_TXC         OWNER
-diff --git a/configs/ccimx95dvk/config_scmi.h b/configs/ccimx95dvk/config_scmi.h
-index 3b6899a7b9c8..20168f81df9d 100644
--- a/configs/ccimx95dvk/config_scmi.h
-+++ b/configs/ccimx95dvk/config_scmi.h
-@@ -550,7 +550,6 @@
-         .pinPerms[DEV_SM_PIN_I2C2_SCL] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_I2C2_SDA] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_PDM_BIT_STREAM0] = SM_SCMI_PERM_ALL, \
-        .pinPerms[DEV_SM_PIN_PDM_BIT_STREAM1] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_PDM_CLK] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_SAI1_RXD0] = SM_SCMI_PERM_ALL, \
-         .pinPerms[DEV_SM_PIN_SAI1_TXC] = SM_SCMI_PERM_ALL, \
--- a/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager_2025q3.bbappend
+++ b/meta-digi-arm/dynamic-layers/arm-toolchain/recipes-bsp/imx-system-manager/imx-system-manager_2025q3.bbappend
@ -1,23 +1,13 @@
 # Copyright (C) 2025, 2026, Digi International Inc.

-FILESEXTRAPATHS:prepend := "${THISDIR}/${BPN}:"
+# Select internal or Github imx-system-manager repo
+IMX_SYSTEM_MANAGER_URI_STASH = "${DIGI_MTK_GIT}/emp/imx-sm.git;protocol=ssh"
+IMX_SYSTEM_MANAGER_URI_GITHUB = "${DIGI_GITHUB_GIT}/imx-sm.git;protocol=https"
+IMX_SYSTEM_MANAGER_SRC:dey = "${@oe.utils.conditional('DIGI_INTERNAL_GIT', '1', '${IMX_SYSTEM_MANAGER_URI_STASH}', '${IMX_SYSTEM_MANAGER_URI_GITHUB}', d)}"

-SRC_URI:append:dey = " \
-    file://0001-ccimx95dvk-add-new-platform-config-and-board.patch \
-    file://0002-ccimx95dvk-configure-board-and-switch-debug-UART-to-.patch \
-    file://0003-ccimx95dvk-disable-PCAL6408A-expander-and-move-GPIO1.patch \
-    file://0004-ccimx95dvk-move-resources-from-M7-to-A55.patch \
-    file://0005-ccimx95dvk-move-pads-to-non-secure-A55.patch \
-    file://0006-ccimx95dvk-move-CAN1-to-be-used-by-A55.patch \
-    file://0007-ccimx95dvk-remove-PCAL6408A-IO-expander-from-EVK.patch \
-    file://0008-ccimx95dvk-remove-PCA2123-RTC-from-EVK.patch \
-    file://0009-ccimx95-change-names-of-voltage-regulators.patch \
-    file://0010-ccimx95dvk-enable-full-access-to-certain-regulators-.patch \
-    file://0011-components-pf09-reduce-LDOs-step-to-50mV.patch \
-    file://0012-ccimx95dvk-remove-access-to-VDD_3V3-and-VDD_1V8-from.patch \
-    file://0013-ccimx95dvk-change-SM-console-from-LPUART7-to-LPUART2.patch \
-    file://0014-ccimx95dvk-PF09-PMIC-interrupt-moved-to-PDM_BIT_STRE.patch \
-"
+SRCBRANCH:dey = "dey/scarthgap/lf-6.6.52-2.2.2"
+# NXP's 'lf-6.6.52_2.2.2' release + patches
+SRCREV:dey = "421dfb2c1d760fb877284b0b2f1ee80b7ce37480"

 # Disable debug monitor by default
 PACKAGECONFIG ??= "m0"
--- a/meta-digi-arm/dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp_2.10.bbappend
+++ b/meta-digi-arm/dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp_2.10.bbappend
@ -10,11 +10,11 @@ TFA_URI_STASH = "${DIGI_MTK_GIT}/emp/arm-trusted-firmware.git;protocol=ssh"
 TFA_URI_GITHUB = "${DIGI_GITHUB_GIT}/arm-trusted-firmware.git;protocol=https"
 TFA_GIT_URI ?= "${@oe.utils.conditional('DIGI_INTERNAL_GIT', '1' , '${TFA_URI_STASH}', '${TFA_URI_GITHUB}', d)}"

-SRCBRANCH = "v2.10/stm32mp/master"
-SRCREV = "${AUTOREV}"
+SRCBRANCH = "v2.10/stm32mp/maint"
+SRCREV = "20bd9eb9805aa1b0545844dba517038e2ac651d6"

 SRC_URI = " \
-    ${TFA_GIT_URI};branch=${SRCBRANCH} \
+    ${TFA_GIT_URI};nobranch=1 \
 "

 # stm32mp15 = header-version 1
--- a/meta-digi-arm/dynamic-layers/stm-st-stm32mp/recipes-security/optee/optee-os-stm32mp_4.0.0.bbappend
+++ b/meta-digi-arm/dynamic-layers/stm-st-stm32mp/recipes-security/optee/optee-os-stm32mp_4.0.0.bbappend
@ -12,7 +12,7 @@ OPTEE_URI_STASH = "${DIGI_MTK_GIT}/emp/optee_os.git;protocol=ssh"
 OPTEE_URI_GITHUB = "${DIGI_GITHUB_GIT}/optee_os.git;protocol=https"
 OPTEE_GIT_URI ?= "${@oe.utils.conditional('DIGI_INTERNAL_GIT', '1' , '${OPTEE_URI_STASH}', '${OPTEE_URI_GITHUB}', d)}"

-SRCBRANCH = "4.0.0/stm/master"
+SRCBRANCH = "4.0.0/stm/maint"
 SRCREV = "${AUTOREV}"

 SRC_URI = " \
--- a/meta-digi-arm/recipes-bsp/u-boot/u-boot-dey_2023.10.bb
+++ b/meta-digi-arm/recipes-bsp/u-boot/u-boot-dey_2023.10.bb
@ -6,7 +6,7 @@ LIC_FILES_CHKSUM = "file://Licenses/README;md5=2ca5f2c35c8cc335f0a19756634782f1"
 DEPENDS += "flex-native bison-native"
 DEPENDS += "python3-setuptools-native"

-SRCBRANCH = "v2023.10/master"
+SRCBRANCH = "v2023.10/maint"
 SRCREV = "${AUTOREV}"

 SRC_URI += " \
--- a/meta-digi-arm/recipes-digi/trustfence/trustfence-sign-tools.inc
+++ b/meta-digi-arm/recipes-digi/trustfence/trustfence-sign-tools.inc
@ -4,7 +4,7 @@ SUMMARY = "TrustFence signing and encryption scripts"
 LICENSE = "GPL-2.0-only"
 LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/GPL-2.0-only;md5=801f80980d171dd6425610833a22dbe6"

-SRCBRANCH = "v2024.04/master"
+SRCBRANCH = "v2024.04/maint"
 SRCREV = "${AUTOREV}"

 S = "${WORKDIR}"
--- a/meta-digi-arm/recipes-kernel/linux/linux-dey_6.6.bb
+++ b/meta-digi-arm/recipes-kernel/linux/linux-dey_6.6.bb
@ -3,7 +3,8 @@
 require recipes-kernel/linux/linux-dey.inc

 SRCBRANCH = "v6.6.52/nxp/master"
-SRCBRANCH:stm32mpcommon = "v6.6.78/stm/master"
+#SRCBRANCH:stm32mpcommon = "v6.6.78/stm/master"
+SRCBRANCH:stm32mpcommon = "v6.6/stm/dey-5.0/maint"
 SRCREV = "${AUTOREV}"
 SRCREV:stm32mpcommon = "${AUTOREV}"

--- a/meta-digi-dey/dynamic-layers/freescale-layer/recipes-multimedia/libcamera/neo-ipa-uguzzi_0.2.5.bb
+++ b/meta-digi-dey/dynamic-layers/freescale-layer/recipes-multimedia/libcamera/neo-ipa-uguzzi_0.2.5.bb
@ -0,0 +1,36 @@
+SUMMARY = "uGuzzi IPA for the libcamera NXP NEO pipeline"
+DESCRIPTION = "\
+An Image Processing Algorithm library for libcamera, for i.MX95 ISP, \
+based on proprietary MM Solutions EAD uGuzzi 3A library"
+SECTION = "libs"
+LICENSE = "Apache-2.0 & BSD-2-Clause & GPL-2.0-or-later & LGPL-2.1-or-later & MIT & Proprietary"
+# Put EULA on separate line for automated recipe updates
+LIC_FILES_CHKSUM = "file://LICENSES/LA_OPT_NXP_Software_License.txt;md5=bc649096ad3928ec06a8713b8d787eac"
+LIC_FILES_CHKSUM += " \
+    file://COPYING;md5=6462e06298403caf09a22e67a7cc551a \
+    file://LICENSES/Apache-2.0.txt;md5=3b83ef96387f14655fc854ddc3c6bd57 \
+    file://LICENSES/BSD-2-Clause.txt;md5=63d6ee386b8aaba70b1bf15a79ca50f2 \
+    file://LICENSES/GPL-2.0-or-later.txt;md5=fed54355545ffd980b814dab4a3b312c \
+    file://LICENSES/LGPL-2.1-or-later.txt;md5=3c328714bf889b2c3c7cd842e3e4893b \
+    file://LICENSES/MIT.txt;md5=38aa75cf4c4c87f018227d5ec9638d75 "
+DEPENDS = "libcamera"
+
+SRC_URI = "${NEO_IPA_UGUZZI_SRC};branch=${SRCBRANCH}"
+NEO_IPA_UGUZZI_SRC ?= "git://github.com/nxp-imx/neo-ipa-uguzzi;protocol=https"
+SRCBRANCH = "lf-6.12.49_2.2.0"
+SRCREV = "c99e172e3f7f49f62625972b25a038e547e24096"
+
+S = "${WORKDIR}/git"
+
+inherit meson pkgconfig
+
+FILES:${PN} += "${libdir}/libcamera ${datadir}/libcamera"
+
+# Libraries are unversioned
+SOLIBS = ".so"
+FILES_SOLIBSDEV = ""
+
+# Pre-built binaries are already stripped, so skip the QA test
+INSANE_SKIP:${PN} = "already-stripped"
+
+COMPATIBLE_MACHINE = "(mx95-generic-bsp)"
--- a/meta-digi-dey/dynamic-layers/freescale-layer/recipes-multimedia/packagegroups/packagegroup-dey-gstreamer.bb
+++ b/meta-digi-dey/dynamic-layers/freescale-layer/recipes-multimedia/packagegroups/packagegroup-dey-gstreamer.bb
@ -1,5 +1,5 @@
 #
-# Copyright (C) 2012-2024, Digi International Inc.
+# Copyright (C) 2012-2026, Digi International Inc.
 #
 SUMMARY = "Gstreamer framework packagegroup for DEY image"

@ -38,7 +38,7 @@ MACHINE_GSTREAMER_1_0_EXTRA_INSTALL ?= " \
    gstreamer1.0-libav \
 "
 MACHINE_GSTREAMER_1_0_EXTRA_INSTALL:ccimx6ul ?= ""
-MACHINE_GSTREAMER_1_0_EXTRA_INSTALL:append:ccimx95 = " libcamera-gst"
+MACHINE_GSTREAMER_1_0_EXTRA_INSTALL:append:ccimx95 = " libcamera-gst neo-ipa-uguzzi"

 RDEPENDS:${PN} = " \
    ${MACHINE_GSTREAMER_1_0_PKGS} \
--- a/meta-digi-dey/recipes-connectivity/glinswup/files/pls3_fw_update.sh
+++ b/meta-digi-dey/recipes-connectivity/glinswup/files/pls3_fw_update.sh
@ -0,0 +1,164 @@
+#!/bin/sh
+#===============================================================================
+#
+#  Copyright (C) 2026 by Digi International Inc.
+#  All rights reserved.
+#
+#  This program is free software; you can redistribute it and/or modify it
+#  under the terms of the GNU General Public License version 2 as published by
+#  the Free Software Foundation.
+#
+#
+#  Description:
+#    Update firmware on a Cinterion PLSx3 modem using glinswup_PLSx3.
+#
+#
+#  Usage:
+#    pls3_fw_update.sh -f <firmware.usf> -p <port> [-n] [-v]
+#
+#===============================================================================
+
+set -eu
+
+UPDATE_BIN="glinswup_PLSx3"
+MM_SERVICE_SYSTEMD=${MM_SERVICE_SYSTEMD:-ModemManager}
+
+# On sysvinit-based platforms, NetworkManager respawns ModemManager automatically.
+# Therefore we must stop NetworkManager to ensure ModemManager remains stopped
+# during the firmware update process.
+NM_SERVICE_VINIT=${NM_SERVICE_VINIT:-networkmanager}
+
+FW_FILE=""
+PORT=""
+VERBOSE=0
+RECOVERY=0
+
+exit_error()
+{
+	ERROR_MESSAGE="$1"
+	ERROR_CODE="${2:-1}"
+
+	echo "## ERROR: ${ERROR_MESSAGE}" >&2
+	exit "${ERROR_CODE}"
+}
+
+log_info()
+{
+	echo "## INFO: $*"
+}
+
+stop_services()
+{
+	if command -v systemctl >/dev/null 2>&1; then
+		log_info "Stopping ${MM_SERVICE_SYSTEMD}..."
+		systemctl stop "${MM_SERVICE_SYSTEMD}" >/dev/null 2>&1 || true
+		return 0
+	fi
+
+	if [ -x "/etc/init.d/${NM_SERVICE_VINIT}" ]; then
+		log_info "Stopping ${NM_SERVICE_VINIT}..."
+		"/etc/init.d/${NM_SERVICE_VINIT}" stop >/dev/null 2>&1 || true
+		return 0
+	fi
+
+	log_info "No service manager found; skipping stop/start"
+	return 0
+}
+
+start_services()
+{
+	if command -v systemctl >/dev/null 2>&1; then
+		systemctl start "${MM_SERVICE_SYSTEMD}" >/dev/null 2>&1 || true
+		return 0
+	fi
+
+	if [ -x "/etc/init.d/${NM_SERVICE_VINIT}" ]; then
+		"/etc/init.d/${NM_SERVICE_VINIT}" start >/dev/null 2>&1 || true
+		return 0
+	fi
+
+	return 0
+}
+
+usage()
+{
+	cat <<'EOF'
+Usage:
+  pls3_fw_update.sh -f <firmware.usf> -p <port> [-n] [-v]
+
+Options:
+  -f, --firmware   Path to firmware file (.usf)
+  -p, --port       Serial port used by the updater tool (e.g. /dev/ttyACM0)
+  -n               Recovery mode (pass -n to updater)
+  -v               Verbose (pass -v to updater and show output)
+
+Environment:
+  MM_SERVICE_SYSTEMD=ModemManager
+  NM_SERVICE_VINIT=networkmanager
+EOF
+}
+
+parse_args()
+{
+	while [ $# -gt 0 ]; do
+		case "$1" in
+			-f|--firmware)
+				[ $# -ge 2 ] || exit_error "Missing value for $1" 2
+				FW_FILE="${2:-}"; shift 2;;
+			-p|--port)
+				[ $# -ge 2 ] || exit_error "Missing value for $1" 2
+				PORT="${2:-}"; shift 2;;
+			-n)
+				RECOVERY=1; shift;;
+			-v)
+				VERBOSE=1; shift;;
+			-h|--help)
+				usage; exit 0;;
+			*)
+				exit_error "Unknown argument: $1" 2;;
+		esac
+	done
+}
+
+require_prereqs()
+{
+	[ -n "${FW_FILE}" ] || exit_error "Missing -f/--firmware" 2
+	[ -n "${PORT}" ] || exit_error "Missing -p/--port" 2
+
+	[ -r "${FW_FILE}" ] || exit_error "Firmware file not readable: ${FW_FILE}" 2
+	command -v "${UPDATE_BIN}" >/dev/null 2>&1 || exit_error "Update tool not found in PATH: ${UPDATE_BIN}" 2
+	[ -e "${PORT}" ] || exit_error "Port does not exist: ${PORT}" 2
+}
+
+run_update()
+{
+	RC=0
+	VERBOSE_ARG=""
+	RECOVERY_ARG=""
+
+	[ "${VERBOSE}" -eq 1 ] && VERBOSE_ARG="-v"
+	[ "${RECOVERY}" -eq 1 ] && RECOVERY_ARG="-n"
+
+	log_info "Running: ${UPDATE_BIN} -f '${FW_FILE}' -p '${PORT}' -u 1 ${RECOVERY_ARG} ${VERBOSE_ARG}"
+
+	if [ "${VERBOSE}" -eq 1 ]; then
+		"${UPDATE_BIN}" -f "${FW_FILE}" -p "${PORT}" -u 1 ${RECOVERY_ARG} ${VERBOSE_ARG} || RC=$?
+	else
+		"${UPDATE_BIN}" -f "${FW_FILE}" -p "${PORT}" -u 1 ${RECOVERY_ARG} >/dev/null 2>&1 || RC=$?
+	fi
+
+	if [ "${RC}" -ne 0 ]; then
+		exit_error "Firmware update FAILED (exit code: ${RC})" "${RC}"
+	fi
+
+	log_info "Firmware update SUCCESS"
+}
+
+parse_args "$@"
+require_prereqs
+
+stop_services
+
+# Always try to restore services even if the update fails.
+trap 'start_services' EXIT
+run_update
--- a/meta-digi-dey/recipes-connectivity/glinswup/glinswup-plsx3_1.0.5.bb
+++ b/meta-digi-dey/recipes-connectivity/glinswup/glinswup-plsx3_1.0.5.bb
@ -0,0 +1,30 @@
+# Copyright (C) 2026, Digi International Inc.
+
+SUMMARY = "Cinterion PLSx3 firmware update tool (glinswup) + helper script"
+SECTION = "console/tools"
+LICENSE = "CLOSED"
+
+PKGNAME = "glinswup_PLSx3"
+
+# ARM tarball
+SRC_URI:arm += "${DIGI_PKG_SRC}/${PKGNAME}-${PV}-arm.tar.gz;name=arm"
+SRC_URI[arm.md5sum] = "e89f7e3e9cc97f4df51366d4a93e7542"
+SRC_URI[arm.sha256sum] = "ca274365c244c3b43ce3e2e3b7b13c70a4104645673c7324a4cbc18132e28a86"
+
+# AARCH64 tarball
+SRC_URI:aarch64 += "${DIGI_PKG_SRC}/${PKGNAME}-${PV}-aarch64.tar.gz;name=aarch64"
+SRC_URI[aarch64.md5sum] = "4e44cd327ce7fe430e1d60d66ae7528e"
+SRC_URI[aarch64.sha256sum] = "3f70500a4c6c280c3c42259fa51abc565fb76c97d4cea64aed36a3539b168c38"
+
+SRC_URI += " file://pls3_fw_update.sh"
+
+S = "${WORKDIR}/${PKGNAME}_${PV}"
+
+do_install:append() {
+	install -d ${D}${sbindir}
+	install -m 0755 ${WORKDIR}/pls3_fw_update.sh ${D}${sbindir}/pls3_fw_update.sh
+}
+
+inherit bin_package
+
+INSANE_SKIP:${PN} = "already-stripped"
--- a/meta-digi-dey/recipes-connectivity/openssl/openssl/0001-e_devcrypto-add-func-ptr-for-init-do-ctrl.patch
+++ b/meta-digi-dey/recipes-connectivity/openssl/openssl/0001-e_devcrypto-add-func-ptr-for-init-do-ctrl.patch
@ -1,7 +1,6 @@
-From d6c1bf7031cbd96c1d0dec589f318ad942107d23 Mon Sep 17 00:00:00 2001
 From: Pankaj Gupta <pankaj.gupta@nxp.com>
 Date: Tue, 18 Jan 2022 17:37:37 +0530
-Subject: [PATCH 1/2] e_devcrypto: add func ptr for init, do, ctrl
+Subject: [PATCH] e_devcrypto: add func ptr for init, do, ctrl

 In engine "devcrypto", as part prepare_cipher_methods()
 - Added function pointer for init, do, ctrl and
@ -12,18 +11,17 @@ In engine "devcrypto", as part prepare_cipher_methods()
 Upstream-Status: Pending [i.MX, Layerscape specific]
 Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
 ---
- engines/e_devcrypto.c | 34 ++++++++++++++++++++++++----------
- 1 file changed, 24 insertions(+), 10 deletions(-)
+ engines/e_devcrypto.c | 31 ++++++++++++++++++++++++-------
+ 1 file changed, 24 insertions(+), 7 deletions(-)

 diff --git a/engines/e_devcrypto.c b/engines/e_devcrypto.c
-index fa01317db5..eb56baec19 100644
+index f66c7f1c1cf4..a46196b9f4aa 100644
 --- a/engines/e_devcrypto.c
 +++ b/engines/e_devcrypto.c
-@@ -408,7 +408,11 @@ static int known_cipher_nids_amount = -1; /* -1 indicates not yet initialised */
- static EVP_CIPHER *known_cipher_methods[OSSL_NELEM(cipher_data)] = { NULL, };
+@@ -403,6 +403,11 @@ static EVP_CIPHER *known_cipher_methods[OSSL_NELEM(cipher_data)] = {
+ };
 static int selected_ciphers[OSSL_NELEM(cipher_data)];
 static struct driver_info_st cipher_driver_info[OSSL_NELEM(cipher_data)];
-
 +int (*init)(EVP_CIPHER_CTX *ctx, const unsigned char *key,
 +                const unsigned char *iv, int enc);
 +int (*do_cipher)(EVP_CIPHER_CTX *ctx, unsigned char *out,
@ -32,7 +30,7 @@ index fa01317db5..eb56baec19 100644
 
 static int devcrypto_test_cipher(size_t cipher_data_index)
 {
-@@ -427,6 +431,7 @@ static void prepare_cipher_methods(void)
+@@ -421,6 +426,7 @@ static void prepare_cipher_methods(void)
     size_t i;
     session_op_t sess;
     unsigned long cipher_mode;
@ -40,14 +38,14 @@ index fa01317db5..eb56baec19 100644
 #ifdef CIOCGSESSION2
     struct crypt_find_op fop;
     enum devcrypto_accelerated_t accelerated;
-@@ -438,16 +443,26 @@ static void prepare_cipher_methods(void)
+@@ -432,16 +438,26 @@ static void prepare_cipher_methods(void)
 
     memset(&sess, 0, sizeof(sess));
     sess.key = (void *)"01234567890123456789012345678901234567890123456789";
 +    sess.mackey = (void *)"123456789ABCDEFGHIJKLMNO";
 
     for (i = 0, known_cipher_nids_amount = 0;
-          i < OSSL_NELEM(cipher_data); i++) {
+         i < OSSL_NELEM(cipher_data); i++) {
 
         selected_ciphers[i] = 1;
 +
@ -67,7 +65,7 @@ index fa01317db5..eb56baec19 100644
 #ifdef CIOCGSESSION2
         /*
          * When using CIOCGSESSION2, first try to allocate a hardware
-@@ -474,6 +489,10 @@ static void prepare_cipher_methods(void)
+@@ -468,6 +484,10 @@ static void prepare_cipher_methods(void)
 
         cipher_mode = cipher_data[i].flags & EVP_CIPH_MODE;
 
@ -75,30 +73,25 @@ index fa01317db5..eb56baec19 100644
 +                                              ctr_do_cipher :
 +                                              cipher_do_cipher);
 +
-         if ((known_cipher_methods[i] =
-                  EVP_CIPHER_meth_new(cipher_data[i].nid,
-                                      cipher_mode == EVP_CIPH_CTR_MODE ? 1 :
-@@ -482,16 +501,11 @@ static void prepare_cipher_methods(void)
+         if ((known_cipher_methods[i] = EVP_CIPHER_meth_new(cipher_data[i].nid,
+                  cipher_mode == EVP_CIPH_CTR_MODE ? 1 : cipher_data[i].blocksize,
+                  cipher_data[i].keylen))
+@@ -475,14 +495,11 @@ static void prepare_cipher_methods(void)
             || !EVP_CIPHER_meth_set_iv_length(known_cipher_methods[i],
-                                               cipher_data[i].ivlen)
+                 cipher_data[i].ivlen)
             || !EVP_CIPHER_meth_set_flags(known_cipher_methods[i],
-                                          cipher_data[i].flags
-                                          | EVP_CIPH_CUSTOM_COPY
-                                          | EVP_CIPH_CTRL_INIT
-                                          | EVP_CIPH_FLAG_DEFAULT_ASN1)
+-                cipher_data[i].flags
+-                    | EVP_CIPH_CUSTOM_COPY
+-                    | EVP_CIPH_CTRL_INIT
+-                    | EVP_CIPH_FLAG_DEFAULT_ASN1)
 -            || !EVP_CIPHER_meth_set_init(known_cipher_methods[i], cipher_init)
 +                                          flags)
 +            || !EVP_CIPHER_meth_set_init(known_cipher_methods[i], init)
             || !EVP_CIPHER_meth_set_do_cipher(known_cipher_methods[i],
-                                     cipher_mode == EVP_CIPH_CTR_MODE ?
-                                              ctr_do_cipher :
-                                              cipher_do_cipher)
+-                cipher_mode == EVP_CIPH_CTR_MODE ? ctr_do_cipher : cipher_do_cipher)
 -            || !EVP_CIPHER_meth_set_ctrl(known_cipher_methods[i], cipher_ctrl)
 +                                              do_cipher)
 +            || !EVP_CIPHER_meth_set_ctrl(known_cipher_methods[i], ctrl)
             || !EVP_CIPHER_meth_set_cleanup(known_cipher_methods[i],
-                                             cipher_cleanup)
+                 cipher_cleanup)
             || !EVP_CIPHER_meth_set_impl_ctx_size(known_cipher_methods[i],
--
-2.17.1
-
--- a/meta-digi-dey/recipes-connectivity/openssl/openssl/0002-e_devcrypto-add-support-for-TLS1.2-algorithms-offloa.patch
+++ b/meta-digi-dey/recipes-connectivity/openssl/openssl/0002-e_devcrypto-add-support-for-TLS1.2-algorithms-offloa.patch
@ -1,4 +1,3 @@
-From f674b2f81a18af2146291eda1bbf60d6f71b2935 Mon Sep 17 00:00:00 2001
 From: Pankaj Gupta <pankaj.gupta@nxp.com>
 Date: Tue, 18 Jan 2022 17:38:11 +0530
 Subject: [PATCH] e_devcrypto: add support for TLS1.2 algorithms offload
@ -17,13 +16,12 @@ Fix: Remove the support for TLS1.0.

 Upstream-Status: Pending [i.MX, Layerscape specific]
 Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
-
 ---
 engines/e_devcrypto.c | 273 ++++++++++++++++++++++++++++++++++++++----
 1 file changed, 249 insertions(+), 24 deletions(-)

 diff --git a/engines/e_devcrypto.c b/engines/e_devcrypto.c
-index 02f3abc..8529bac 100644
+index a46196b9f4aa..1d21dffabfbf 100644
 --- a/engines/e_devcrypto.c
 +++ b/engines/e_devcrypto.c
@@ -28,6 +28,7 @@
@ -33,11 +31,11 @@ index 02f3abc..8529bac 100644
 +#define TLS1_1_VERSION  0x0302
 
 #if CRYPTO_ALGORITHM_MIN < CRYPTO_ALGORITHM_MAX
- # define CHECK_BSD_STYLE_MACROS
-@@ -107,10 +108,14 @@ struct cipher_ctx {
+ #define CHECK_BSD_STYLE_MACROS
+@@ -108,10 +109,14 @@ struct cipher_ctx {
     session_op_t sess;
-     int op;                      /* COP_ENCRYPT or COP_DECRYPT */
-     unsigned long mode;          /* EVP_CIPH_*_MODE */
+     int op; /* COP_ENCRYPT or COP_DECRYPT */
+     unsigned long mode; /* EVP_CIPH_*_MODE */
 +    unsigned char *aad;
 +    unsigned int aad_len;
 +    unsigned int len;
@ -49,7 +47,7 @@ index 02f3abc..8529bac 100644
 };
 
 static const struct cipher_data_st {
-@@ -120,49 +125,66 @@ static const struct cipher_data_st {
+@@ -121,49 +126,66 @@ static const struct cipher_data_st {
     int ivlen;
     int flags;
     int devcryptoid;
@ -99,7 +97,7 @@ index 02f3abc..8529bac 100644
 +    { NID_aes_192_ctr, 16, 192 / 8, 16, EVP_CIPH_CTR_MODE, CRYPTO_AES_CTR, 0 },
 +    { NID_aes_256_ctr, 16, 256 / 8, 16, EVP_CIPH_CTR_MODE, CRYPTO_AES_CTR, 0 },
 #endif
- #if 0                            /* Not yet supported */
+ #if 0 /* Not yet supported */
 -    { NID_aes_128_xts, 16, 128 / 8 * 2, 16, EVP_CIPH_XTS_MODE, CRYPTO_AES_XTS },
 -    { NID_aes_256_xts, 16, 256 / 8 * 2, 16, EVP_CIPH_XTS_MODE, CRYPTO_AES_XTS },
 +    { NID_aes_128_xts, 16, 128 / 8 * 2, 16, EVP_CIPH_XTS_MODE, CRYPTO_AES_XTS, 0 },
@ -113,7 +111,7 @@ index 02f3abc..8529bac 100644
 +    { NID_aes_192_ecb, 16, 192 / 8, 0, EVP_CIPH_ECB_MODE, CRYPTO_AES_ECB, 0 },
 +    { NID_aes_256_ecb, 16, 256 / 8, 0, EVP_CIPH_ECB_MODE, CRYPTO_AES_ECB, 0 },
 #endif
- #if 0                            /* Not yet supported */
+ #if 0 /* Not yet supported */
 -    { NID_aes_128_gcm, 16, 128 / 8, 16, EVP_CIPH_GCM_MODE, CRYPTO_AES_GCM },
 -    { NID_aes_192_gcm, 16, 192 / 8, 16, EVP_CIPH_GCM_MODE, CRYPTO_AES_GCM },
 -    { NID_aes_256_gcm, 16, 256 / 8, 16, EVP_CIPH_GCM_MODE, CRYPTO_AES_GCM },
@ -127,18 +125,18 @@ index 02f3abc..8529bac 100644
 #endif
 #ifndef OPENSSL_NO_CAMELLIA
     { NID_camellia_128_cbc, 16, 128 / 8, 16, EVP_CIPH_CBC_MODE,
-      CRYPTO_CAMELLIA_CBC },
-+      CRYPTO_CAMELLIA_CBC, 0 },
+-        CRYPTO_CAMELLIA_CBC },
+        CRYPTO_CAMELLIA_CBC, 0 },
     { NID_camellia_192_cbc, 16, 192 / 8, 16, EVP_CIPH_CBC_MODE,
-      CRYPTO_CAMELLIA_CBC },
-+      CRYPTO_CAMELLIA_CBC, 0 },
+-        CRYPTO_CAMELLIA_CBC },
+        CRYPTO_CAMELLIA_CBC, 0 },
     { NID_camellia_256_cbc, 16, 256 / 8, 16, EVP_CIPH_CBC_MODE,
-      CRYPTO_CAMELLIA_CBC },
-+      CRYPTO_CAMELLIA_CBC, 0 },
+-        CRYPTO_CAMELLIA_CBC },
+        CRYPTO_CAMELLIA_CBC, 0 },
 #endif
 };
 
-@@ -197,6 +219,193 @@ static const struct cipher_data_st *get_cipher_data(int nid)
+@@ -198,6 +220,193 @@ static const struct cipher_data_st *get_cipher_data(int nid)
     return &cipher_data[get_cipher_data_index(nid)];
 }
 
@ -332,7 +330,7 @@ index 02f3abc..8529bac 100644
 /*
  * Following are the three necessary functions to map OpenSSL functionality
  * with cryptodev.
-@@ -463,6 +672,7 @@ static void prepare_cipher_methods(void)
+@@ -457,6 +666,7 @@ static void prepare_cipher_methods(void)
          */
         sess.cipher = cipher_data[i].devcryptoid;
         sess.keylen = cipher_data[i].keylen;
@ -340,7 +338,7 @@ index 02f3abc..8529bac 100644
 
 #ifdef CIOCGSESSION2
         /*
-@@ -494,6 +704,15 @@ static void prepare_cipher_methods(void)
+@@ -488,6 +698,15 @@ static void prepare_cipher_methods(void)
                                               ctr_do_cipher :
                                               cipher_do_cipher);
 
@ -353,10 +351,10 @@ index 02f3abc..8529bac 100644
 +                ctrl = cryptodev_cbc_hmac_sha1_ctrl;
 +                flags = cipher_data[i].flags;
 +        }
-         if ((known_cipher_methods[i] =
-                  EVP_CIPHER_meth_new(cipher_data[i].nid,
-                                      cipher_mode == EVP_CIPH_CTR_MODE ? 1 :
-@@ -538,11 +757,17 @@ static void prepare_cipher_methods(void)
+         if ((known_cipher_methods[i] = EVP_CIPHER_meth_new(cipher_data[i].nid,
+                  cipher_mode == EVP_CIPH_CTR_MODE ? 1 : cipher_data[i].blocksize,
+                  cipher_data[i].keylen))
+@@ -529,10 +748,16 @@ static void prepare_cipher_methods(void)
             }
 #endif /* CIOCGSESSINFO */
         }
@ -370,8 +368,7 @@ index 02f3abc..8529bac 100644
         ioctl(cfd, CIOCFSESSION, &sess.ses);
 -        if (devcrypto_test_cipher(i)) {
 +        if (devcrypto_test_cipher(i))
-             known_cipher_nids[known_cipher_nids_amount++] =
-                 cipher_data[i].nid;
+             known_cipher_nids[known_cipher_nids_amount++] = cipher_data[i].nid;
 -        }
     }
 }
--- a/meta-digi-dey/recipes-connectivity/openssl/openssl/0003-Set-algorithm-id-before-generating-the-EC-key.patch
+++ b/meta-digi-dey/recipes-connectivity/openssl/openssl/0003-Set-algorithm-id-before-generating-the-EC-key.patch
@ -1,20 +1,18 @@
-From 27e4bd35a42287248bd5253836c265dd555b1ee2 Mon Sep 17 00:00:00 2001
 From: Ilie Halip <ilie.halip@nxp.com>
-Date: Wed, 10 Sep 2025 08:46:50 +0200
-Subject: [PATCH] [PATCH] Set "algorithm-id" before generating the EC key.
+Date: Wed, 12 Mar 2025 20:57:10 +0200
+Subject: [PATCH] Set "algorithm-id" before generating the EC key.

 Upstream-Status: Pending
-
 Signed-off-by: Ilie Halip <ilie.halip@nxp.com>
 ---
 ssl/s3_lib.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

 diff --git a/ssl/s3_lib.c b/ssl/s3_lib.c
-index d6ed169f39..68938bb8fb 100644
+index 0e1445b38fb7..62f7409cb2aa 100644
 --- a/ssl/s3_lib.c
 +++ b/ssl/s3_lib.c
-@@ -4742,6 +4742,30 @@ int ssl_generate_master_secret(SSL_CONNECTION *s, unsigned char *pms,
+@@ -5274,6 +5274,30 @@ err:
     return ret;
 }
 
@ -45,7 +43,7 @@ index d6ed169f39..68938bb8fb 100644
 /* Generate a private key from parameters */
 EVP_PKEY *ssl_generate_pkey(SSL_CONNECTION *s, EVP_PKEY *pm)
 {
-@@ -4756,6 +4780,9 @@ EVP_PKEY *ssl_generate_pkey(SSL_CONNECTION *s, EVP_PKEY *pm)
+@@ -5288,6 +5312,9 @@ EVP_PKEY *ssl_generate_pkey(SSL_CONNECTION *s, EVP_PKEY *pm)
         goto err;
     if (EVP_PKEY_keygen_init(pctx) <= 0)
         goto err;
@ -55,7 +53,7 @@ index d6ed169f39..68938bb8fb 100644
     if (EVP_PKEY_keygen(pctx, &pkey) <= 0) {
         EVP_PKEY_free(pkey);
         pkey = NULL;
-@@ -4794,6 +4821,9 @@ EVP_PKEY *ssl_generate_pkey_group(SSL_CONNECTION *s, uint16_t id)
+@@ -5326,6 +5353,9 @@ EVP_PKEY *ssl_generate_pkey_group(SSL_CONNECTION *s, uint16_t id)
         SSLfatal(s, SSL_AD_INTERNAL_ERROR, ERR_R_EVP_LIB);
         goto err;
     }
@ -65,6 +63,3 @@ index d6ed169f39..68938bb8fb 100644
     if (EVP_PKEY_keygen(pctx, &pkey) <= 0) {
         SSLfatal(s, SSL_AD_INTERNAL_ERROR, ERR_R_EVP_LIB);
         EVP_PKEY_free(pkey);
-- 
-2.43.0
-
--- a/meta-digi-dey/recipes-connectivity/openssl/openssl/openssl-3.0-add-Kernel-TLS-configuration.patch
+++ b/meta-digi-dey/recipes-connectivity/openssl/openssl/openssl-3.0-add-Kernel-TLS-configuration.patch
@ -1,4 +1,3 @@
-From 24254454e5f5fc503b5e4cc1fa8c6d9b1a3ae9ba Mon Sep 17 00:00:00 2001
 From: Gaurav Jain <gaurav.jain@nxp.com>
 Date: Wed, 19 Jan 2022 15:45:29 +0530
 Subject: [PATCH] openssl 3.0: add Kernel TLS configuration
@ -10,7 +9,7 @@ Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
 1 file changed, 9 insertions(+)

 diff --git a/apps/openssl.cnf b/apps/openssl.cnf
-index 03330e0120..ec18df388e 100644
+index abace0ea7f1c..f4d5ec19de27 100644
 --- a/apps/openssl.cnf
 +++ b/apps/openssl.cnf
@@ -30,6 +30,15 @@ oid_section = new_oids
@ -29,6 +28,3 @@ index 03330e0120..ec18df388e 100644
 [ new_oids ]
 # We can add new OIDs in here for use by 'ca', 'req' and 'ts'.
 # Add a simple OID like this:
-- 
-2.25.1
-
--- a/meta-digi-dey/recipes-connectivity/openssl/openssl_3.5.%.bbappend
+++ b/meta-digi-dey/recipes-connectivity/openssl/openssl_3.5.%.bbappend
@ -1,4 +1,4 @@
-# Copyright (C) 2022,2026 Digi International Inc.
+# Copyright (C) 2022-2026 Digi International Inc.

 FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"

@ -6,7 +6,7 @@ SRC_URI += "file://openssl-3.0-add-Kernel-TLS-configuration.patch \
            file://0001-e_devcrypto-add-func-ptr-for-init-do-ctrl.patch \
            file://0002-e_devcrypto-add-support-for-TLS1.2-algorithms-offloa.patch \
            file://0003-Set-algorithm-id-before-generating-the-EC-key.patch \
-            file://0004-Amend-the-design-of-AlgorithmIdentifier-parameter-pa.patch"
+           "

 PACKAGECONFIG:append:imx-nxp-bsp = " cryptodev-linux"

--- a/meta-digi-dey/recipes-core/systemd/systemd-conf/logind.conf-digi
+++ b/meta-digi-dey/recipes-core/systemd/systemd-conf/logind.conf-digi
@ -1,3 +1,3 @@
 [Login]
-HandlePowerKey=suspend
-HandlePowerKeyLongPress=poweroff
+HandlePowerKey=##HANDLEPOWERKEY##
+HandlePowerKeyLongPress=##HANDLEPOWERKEYLONGPRESS##
--- a/meta-digi-dey/recipes-core/systemd/systemd-conf_%.bbappend
+++ b/meta-digi-dey/recipes-core/systemd/systemd-conf_%.bbappend
@ -20,8 +20,12 @@ do_install:append() {

 do_install:append:stm32mpcommon() {
 	install -D -m0644 ${WORKDIR}/logind.conf-digi ${D}${systemd_unitdir}/logind.conf.d/01-${PN}.conf
+	sed -i -e 's,##HANDLEPOWERKEY##,${LOGIND_HANDLE_POWER_KEY},g' \
+	       -e 's,##HANDLEPOWERKEYLONGPRESS##,${LOGIND_HANDLE_POWER_KEY_LONGPRESS},g' ${D}${systemd_unitdir}/logind.conf.d/01-${PN}.conf
 }

 do_install:append:ccimx9() {
 	install -D -m0644 ${WORKDIR}/logind.conf-digi ${D}${systemd_unitdir}/logind.conf.d/01-${PN}.conf
+	sed -i -e 's,##HANDLEPOWERKEY##,${LOGIND_HANDLE_POWER_KEY},g' \
+	       -e 's,##HANDLEPOWERKEYLONGPRESS##,${LOGIND_HANDLE_POWER_KEY_LONGPRESS},g' ${D}${systemd_unitdir}/logind.conf.d/01-${PN}.conf
 }
--- a/meta-digi-dey/recipes-digi/dey-examples/dey-examples-src.inc
+++ b/meta-digi-dey/recipes-digi/dey-examples/dey-examples-src.inc
@ -1,13 +1,11 @@
 # Copyright (C) 2019-2025, Digi International Inc.

-SRCBRANCH = "master"
+SRCBRANCH = "dey-5.0/maint"
 SRCREV = "${AUTOREV}"

 DEY_EXAMPLES_STASH = "${DIGI_MTK_GIT}/dey/dey-examples.git;protocol=ssh"
 DEY_EXAMPLES_GITHUB = "${DIGI_GITHUB_GIT}/dey-examples.git;protocol=https"
-DEY_EXAMPLES_ECCEE = "https://git.eccee.com/Digi/dey-examples.git;protocol=https"

-# 使用条件判断选择仓库
-DEY_EXAMPLES_GIT_URI ?= "${@oe.utils.conditional('USE_ECCEE', '1', '${DEY_EXAMPLES_ECCEE}', oe.utils.conditional('DIGI_INTERNAL_GIT', '1', '${DEY_EXAMPLES_STASH}', '${DEY_EXAMPLES_GITHUB}', d), d)}"
+DEY_EXAMPLES_GIT_URI ?= "${@oe.utils.conditional('DIGI_INTERNAL_GIT', '1' , '${DEY_EXAMPLES_STASH}', '${DEY_EXAMPLES_GITHUB}', d)}"

 SRC_URI = "${DEY_EXAMPLES_GIT_URI};branch=${SRCBRANCH}"
--- a/meta-digi-dey/recipes-digi/libdigiapix/libdigiapix_git.bb
+++ b/meta-digi-dey/recipes-digi/libdigiapix/libdigiapix_git.bb
@ -6,7 +6,7 @@ SECTION = "libs"
 LICENSE = "ISC"
 LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/ISC;md5=f3b90e78ea0cffb20bf5cca7947a896d"

-SRCBRANCH ?= "master"
+SRCBRANCH ?= "dey-5.0/maint"
 SRCREV = "${AUTOREV}"

 LIBDIGIAPIX_URI_STASH = "${DIGI_MTK_GIT}/dey/libdigiapix.git;protocol=ssh"
Author	SHA1	Message	Date
peyoot	e3466c32a3	updat	2026-06-04 00:13:25 -05:00
peyoot	edc9431c78	updat	2026-06-04 00:03:41 -05:00
peyoot	596d33c33c	update ,fix branch name to dey5.0/maint	2026-06-03 19:20:59 -05:00
peyoot	f49c068fb3	update openssl	2026-06-03 04:34:45 -05:00
peyoot	cb57728d8f	update tf-a-stm32mp bbapend srcurl	2026-06-02 19:36:00 -05:00
peyoot	3eccd2b280	update uboot url	2026-06-02 19:22:51 -05:00
peyoot	0758b16054	fix optee-os-stm32mp digi fork branch name issue	2026-06-01 18:48:21 -05:00
peyoot	23b0202806	update to fix linux branch name	2026-06-01 17:59:07 -05:00
peyoot	95a8310101	fix trustfence-sign-tools src branch name issue	2026-06-01 17:37:33 -05:00
peyoot	56184bf744	fix branch name issue in dey-example-src.inc	2026-06-01 17:23:47 -05:00
Hector Palacios	5b18593bfd	ccimx95-dvk: remove unneeded overlays for SMARC DVK The SMARC module uses both Ethernet controllers, so ENET2 is no longer optional. The DVK does no longer have a MikroBUS connector so the Mikro-E overlays are no longer needed. Signed-off-by: Hector Palacios <hector.palacios@digi.com>	2026-03-17 12:03:19 +01:00
Hector Palacios	77dde9f8f1	ccimx95: adapt systemd power key events for SMARC module For the ccimx95 SMARC module, the power button is connected to the MCA, and the MCA is the one that generates the signal to the ON_OFF input. In the SMARC design, the power button is dedicated (there is a different button for standby) so we want short key presses to be treated as a poweroff event right away. We also want systemd to ignore long presses, as these are absorbed by the MCA firmware to forcefully power off the PMIC. When SMARC is disabled, use the default behavior: - short press: suspend - long press: graceful poweroff Signed-off-by: Hector Palacios <hector.palacios@digi.com>	2026-03-17 12:01:09 +01:00
Hector Palacios	6b9d2e4114	systemd-conf: machine-configurable power key behavior Use placeholders and machine-configurable variables to determine systemd behavior when receiving power key events. By default, these are: - short press: suspend - long press: graceful poweroff Signed-off-by: Hector Palacios <hector.palacios@digi.com>	2026-03-17 12:00:47 +01:00
Hector Palacios	ebe606d9ac	ccimx95: enable SMARC module by default and conditionalize 'mca' feature Signed-off-by: Hector Palacios <hector.palacios@digi.com>	2026-03-17 11:17:20 +01:00
Javier Viguera	cf8d771390	imx-system-manager: use git repository and drop local patches Remove the local ccimx95 patch series from imx-system-manager bbappend and fetch the DEY-specific changes directly from the Digi fork. https://onedigi.atlassian.net/browse/DEL-10009 Signed-off-by: Javier Viguera <javier.viguera@digi.com>	2026-03-13 14:56:11 +01:00
Javier Viguera	fe54927861	imx-oei: use git repository and drop local patches Remove the local ccimx95 patch series from imx-oei bbappend and fetch the DEY-specific changes directly from the Digi fork. https://onedigi.atlassian.net/browse/DEL-10009 Signed-off-by: Javier Viguera <javier.viguera@digi.com>	2026-03-13 14:55:56 +01:00
Javier Viguera	3f4a8a410c	neo-ipa-uguzzi: add package for NXP's Neo ISP The neo-ipa-uguzzi package provides uGuzzi IPA (image processing algorithms) for NXP's Neo ISP on the ccimx95. The recipe is backported from NXP’s lf-6.12.49_2.2.0 release, and enabled at runtime as part of the gstreamer packagegroup. https://onedigi.atlassian.net/browse/DEL-10003 Signed-off-by: Javier Viguera <javier.viguera@digi.com>	2026-03-09 16:51:02 +01:00
Francisco Gil	3b9a8698a7	xbee: cellular: add PLSx3 firmware updater recipe and helper script Add new `glinswup-PLSx3_1.0.5.bb` binary recipe to package the Cinterion PLSx3 firmware update tool. Include `pls3_fw_update.sh` helper script to: - validate input firmware file and modem port - stop modem-related services before update - run `glinswup_PLSx3` firmware update - restore services on exit https://onedigi.atlassian.net/browse/DEL-9989 Signed-off-by: Francisco Gil <francisco.gilmartinez@digi.com>	2026-03-09 15:54:01 +01:00
Javier Viguera	35dd3ec6c9	imx-oei: add patch with support for 2GiB ram https://onedigi.atlassian.net/browse/DUB-1117 Signed-off-by: Javier Viguera <javier.viguera@digi.com>	2026-03-06 14:49:00 +01:00
Javier Viguera	d5fe033b46	imx-system-manager: add patch with SM fix for 2GiB DDR The system manager was not reporting (via SCMI) the size for the 2GiB ram. This patch is a backport of a newer version of the SM. https://onedigi.atlassian.net/browse/DUB-1117 Signed-off-by: Javier Viguera <javier.viguera@digi.com>	2026-03-06 14:49:00 +01:00