imx-atf: add patch to fix the ccimx8mn hanging on suspend/resume

The LPDDR4 retention code is executed as part of the suspend/resume process.
When resuming, this code writes to a register that doesn't exist on the
i.MX8MN, causing the system to freeze before control is returned to Linux.

Add a patch that introduces a compile-time check for the SoC type to avoid
performing the write operation on the i.MX8MN.

https://jira.digi.com/browse/DEL-6914

Signed-off-by: Gabriel Valcazar <gabriel.valcazar@digi.com>
This commit is contained in:
Gabriel Valcazar 2020-01-07 16:07:11 +01:00 committed by Arturo Buzarra
parent cdd1ca5ce7
commit b7b7d0110b
2 changed files with 30 additions and 1 deletions

View File

@ -0,0 +1,26 @@
From: Jacky Bai <ping.bai@nxp.com>
Date: Wed, 23 Oct 2019 13:44:28 +0800
Subject: [PATCH] plat: imx8m: update the lpddr4 retention flow for imx8mn
for i.MX8MN, it can only support 16bit DDR, so
it is not necessary to config the DDR_SS_GPR register.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
plat/imx/common/imx8m/lpddr4_retention.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/plat/imx/common/imx8m/lpddr4_retention.c b/plat/imx/common/imx8m/lpddr4_retention.c
index 8cc44c8..dbec3d5 100644
--- a/plat/imx/common/imx8m/lpddr4_retention.c
+++ b/plat/imx/common/imx8m/lpddr4_retention.c
@@ -184,7 +184,9 @@ void lpddr4_exit_retention(void)
/* before write Dynamic reg, sw_done should be 0 */
mmio_write_32(DDRC_SWCTL(0), 0x00000000);
+#if !defined(PLAT_imx8mn)
mmio_write_32(DDRC_DDR_SS_GPR0, 0x01); /*LPDDR4 mode */
+#endif
mmio_write_32(DDRC_DFIMISC(0), 0x00000000);
/* dram phy re-init */

View File

@ -15,7 +15,10 @@ SRCBRANCH = "imx_4.14.98_2.2.0"
SRC_URI = "${ATF_SRC};branch=${SRCBRANCH}"
SRCREV = "1355c5d12d75c9c7bdd08826796096bab519b3d5"
SRC_URI_append_ccimx8mn = " file://0001-imx8mn-Disable-M7-debug-console.patch"
SRC_URI_append_ccimx8mn = " \
file://0001-imx8mn-Disable-M7-debug-console.patch \
file://0002-plat-imx8m-update-the-lpddr4-retention-flow-for-imx8.patch \
"
S = "${WORKDIR}/git"